yosys 0.5.0-1 source package in Ubuntu

Changelog

yosys (0.5.0-1) unstable; urgency=low


  * New upstream release
  * Added d/watch
  * Updated copyright years in d/copyright
  * Changed dependency from tcl8.5-dev to tcl-dev
  * Added d/gbp.conf
  * Added link from /usr/bin/yosys-abc to /usr/bin/berkeley-abc
    - Also added man page for yosys-abc
  * Fixed paths returned by yosys-config
    - fix included in 04_installpath.patch

 -- Ruben Undheim <email address hidden>  Mon, 09 Feb 2015 20:37:38 +0100

Upload details

Uploaded by:
Debian Science Team
Uploaded to:
Sid
Original maintainer:
Debian Science Team
Architectures:
any
Section:
misc
Urgency:
Low Urgency

See full publishing history Publishing

Series Pocket Published Component Section

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File Size SHA-256 Checksum
yosys_0.5.0-1.dsc 1.9 KiB 356518774d1b113c342b769fc1a88bcbf9babef53c1053a9b16fad6cb11c6777
yosys_0.5.0.orig.tar.gz 755.9 KiB f2adb8115f95e9613838fc545bad94dcfe7c8afcfb092595c1b6996f81eadfac
yosys_0.5.0-1.debian.tar.xz 7.4 KiB a73f86d0d374ecf128b8e9da2e576799e84bc18f6876c5cac694e5c7e2c0e8c5

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Binary packages built by this source

yosys: Framework for Verilog RTL synthesis

 This is a framework for Verilog RTL synthesis. It currently has extensive
 Verilog-2005 support and provides a basic set of synthesis algorithms for
 various application domains.
 .
 Yosys can be adapted to perform any synthesis job by combining the existing
 passes (algorithms) using synthesis scripts and adding additional passes as
 needed by extending the yosys C++ code base.

yosys-dbgsym: debug symbols for package yosys

 This is a framework for Verilog RTL synthesis. It currently has extensive
 Verilog-2005 support and provides a basic set of synthesis algorithms for
 various application domains.
 .
 Yosys can be adapted to perform any synthesis job by combining the existing
 passes (algorithms) using synthesis scripts and adding additional passes as
 needed by extending the yosys C++ code base.