yosys 0.23-3 source package in Ubuntu
Changelog
yosys (0.23-3) unstable; urgency=medium * Add patch to fix blhc CLFAGS warning * Fix d/rules sh syntax -- Daniel Gröber <email address hidden> Sun, 13 Nov 2022 23:34:50 +0100
Upload details
- Uploaded by:
- Debian Science Team
- Uploaded to:
- Sid
- Original maintainer:
- Debian Science Team
- Architectures:
- any all
- Section:
- misc
- Urgency:
- Medium Urgency
See full publishing history Publishing
| Series | Published | Component | Section |
|---|
Downloads
| File | Size | SHA-256 Checksum |
|---|---|---|
| yosys_0.23-3.dsc | 2.5 KiB | 4b0672d53cc06442919126dbe6e34bc93dcadc8dead7116677b3c63fcd6d9c98 |
| yosys_0.23.orig.tar.gz | 2.3 MiB | ec982a9393b3217deecfbd3cf9a64109b85310a949e46a51cf2e07fba1071aeb |
| yosys_0.23-3.debian.tar.xz | 17.0 KiB | 203ad1e13e222a70fe8c5cac1f5511ab4f47569348368464a8d1222cac63147f |
Available diffs
- diff from 0.19-1 to 0.23-3 (118.8 KiB)
- diff from 0.23-1 to 0.23-3 (1.0 KiB)
No changes file available.
Binary packages built by this source
- yosys: Framework for Verilog RTL synthesis
This is a framework for Verilog RTL synthesis. It currently has extensive
Verilog-2005 support and provides a basic set of synthesis algorithms for
various application domains.
.
Yosys can be adapted to perform any synthesis job by combining the existing
passes (algorithms) using synthesis scripts and adding additional passes as
needed by extending the yosys C++ code base.
- yosys-dbgsym: debug symbols for yosys
- yosys-dev: Framework for Verilog RTL synthesis (development files)
Yosys is a framework for Verilog RTL synthesis. It currently has extensive
Verilog-2005 support and provides a basic set of synthesis algorithms for
various application domains.
.
Yosys can be adapted to perform any synthesis job by combining the existing
passes (algorithms) using synthesis scripts and adding additional passes as
needed by extending the yosys C++ code base.
.
This package contains the headers and programs needed to build yosys plugins.
- yosys-doc: Documentation for Yosys
Yosys is a framework for Verilog RTL synthesis. It currently has extensive
Verilog-2005 support and provides a basic set of synthesis algorithms for
various application domains.
.
Yosys can be adapted to perform any synthesis job by combining the existing
passes (algorithms) using synthesis scripts and adding additional passes as
needed by extending the yosys C++ code base.
.
This package contains the manual.
