yosys 0.19-1 source package in Ubuntu
Changelog
yosys (0.19-1) unstable; urgency=medium [ Steffen Moeller ] * d/control: Bumped standard to 4.6.1 * d/u/metadata: Added SciCrunch RRID:SCR_022549 [ Daniel Gröber ] * New upstream version 0.19 -- Daniel Gröber <email address hidden> Sat, 30 Jul 2022 17:26:45 +0200
Upload details
- Uploaded by:
- Debian Science Team
- Uploaded to:
- Sid
- Original maintainer:
- Debian Science Team
- Architectures:
- alpha amd64 arm64 armel armhf hurd i386 ia64 kfreebsd-amd64 kfreebsd-i386 m68k mipsel ppc64el riscv64 sh4 x32 all
- Section:
- misc
- Urgency:
- Medium Urgency
See full publishing history Publishing
| Series | Published | Component | Section |
|---|
Downloads
| File | Size | SHA-256 Checksum |
|---|---|---|
| yosys_0.19-1.dsc | 2.8 KiB | cdca41ad2a92bd1d1c074469b78151a1268743d6cd5ceb082e8fd9a5018fcc8c |
| yosys_0.19.orig.tar.gz | 2.2 MiB | d527fd88a9f7101c6f8e37889b14add0b6d2c74c2c611295f3813db4f397518f |
| yosys_0.19-1.debian.tar.xz | 16.6 KiB | 5cb976e010425aed2050c59f2492a66da4856132e7a141397d79ba4ec64c258b |
Available diffs
- diff from 0.9-2 to 0.19-1 (1.6 MiB)
- diff from 0.18-1 to 0.19-1 (30.5 KiB)
No changes file available.
Binary packages built by this source
- yosys: No summary available for yosys in ubuntu kinetic.
No description available for yosys in ubuntu kinetic.
- yosys-dbgsym: No summary available for yosys-dbgsym in ubuntu kinetic.
No description available for yosys-dbgsym in ubuntu kinetic.
- yosys-dev: Framework for Verilog RTL synthesis (development files)
Yosys is a framework for Verilog RTL synthesis. It currently has extensive
Verilog-2005 support and provides a basic set of synthesis algorithms for
various application domains.
.
Yosys can be adapted to perform any synthesis job by combining the existing
passes (algorithms) using synthesis scripts and adding additional passes as
needed by extending the yosys C++ code base.
.
This package contains the headers and programs needed to build yosys plugins.
- yosys-doc: Documentation for Yosys
Yosys is a framework for Verilog RTL synthesis. It currently has extensive
Verilog-2005 support and provides a basic set of synthesis algorithms for
various application domains.
.
Yosys can be adapted to perform any synthesis job by combining the existing
passes (algorithms) using synthesis scripts and adding additional passes as
needed by extending the yosys C++ code base.
.
This package contains the manual.
