diff -u mesa-6.5.2/debian/patches/series mesa-6.5.2/debian/patches/series --- mesa-6.5.2/debian/patches/series +++ mesa-6.5.2/debian/patches/series @@ -16,0 +17,5 @@ +113_avoid-branch-insns-while-in-single-program-flow-mode.patch +200_945gme.patch +201_g33.patch +202_965gm.patch +203_965gme.patch diff -u mesa-6.5.2/debian/changelog mesa-6.5.2/debian/changelog --- mesa-6.5.2/debian/changelog +++ mesa-6.5.2/debian/changelog @@ -1,3 +1,18 @@ +mesa (6.5.2-3ubuntu8) feisty-proposed; urgency=low + + [ Kyle McMartin ] + * Add support for Intel 945GME, G33, Q33, Q35, 965GM, 965GME/GLE + - 200_945gme.patch, upstream a74eec5af5397b612d60dd4b0d81666027f19bb0, + ad6351a994fd14af9d07da4f06837a7f9b9d0de4 + - 201_g33.patch, upstream 8331d9d7aa7cde7126d38d4e1eb5fe8a168077f3 + - 202_965gm.patch, upstream adb91c056f896955efcbf627bb1c2012aeb8a735 + - 203_965gme.patch, upstream 1b27ef39c9abeaa03d65f477ac4538361f2341cc + * Fix lock up on i965 with fullscreen GL + - 113_avoid-branch-insns-while-in-single-program-flow-mode.patch, + upstream 1b9f7819... + + -- Kyle McMartin Tue, 3 Jul 2007 21:48:29 +0000 + mesa (6.5.2-3ubuntu7) feisty; urgency=low * debian/patches: only in patch2: unchanged: --- mesa-6.5.2.orig/debian/patches/113_avoid-branch-insns-while-in-single-program-flow-mode.patch +++ mesa-6.5.2/debian/patches/113_avoid-branch-insns-while-in-single-program-flow-mode.patch @@ -0,0 +1,328 @@ +commit 1b9f78195f62959601d440475a6cbba5e8046813 +Author: Eric Anholt +Date: Wed Oct 18 00:24:01 2006 -0700 + + i965: Avoid branch instructions while in single program flow mode. + + There is an errata for Broadwater that threads don't have the instruction/loop + mask stacks initialized on thread spawn. In single program flow mode, those + stacks are not writable, so we can't initialize them. However, they do get + read during ELSE and ENDIF instructions. So, instead, replace branch + instructions in single program flow mode with predicated jumps (ADD to the ip + register), avoiding use of the more complicated branch instructions that may + fail. This is also a minor optimization as no ENDIF equivalent is necessary. + + Signed-off-by: Keith Packard + +diff --git a/src/mesa/drivers/dri/i965/brw_clip.c b/src/mesa/drivers/dri/i965/brw_clip.c +index 0e8591a..3bec153 100644 +--- a/src/mesa/drivers/dri/i965/brw_clip.c ++++ b/src/mesa/drivers/dri/i965/brw_clip.c +@@ -62,6 +62,8 @@ static void compile_clip_prog( struct brw_context *brw, + */ + brw_init_compile(&c.func); + ++ c.func.single_program_flow = 1; ++ + c.key = *key; + + +diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h +index 1afa0f8..d4dbcf3 100644 +--- a/src/mesa/drivers/dri/i965/brw_eu.h ++++ b/src/mesa/drivers/dri/i965/brw_eu.h +@@ -104,6 +104,7 @@ struct brw_compile { + struct brw_instruction *current; + + GLuint flag_value; ++ GLboolean single_program_flow; + }; + + +diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c +index 6425c91..9992b47 100644 +--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c ++++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c +@@ -464,7 +464,6 @@ struct brw_instruction *brw_JMPI(struct brw_compile *p, + return insn; + } + +- + /* EU takes the value from the flag register and pushes it onto some + * sort of a stack (presumably merging with any flag value already on + * the stack). Within an if block, the flags at the top of the stack +@@ -482,7 +481,16 @@ struct brw_instruction *brw_JMPI(struct brw_compile *p, + */ + struct brw_instruction *brw_IF(struct brw_compile *p, GLuint execute_size) + { +- struct brw_instruction *insn = next_insn(p, BRW_OPCODE_IF); ++ struct brw_instruction *insn; ++ ++ if (p->single_program_flow) { ++ assert(execute_size == BRW_EXECUTE_1); ++ ++ insn = next_insn(p, BRW_OPCODE_ADD); ++ insn->header.predicate_inverse = 1; ++ } else { ++ insn = next_insn(p, BRW_OPCODE_IF); ++ } + + /* Override the defaults for this instruction: + */ +@@ -504,7 +512,13 @@ struct brw_instruction *brw_IF(struct brw_compile *p, GLuint execute_size) + struct brw_instruction *brw_ELSE(struct brw_compile *p, + struct brw_instruction *if_insn) + { +- struct brw_instruction *insn = next_insn(p, BRW_OPCODE_ELSE); ++ struct brw_instruction *insn; ++ ++ if (p->single_program_flow) { ++ insn = next_insn(p, BRW_OPCODE_ADD); ++ } else { ++ insn = next_insn(p, BRW_OPCODE_ELSE); ++ } + + brw_set_dest(insn, brw_ip_reg()); + brw_set_src0(insn, brw_ip_reg()); +@@ -516,11 +530,17 @@ struct brw_instruction *brw_ELSE(struct brw_compile *p, + + /* Patch the if instruction to point at this instruction. + */ +- assert(if_insn->header.opcode == BRW_OPCODE_IF); ++ if (p->single_program_flow) { ++ assert(if_insn->header.opcode == BRW_OPCODE_ADD); + +- if_insn->bits3.if_else.jump_count = insn - if_insn; +- if_insn->bits3.if_else.pop_count = 1; +- if_insn->bits3.if_else.pad0 = 0; ++ if_insn->bits3.ud = (insn - if_insn + 1) * 16; ++ } else { ++ assert(if_insn->header.opcode == BRW_OPCODE_IF); ++ ++ if_insn->bits3.if_else.jump_count = insn - if_insn; ++ if_insn->bits3.if_else.pop_count = 1; ++ if_insn->bits3.if_else.pad0 = 0; ++ } + + return insn; + } +@@ -528,63 +548,76 @@ struct brw_instruction *brw_ELSE(struct brw_compile *p, + void brw_ENDIF(struct brw_compile *p, + struct brw_instruction *patch_insn) + { +- struct brw_instruction *insn = next_insn(p, BRW_OPCODE_ENDIF); ++ if (p->single_program_flow) { ++ /* In single program flow mode, there's no need to execute an ENDIF, ++ * since we don't need to do any stack operations, and if we're executing ++ * currently, we want to just continue executing. ++ */ ++ struct brw_instruction *next = &p->store[p->nr_insn]; + +- brw_set_dest(insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD)); +- brw_set_src0(insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD)); +- brw_set_src1(insn, brw_imm_d(0x0)); ++ assert(patch_insn->header.opcode == BRW_OPCODE_ADD); + +- insn->header.compression_control = BRW_COMPRESSION_NONE; +- insn->header.execution_size = patch_insn->header.execution_size; +- insn->header.mask_control = BRW_MASK_ENABLE; ++ patch_insn->bits3.ud = (next - patch_insn) * 16; ++ } else { ++ struct brw_instruction *insn = next_insn(p, BRW_OPCODE_ENDIF); + +- assert(patch_insn->bits3.if_else.jump_count == 0); +- +- /* Patch the if or else instructions to point at this or the next +- * instruction respectively. +- */ +- if (patch_insn->header.opcode == BRW_OPCODE_IF) { +- /* Automagically turn it into an IFF: ++ brw_set_dest(insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD)); ++ brw_set_src0(insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD)); ++ brw_set_src1(insn, brw_imm_d(0x0)); ++ ++ insn->header.compression_control = BRW_COMPRESSION_NONE; ++ insn->header.execution_size = patch_insn->header.execution_size; ++ insn->header.mask_control = BRW_MASK_ENABLE; ++ ++ assert(patch_insn->bits3.if_else.jump_count == 0); ++ ++ /* Patch the if or else instructions to point at this or the next ++ * instruction respectively. + */ +- patch_insn->header.opcode = BRW_OPCODE_IFF; +- patch_insn->bits3.if_else.jump_count = insn - patch_insn + 1; +- patch_insn->bits3.if_else.pop_count = 0; +- patch_insn->bits3.if_else.pad0 = 0; ++ if (patch_insn->header.opcode == BRW_OPCODE_IF) { ++ /* Automagically turn it into an IFF: ++ */ ++ patch_insn->header.opcode = BRW_OPCODE_IFF; ++ patch_insn->bits3.if_else.jump_count = insn - patch_insn + 1; ++ patch_insn->bits3.if_else.pop_count = 0; ++ patch_insn->bits3.if_else.pad0 = 0; ++ } else if (patch_insn->header.opcode == BRW_OPCODE_ELSE) { ++ patch_insn->bits3.if_else.jump_count = insn - patch_insn + 1; ++ patch_insn->bits3.if_else.pop_count = 1; ++ patch_insn->bits3.if_else.pad0 = 0; ++ } else { ++ assert(0); ++ } + ++ /* Also pop item off the stack in the endif instruction: ++ */ ++ insn->bits3.if_else.jump_count = 0; ++ insn->bits3.if_else.pop_count = 1; ++ insn->bits3.if_else.pad0 = 0; + } +- else if (patch_insn->header.opcode == BRW_OPCODE_ELSE) { +- patch_insn->bits3.if_else.jump_count = insn - patch_insn + 1; +- patch_insn->bits3.if_else.pop_count = 1; +- patch_insn->bits3.if_else.pad0 = 0; +- } +- else { +- assert(0); +- } +- +- /* Also pop item off the stack in the endif instruction: +- */ +- insn->bits3.if_else.jump_count = 0; +- insn->bits3.if_else.pop_count = 1; +- insn->bits3.if_else.pad0 = 0; + } + + /* DO/WHILE loop: + */ + struct brw_instruction *brw_DO(struct brw_compile *p, GLuint execute_size) + { +- struct brw_instruction *insn = next_insn(p, BRW_OPCODE_DO); ++ if (p->single_program_flow) { ++ return &p->store[p->nr_insn]; ++ } else { ++ struct brw_instruction *insn = next_insn(p, BRW_OPCODE_DO); + +- /* Override the defaults for this instruction: +- */ +- brw_set_dest(insn, retype(brw_vec1_grf(0,0), BRW_REGISTER_TYPE_UD)); +- brw_set_src0(insn, retype(brw_vec1_grf(0,0), BRW_REGISTER_TYPE_UD)); +- brw_set_src1(insn, retype(brw_vec1_grf(0,0), BRW_REGISTER_TYPE_UD)); ++ /* Override the defaults for this instruction: ++ */ ++ brw_set_dest(insn, retype(brw_vec1_grf(0,0), BRW_REGISTER_TYPE_UD)); ++ brw_set_src0(insn, retype(brw_vec1_grf(0,0), BRW_REGISTER_TYPE_UD)); ++ brw_set_src1(insn, retype(brw_vec1_grf(0,0), BRW_REGISTER_TYPE_UD)); + +- insn->header.compression_control = BRW_COMPRESSION_NONE; +- insn->header.execution_size = execute_size; +-/* insn->header.mask_control = BRW_MASK_ENABLE; */ ++ insn->header.compression_control = BRW_COMPRESSION_NONE; ++ insn->header.execution_size = execute_size; ++ /* insn->header.mask_control = BRW_MASK_ENABLE; */ + +- return insn; ++ return insn; ++ } + } + + +@@ -592,19 +625,31 @@ struct brw_instruction *brw_DO(struct brw_compile *p, GLuint execute_size) + void brw_WHILE(struct brw_compile *p, + struct brw_instruction *do_insn) + { +- struct brw_instruction *insn = next_insn(p, BRW_OPCODE_WHILE); ++ struct brw_instruction *insn; ++ ++ if (p->single_program_flow) ++ insn = next_insn(p, BRW_OPCODE_ADD); ++ else ++ insn = next_insn(p, BRW_OPCODE_WHILE); + + brw_set_dest(insn, brw_ip_reg()); + brw_set_src0(insn, brw_ip_reg()); + brw_set_src1(insn, brw_imm_d(0x0)); + + insn->header.compression_control = BRW_COMPRESSION_NONE; +- insn->header.execution_size = do_insn->header.execution_size; + +- assert(do_insn->header.opcode == BRW_OPCODE_DO); +- insn->bits3.if_else.jump_count = do_insn - insn; +- insn->bits3.if_else.pop_count = 0; +- insn->bits3.if_else.pad0 = 0; ++ if (p->single_program_flow) { ++ insn->header.execution_size = BRW_EXECUTE_1; ++ ++ insn->bits3.d = (do_insn - insn) * 16; ++ } else { ++ insn->header.execution_size = do_insn->header.execution_size; ++ ++ assert(do_insn->header.opcode == BRW_OPCODE_DO); ++ insn->bits3.if_else.jump_count = do_insn - insn; ++ insn->bits3.if_else.pop_count = 0; ++ insn->bits3.if_else.pad0 = 0; ++ } + + /* insn->header.mask_control = BRW_MASK_ENABLE; */ + +diff --git a/src/mesa/drivers/dri/i965/brw_gs.c b/src/mesa/drivers/dri/i965/brw_gs.c +index 7d3f9dd..9066e42 100644 +--- a/src/mesa/drivers/dri/i965/brw_gs.c ++++ b/src/mesa/drivers/dri/i965/brw_gs.c +@@ -66,7 +66,9 @@ static void compile_gs_prog( struct brw_context *brw, + /* Begin the compilation: + */ + brw_init_compile(&c.func); +- ++ ++ c.func.single_program_flow = 1; ++ + /* For some reason the thread is spawned with only 4 channels + * unmasked. + */ +diff --git a/src/mesa/drivers/dri/i965/brw_structs.h b/src/mesa/drivers/dri/i965/brw_structs.h +index 25acdcf..10fee94 100644 +--- a/src/mesa/drivers/dri/i965/brw_structs.h ++++ b/src/mesa/drivers/dri/i965/brw_structs.h +@@ -519,7 +519,22 @@ struct thread3 + struct brw_clip_unit_state + { + struct thread0 thread0; +- struct thread1 thread1; ++ struct ++ { ++ GLuint pad0:7; ++ GLuint sw_exception_enable:1; ++ GLuint pad1:3; ++ GLuint mask_stack_exception_enable:1; ++ GLuint pad2:1; ++ GLuint illegal_op_exception_enable:1; ++ GLuint pad3:2; ++ GLuint floating_point_mode:1; ++ GLuint thread_priority:1; ++ GLuint binding_table_entry_count:8; ++ GLuint pad4:5; ++ GLuint single_program_flow:1; ++ } thread1; ++ + struct thread2 thread2; + struct thread3 thread3; + +@@ -532,8 +547,8 @@ struct brw_clip_unit_state + GLuint pad1:1; + GLuint urb_entry_allocation_size:5; + GLuint pad2:1; +- GLuint max_threads:6; /* may be less */ +- GLuint pad3:1; ++ GLuint max_threads:1; /* may be less */ ++ GLuint pad3:6; + } thread4; + + struct +@@ -1322,6 +1337,7 @@ struct brw_instruction + GLuint end_of_thread:1; + } generic; + ++ GLint d; + GLuint ud; + } bits3; + }; + only in patch2: unchanged: --- mesa-6.5.2.orig/debian/patches/200_945gme.patch +++ mesa-6.5.2/debian/patches/200_945gme.patch @@ -0,0 +1,106 @@ +diff -Nur mesa-6.5.2/src/mesa/drivers/dri/i915/i915_texstate.c mesa-6.5.2~/src/mesa/drivers/dri/i915/i915_texstate.c +--- mesa-6.5.2/src/mesa/drivers/dri/i915/i915_texstate.c 2006-04-06 16:23:40.000000000 +0000 ++++ mesa-6.5.2~/src/mesa/drivers/dri/i915/i915_texstate.c 2007-07-03 21:26:34.000000000 +0000 +@@ -497,7 +497,8 @@ + + + if (i915->intel.intelScreen->deviceID == PCI_CHIP_I945_G || +- i915->intel.intelScreen->deviceID == PCI_CHIP_I945_GM) ++ i915->intel.intelScreen->deviceID == PCI_CHIP_I945_GM || ++ i915->intel.intelScreen->deviceID == PCI_CHIP_I945_GME) + i945LayoutTextureImages( i915, tObj ); + else + i915LayoutTextureImages( i915, tObj ); +diff -Nur mesa-6.5.2/src/mesa/drivers/dri/i915/intel_context.c mesa-6.5.2~/src/mesa/drivers/dri/i915/intel_context.c +--- mesa-6.5.2/src/mesa/drivers/dri/i915/intel_context.c 2006-11-02 22:29:39.000000000 +0000 ++++ mesa-6.5.2~/src/mesa/drivers/dri/i915/intel_context.c 2007-07-03 21:27:13.000000000 +0000 +@@ -122,6 +122,8 @@ + chipset = "Intel(R) 945G"; break; + case PCI_CHIP_I945_GM: + chipset = "Intel(R) 945GM"; break; ++ case PCI_CHIP_I945_GME: ++ chipset = "Intel(R) 945GME"; break; + default: + chipset = "Unknown Intel Chipset"; break; + } +diff -Nur mesa-6.5.2/src/mesa/drivers/dri/i915/intel_context.h mesa-6.5.2~/src/mesa/drivers/dri/i915/intel_context.h +--- mesa-6.5.2/src/mesa/drivers/dri/i915/intel_context.h 2006-10-04 16:27:11.000000000 +0000 ++++ mesa-6.5.2~/src/mesa/drivers/dri/i915/intel_context.h 2007-07-03 21:27:46.000000000 +0000 +@@ -454,6 +454,7 @@ + #define PCI_CHIP_I915_GM 0x2592 + #define PCI_CHIP_I945_G 0x2772 + #define PCI_CHIP_I945_GM 0x27A2 ++#define PCI_CHIP_I945_GME 0x27AE + + + /* ================================================================ +diff -Nur mesa-6.5.2/src/mesa/drivers/dri/i915/intel_screen.c mesa-6.5.2~/src/mesa/drivers/dri/i915/intel_screen.c +--- mesa-6.5.2/src/mesa/drivers/dri/i915/intel_screen.c 2006-09-11 21:35:49.000000000 +0000 ++++ mesa-6.5.2~/src/mesa/drivers/dri/i915/intel_screen.c 2007-07-03 21:28:10.000000000 +0000 +@@ -514,6 +514,7 @@ + case PCI_CHIP_I915_GM: + case PCI_CHIP_I945_G: + case PCI_CHIP_I945_GM: ++ case PCI_CHIP_I945_GME: + return i915CreateContext( mesaVis, driContextPriv, + sharedContextPrivate ); + +diff -Nur mesa-6.5.2/src/mesa/drivers/dri/i915/intel_tex.c mesa-6.5.2~/src/mesa/drivers/dri/i915/intel_tex.c +--- mesa-6.5.2/src/mesa/drivers/dri/i915/intel_tex.c 2006-04-07 08:50:39.000000000 +0000 ++++ mesa-6.5.2~/src/mesa/drivers/dri/i915/intel_tex.c 2007-07-03 21:28:38.000000000 +0000 +@@ -675,7 +675,8 @@ + /* Time for another vtbl entry: + */ + else if (intel->intelScreen->deviceID == PCI_CHIP_I945_G || +- intel->intelScreen->deviceID == PCI_CHIP_I945_GM) { ++ intel->intelScreen->deviceID == PCI_CHIP_I945_GM || ++ intel->intelScreen->deviceID == PCI_CHIP_I945_GME) { + GLuint row_len = image->Width * image->TexFormat->TexelBytes; + GLubyte *dst = (GLubyte *)(t->BufAddr + offset); + GLubyte *src = (GLubyte *)image->Data; +diff -Nur mesa-6.5.2/src/mesa/drivers/dri/i915tex/intel_context.c mesa-6.5.2~/src/mesa/drivers/dri/i915tex/intel_context.c +--- mesa-6.5.2/src/mesa/drivers/dri/i915tex/intel_context.c 2006-11-02 22:29:39.000000000 +0000 ++++ mesa-6.5.2~/src/mesa/drivers/dri/i915tex/intel_context.c 2007-07-03 21:30:16.000000000 +0000 +@@ -129,6 +129,9 @@ + case PCI_CHIP_I945_GM: + chipset = "Intel(R) 945GM"; + break; ++ case PCI_CHIP_I945_GME: ++ chipset = "Intel(R) 945GME"; ++ break; + default: + chipset = "Unknown Intel Chipset"; + break; +diff -Nur mesa-6.5.2/src/mesa/drivers/dri/i915tex/intel_context.h mesa-6.5.2~/src/mesa/drivers/dri/i915tex/intel_context.h +--- mesa-6.5.2/src/mesa/drivers/dri/i915tex/intel_context.h 2006-11-03 20:18:19.000000000 +0000 ++++ mesa-6.5.2~/src/mesa/drivers/dri/i915tex/intel_context.h 2007-07-03 21:30:37.000000000 +0000 +@@ -386,6 +386,7 @@ + #define PCI_CHIP_I915_GM 0x2592 + #define PCI_CHIP_I945_G 0x2772 + #define PCI_CHIP_I945_GM 0x27A2 ++#define PCI_CHIP_I945_GME 0x27AE + + + /* ================================================================ +diff -Nur mesa-6.5.2/src/mesa/drivers/dri/i915tex/intel_mipmap_tree.c mesa-6.5.2~/src/mesa/drivers/dri/i915tex/intel_mipmap_tree.c +--- mesa-6.5.2/src/mesa/drivers/dri/i915tex/intel_mipmap_tree.c 2006-11-15 14:55:48.000000000 +0000 ++++ mesa-6.5.2~/src/mesa/drivers/dri/i915tex/intel_mipmap_tree.c 2007-07-03 21:30:56.000000000 +0000 +@@ -79,6 +79,7 @@ + switch (intel->intelScreen->deviceID) { + case PCI_CHIP_I945_G: + case PCI_CHIP_I945_GM: ++ case PCI_CHIP_I945_GME: + ok = i945_miptree_layout(mt); + break; + case PCI_CHIP_I915_G: +diff -Nur mesa-6.5.2/src/mesa/drivers/dri/i915tex/intel_screen.c mesa-6.5.2~/src/mesa/drivers/dri/i915tex/intel_screen.c +--- mesa-6.5.2/src/mesa/drivers/dri/i915tex/intel_screen.c 2006-11-01 18:48:28.000000000 +0000 ++++ mesa-6.5.2~/src/mesa/drivers/dri/i915tex/intel_screen.c 2007-07-03 21:31:24.000000000 +0000 +@@ -676,6 +676,7 @@ + case PCI_CHIP_I915_GM: + case PCI_CHIP_I945_G: + case PCI_CHIP_I945_GM: ++ case PCI_CHIP_I945_GME: + return i915CreateContext(mesaVis, driContextPriv, sharedContextPrivate); + + default: only in patch2: unchanged: --- mesa-6.5.2.orig/debian/patches/203_965gme.patch +++ mesa-6.5.2/debian/patches/203_965gme.patch @@ -0,0 +1,23 @@ +diff -Nur mesa-6.5.2~/src/mesa/drivers/dri/i965/intel_context.c mesa-6.5.2~~/src/mesa/drivers/dri/i965/intel_context.c +--- mesa-6.5.2~/src/mesa/drivers/dri/i965/intel_context.c 2007-07-03 22:01:00.000000000 +0000 ++++ mesa-6.5.2~~/src/mesa/drivers/dri/i965/intel_context.c 2007-07-03 22:02:31.000000000 +0000 +@@ -119,6 +119,8 @@ + break; + case PCI_CHIP_I965_GM: + chipset = "Intel(R) 965GM"; break; ++ case PCI_CHIP_I965_GME: ++ chipset = "Intel(R) 965GME/GLE"; break; + default: + chipset = "Unknown Intel Chipset"; break; + } +diff -Nur mesa-6.5.2~/src/mesa/drivers/dri/i965/intel_context.h mesa-6.5.2~~/src/mesa/drivers/dri/i965/intel_context.h +--- mesa-6.5.2~/src/mesa/drivers/dri/i965/intel_context.h 2007-07-03 22:01:00.000000000 +0000 ++++ mesa-6.5.2~~/src/mesa/drivers/dri/i965/intel_context.h 2007-07-03 22:02:05.000000000 +0000 +@@ -384,6 +384,7 @@ + #define PCI_CHIP_I965_G_1 0x2982 + #define PCI_CHIP_I946_GZ 0x2972 + #define PCI_CHIP_I965_GM 0x2A02 ++#define PCI_CHIP_I965_GME 0x2A12 + + + /* ================================================================ only in patch2: unchanged: --- mesa-6.5.2.orig/debian/patches/202_965gm.patch +++ mesa-6.5.2/debian/patches/202_965gm.patch @@ -0,0 +1,23 @@ +diff -Nur mesa-6.5.2~/src/mesa/drivers/dri/i965/intel_context.c mesa-6.5.2~~/src/mesa/drivers/dri/i965/intel_context.c +--- mesa-6.5.2~/src/mesa/drivers/dri/i965/intel_context.c 2006-11-23 16:57:10.000000000 +0000 ++++ mesa-6.5.2~~/src/mesa/drivers/dri/i965/intel_context.c 2007-07-03 21:57:04.000000000 +0000 +@@ -117,6 +117,8 @@ + case PCI_CHIP_I946_GZ: + chipset = "Intel(R) 946GZ"; break; + break; ++ case PCI_CHIP_I965_GM: ++ chipset = "Intel(R) 965GM"; break; + default: + chipset = "Unknown Intel Chipset"; break; + } +diff -Nur mesa-6.5.2~/src/mesa/drivers/dri/i965/intel_context.h mesa-6.5.2~~/src/mesa/drivers/dri/i965/intel_context.h +--- mesa-6.5.2~/src/mesa/drivers/dri/i965/intel_context.h 2006-12-02 18:14:17.000000000 +0000 ++++ mesa-6.5.2~~/src/mesa/drivers/dri/i965/intel_context.h 2007-07-03 21:57:58.000000000 +0000 +@@ -383,6 +383,7 @@ + #define PCI_CHIP_I965_Q 0x2992 + #define PCI_CHIP_I965_G_1 0x2982 + #define PCI_CHIP_I946_GZ 0x2972 ++#define PCI_CHIP_I965_GM 0x2A02 + + + /* ================================================================ only in patch2: unchanged: --- mesa-6.5.2.orig/debian/patches/201_g33.patch +++ mesa-6.5.2/debian/patches/201_g33.patch @@ -0,0 +1,142 @@ +diff -Nur mesa-6.5.2~/src/mesa/drivers/dri/i915/i915_texstate.c mesa-6.5.2~~/src/mesa/drivers/dri/i915/i915_texstate.c +--- mesa-6.5.2~/src/mesa/drivers/dri/i915/i915_texstate.c 2007-07-03 21:37:16.000000000 +0000 ++++ mesa-6.5.2~~/src/mesa/drivers/dri/i915/i915_texstate.c 2007-07-03 21:39:30.000000000 +0000 +@@ -496,12 +496,19 @@ + } + + +- if (i915->intel.intelScreen->deviceID == PCI_CHIP_I945_G || +- i915->intel.intelScreen->deviceID == PCI_CHIP_I945_GM || +- i915->intel.intelScreen->deviceID == PCI_CHIP_I945_GME) ++ switch (i915->intel.intelScreen->deviceID) { ++ case PCI_CHIP_I945_G: ++ case PCI_CHIP_I945_GM: ++ case PCI_CHIP_I945_GME: ++ case PCI_CHIP_G33_G: ++ case PCI_CHIP_Q33_G: ++ case PCI_CHIP_Q35_G: + i945LayoutTextureImages( i915, tObj ); +- else ++ break; ++ default: + i915LayoutTextureImages( i915, tObj ); ++ break; ++ } + + t->Setup[I915_TEXREG_MS3] = + (((tObj->Image[0][t->intel.base.firstLevel]->Height - 1) << MS3_HEIGHT_SHIFT) | +diff -Nur mesa-6.5.2~/src/mesa/drivers/dri/i915/intel_context.c mesa-6.5.2~~/src/mesa/drivers/dri/i915/intel_context.c +--- mesa-6.5.2~/src/mesa/drivers/dri/i915/intel_context.c 2007-07-03 21:37:16.000000000 +0000 ++++ mesa-6.5.2~~/src/mesa/drivers/dri/i915/intel_context.c 2007-07-03 21:41:16.000000000 +0000 +@@ -124,6 +124,12 @@ + chipset = "Intel(R) 945GM"; break; + case PCI_CHIP_I945_GME: + chipset = "Intel(R) 945GME"; break; ++ case PCI_CHIP_G33_G: ++ chipset = "Intel(R) G33"; break; ++ case PCI_CHIP_Q35_G: ++ chipset = "Intel(R) Q35"; break; ++ case PCI_CHIP_Q33_G: ++ chipset = "Intel(R) Q33"; break; + default: + chipset = "Unknown Intel Chipset"; break; + } +diff -Nur mesa-6.5.2~/src/mesa/drivers/dri/i915/intel_context.h mesa-6.5.2~~/src/mesa/drivers/dri/i915/intel_context.h +--- mesa-6.5.2~/src/mesa/drivers/dri/i915/intel_context.h 2007-07-03 21:37:16.000000000 +0000 ++++ mesa-6.5.2~~/src/mesa/drivers/dri/i915/intel_context.h 2007-07-03 21:42:26.000000000 +0000 +@@ -455,6 +455,9 @@ + #define PCI_CHIP_I945_G 0x2772 + #define PCI_CHIP_I945_GM 0x27A2 + #define PCI_CHIP_I945_GME 0x27AE ++#define PCI_CHIP_G33_G 0x29C2 ++#define PCI_CHIP_Q35_G 0x29B2 ++#define PCI_CHIP_Q33_G 0x29D2 + + + /* ================================================================ +diff -Nur mesa-6.5.2~/src/mesa/drivers/dri/i915/intel_screen.c mesa-6.5.2~~/src/mesa/drivers/dri/i915/intel_screen.c +--- mesa-6.5.2~/src/mesa/drivers/dri/i915/intel_screen.c 2007-07-03 21:37:16.000000000 +0000 ++++ mesa-6.5.2~~/src/mesa/drivers/dri/i915/intel_screen.c 2007-07-03 21:43:06.000000000 +0000 +@@ -515,6 +515,9 @@ + case PCI_CHIP_I945_G: + case PCI_CHIP_I945_GM: + case PCI_CHIP_I945_GME: ++ case PCI_CHIP_G33_G: ++ case PCI_CHIP_Q35_G: ++ case PCI_CHIP_Q33_G: + return i915CreateContext( mesaVis, driContextPriv, + sharedContextPrivate ); + +diff -Nur mesa-6.5.2~/src/mesa/drivers/dri/i915/intel_tex.c mesa-6.5.2~~/src/mesa/drivers/dri/i915/intel_tex.c +--- mesa-6.5.2~/src/mesa/drivers/dri/i915/intel_tex.c 2007-07-03 21:37:16.000000000 +0000 ++++ mesa-6.5.2~~/src/mesa/drivers/dri/i915/intel_tex.c 2007-07-03 21:44:17.000000000 +0000 +@@ -676,7 +676,10 @@ + */ + else if (intel->intelScreen->deviceID == PCI_CHIP_I945_G || + intel->intelScreen->deviceID == PCI_CHIP_I945_GM || +- intel->intelScreen->deviceID == PCI_CHIP_I945_GME) { ++ intel->intelScreen->deviceID == PCI_CHIP_I945_GME || ++ intel->intelScreen->deviceID == PCI_CHIP_G33_G || ++ intel->intelScreen->deviceID == PCI_CHIP_Q33_G || ++ intel->intelScreen->deviceID == PCI_CHIP_Q35_G) { + GLuint row_len = image->Width * image->TexFormat->TexelBytes; + GLubyte *dst = (GLubyte *)(t->BufAddr + offset); + GLubyte *src = (GLubyte *)image->Data; +diff -Nur mesa-6.5.2~/src/mesa/drivers/dri/i915tex/intel_context.c mesa-6.5.2~~/src/mesa/drivers/dri/i915tex/intel_context.c +--- mesa-6.5.2~/src/mesa/drivers/dri/i915tex/intel_context.c 2007-07-03 21:37:16.000000000 +0000 ++++ mesa-6.5.2~~/src/mesa/drivers/dri/i915tex/intel_context.c 2007-07-03 21:45:07.000000000 +0000 +@@ -132,6 +132,15 @@ + case PCI_CHIP_I945_GME: + chipset = "Intel(R) 945GME"; + break; ++ case PCI_CHIP_G33_G: ++ chipset = "Intel(R) G33"; ++ break; ++ case PCI_CHIP_Q35_G: ++ chipset = "Intel(R) Q35"; ++ break; ++ case PCI_CHIP_Q33_G: ++ chipset = "Intel(R) Q33"; ++ break; + default: + chipset = "Unknown Intel Chipset"; + break; +diff -Nur mesa-6.5.2~/src/mesa/drivers/dri/i915tex/intel_context.h mesa-6.5.2~~/src/mesa/drivers/dri/i915tex/intel_context.h +--- mesa-6.5.2~/src/mesa/drivers/dri/i915tex/intel_context.h 2007-07-03 21:37:16.000000000 +0000 ++++ mesa-6.5.2~~/src/mesa/drivers/dri/i915tex/intel_context.h 2007-07-03 21:45:51.000000000 +0000 +@@ -387,6 +387,9 @@ + #define PCI_CHIP_I945_G 0x2772 + #define PCI_CHIP_I945_GM 0x27A2 + #define PCI_CHIP_I945_GME 0x27AE ++#define PCI_CHIP_G33_G 0x29C2 ++#define PCI_CHIP_Q35_G 0x29B2 ++#define PCI_CHIP_Q33_G 0x29D2 + + + /* ================================================================ +diff -Nur mesa-6.5.2~/src/mesa/drivers/dri/i915tex/intel_mipmap_tree.c mesa-6.5.2~~/src/mesa/drivers/dri/i915tex/intel_mipmap_tree.c +--- mesa-6.5.2~/src/mesa/drivers/dri/i915tex/intel_mipmap_tree.c 2007-07-03 21:37:16.000000000 +0000 ++++ mesa-6.5.2~~/src/mesa/drivers/dri/i915tex/intel_mipmap_tree.c 2007-07-03 21:46:20.000000000 +0000 +@@ -80,6 +80,9 @@ + case PCI_CHIP_I945_G: + case PCI_CHIP_I945_GM: + case PCI_CHIP_I945_GME: ++ case PCI_CHIP_G33_G: ++ case PCI_CHIP_Q33_G: ++ case PCI_CHIP_Q35_G: + ok = i945_miptree_layout(mt); + break; + case PCI_CHIP_I915_G: +diff -Nur mesa-6.5.2~/src/mesa/drivers/dri/i915tex/intel_screen.c mesa-6.5.2~~/src/mesa/drivers/dri/i915tex/intel_screen.c +--- mesa-6.5.2~/src/mesa/drivers/dri/i915tex/intel_screen.c 2007-07-03 21:37:16.000000000 +0000 ++++ mesa-6.5.2~~/src/mesa/drivers/dri/i915tex/intel_screen.c 2007-07-03 21:46:51.000000000 +0000 +@@ -677,6 +677,9 @@ + case PCI_CHIP_I945_G: + case PCI_CHIP_I945_GM: + case PCI_CHIP_I945_GME: ++ case PCI_CHIP_G33_G: ++ case PCI_CHIP_Q35_G: ++ case PCI_CHIP_Q33_G: + return i915CreateContext(mesaVis, driContextPriv, sharedContextPrivate); + + default: