verilator 5.024-1 source package in Ubuntu

Changelog

verilator (5.024-1) unstable; urgency=medium

  * Team upload.
  * [6494ad2] New upstream version 5.024
  * [cd7e535] d/rules: Add target override_dh_install
  * [46fe05b] d/control: Use the Recommends only on some architectures
  * [b2657af] d/verilator.lintian-overrides: Update the overrides
  * [beddf5b] d/control: Bump Standards-Version to 4.7.0
    No further modifications needed.

 -- Carsten Schoenert <email address hidden>  Fri, 10 May 2024 18:56:00 +0200

Upload details

Uploaded by:
Debian Electronics Team
Uploaded to:
Sid
Original maintainer:
Debian Electronics Team
Architectures:
any
Section:
electronics
Urgency:
Medium Urgency

See full publishing history Publishing

Series Pocket Published Component Section
Plucky release universe electronics
Oracular release universe electronics

Downloads

File Size SHA-256 Checksum
verilator_5.024-1.dsc 2.1 KiB 8449e15c06cbcc455ca2de9eaac2e7c3869cfbd7e28f62374184b997bee06654
verilator_5.024.orig.tar.gz 4.0 MiB c02e009b1d76863e8e3e9557b566f86cbe5f9799815d64b849eed5d76a81ecd5
verilator_5.024-1.debian.tar.xz 12.2 KiB e51b194ebfbe4bf57870f3c100a2ea8364c1af7c150abe0ff730e85d53fbb862

Available diffs

No changes file available.

Binary packages built by this source

verilator: fast free Verilog simulator

 Verilator is the fastest free Verilog HDL simulator, and beats many commercial
 simulators. It compiles synthesizable Verilog (not test-bench code!), plus
 some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code.
 It is designed for large projects where fast simulation performance is of
 primary concern, and is especially well suited to generate executable models
 of CPUs for embedded software design teams.