Ubuntu
verilator package

verilator 5.020-1 source package in Ubuntu

Changelog

verilator (5.020-1) unstable; urgency=medium

  * Team upload

  [ Adrian Bunk ]
  * [ab21150] Use -g1 to work around mipsel address space limitation

  [ Carsten Schoenert ]
  * [3f5e8c3] New upstream version 5.020
    (Closes: #1053383)
  * [e2c5fd7] Rebuild patch queue from patch-queue branch
    Removed patches (included upstream):
    fix-typos.patch
    remove-gtag.js.patch
  * [b782632] d/copyright: Update year data
  * [ed077bf] d/verilator.lintian-overrides: Adjust override to 'wTH'

 -- Carsten Schoenert <email address hidden>  Sat, 13 Jan 2024 09:54:40 +0100

Upload details

Uploaded by:
Debian Electronics Team
Uploaded to:
Sid
Original maintainer:
Debian Electronics Team
Architectures:
any
Section:
electronics
Urgency:
Medium Urgency

See full publishing history Publishing

Series Pocket Published Component Section
Noble release universe electronics

Downloads

File Size SHA-256 Checksum
verilator_5.020-1.dsc 2.1 KiB d04cf6f86f3471831e9ec7cf5512285fde91995ea38bf796fc8f83f43ae4c8f1
verilator_5.020.orig.tar.gz 3.7 MiB 3efb3a7c50c0bc0ea3989bf9219785b718cf9d056c643a9cef45570fbe46dafb
verilator_5.020-1.debian.tar.xz 12.1 KiB e31f96dcff0bf32c90fd5f5d31e779be6a1a51c159e97f0d0443ae922537eaa1

Available diffs

No changes file available.

Binary packages built by this source

verilator: fast free Verilog simulator

 Verilator is the fastest free Verilog HDL simulator, and beats many commercial
 simulators. It compiles synthesizable Verilog (not test-bench code!), plus
 some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code.
 It is designed for large projects where fast simulation performance is of
 primary concern, and is especially well suited to generate executable models
 of CPUs for embedded software design teams.

verilator-dbgsym: No summary available for verilator-dbgsym in ubuntu oracular.

No description available for verilator-dbgsym in ubuntu oracular.