verilator 5.012-1 source package in Ubuntu
Changelog
verilator (5.012-1) unstable; urgency=medium
* [bbe4c20] New upstream version 5.012
* [988bc5e] Add fix-typos.patch to fix a typo
* [ffd7dca] Add remove-gtag.js.patch to avoid inclusion of gtag.js in
generated HTML docs
* Upload to unstable
-- أحمد المحمودي (Ahmed El-Mahmoudy) <email address hidden> Sun, 02 Jul 2023 22:36:32 +0200
Upload details
- Uploaded by:
- Debian Electronics Team
- Uploaded to:
- Sid
- Original maintainer:
- Debian Electronics Team
- Architectures:
- any
- Section:
- electronics
- Urgency:
- Medium Urgency
See full publishing history Publishing
| Series | Published | Component | Section | |
|---|---|---|---|---|
| Mantic | release | universe | electronics |
Downloads
| File | Size | SHA-256 Checksum |
|---|---|---|
| verilator_5.012-1.dsc | 1.9 KiB | 75be3c81f72573ff00fc95ba7dc774bb55b7d9e91fc02293c0dcbd56cab38434 |
| verilator_5.012.orig.tar.gz | 3.1 MiB | 9c49c943972059577a2d7f0e8c755c8c96d8f2c85ea65d3b42e2278333a73a7a |
| verilator_5.012-1.debian.tar.xz | 12.5 KiB | 0a9761c52b1425260da066dcfa6370f158eba23b35ab8757d78981fbf5b9a114 |
Available diffs
- diff from 5.006-3 to 5.012-1 (467.3 KiB)
No changes file available.
Binary packages built by this source
- verilator: fast free Verilog simulator
Verilator is the fastest free Verilog HDL simulator, and beats many commercial
simulators. It compiles synthesizable Verilog (not test-bench code!), plus
some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code.
It is designed for large projects where fast simulation performance is of
primary concern, and is especially well suited to generate executable models
of CPUs for embedded software design teams.
- verilator-dbgsym: debug symbols for verilator
