verilator 5.006-1 source package in Ubuntu
Changelog
verilator (5.006-1) unstable; urgency=medium
* Team upload
* New upstream version 5.006
* Rebuild patch queue from patch-queue branch
Removed patches (included upstream):
Add-manpages-for-missing-user-commands-using-help2man.patch
Fix-VL_CPU_RELAX-on-MIPS-Armel-s390-sparc-3891.patch
Fix-to-use-same-std-flag-in-Verilator-and-Verilated-desig.patch
* d/u/metadata: Adjust repository URL data
-- Carsten Schoenert <email address hidden> Wed, 25 Jan 2023 17:52:48 +0100
Upload details
- Uploaded by:
- Debian Electronics Team
- Uploaded to:
- Sid
- Original maintainer:
- Debian Electronics Team
- Architectures:
- any
- Section:
- electronics
- Urgency:
- Medium Urgency
See full publishing history Publishing
| Series | Published | Component | Section |
|---|
Downloads
| File | Size | SHA-256 Checksum |
|---|---|---|
| verilator_5.006-1.dsc | 2.1 KiB | 204a1444f48eb8ceea1ac7f4b29af4579962b48582298610f83f3c99c12af2e3 |
| verilator_5.006.orig.tar.gz | 3.0 MiB | 732389e5906a600cc65230410c91b16a4fc8911d5455f1b488fc6964b4490b92 |
| verilator_5.006-1.debian.tar.xz | 11.6 KiB | 99a1cf95adb1bbd84744a09e1d8205bc76f5b13d5874b45c946c0c002b0dca91 |
Available diffs
- diff from 4.038-1 to 5.006-1 (3.0 MiB)
- diff from 5.004-2 to 5.006-1 (162.7 KiB)
No changes file available.
Binary packages built by this source
- verilator: fast free Verilog simulator
Verilator is the fastest free Verilog HDL simulator, and beats many commercial
simulators. It compiles synthesizable Verilog (not test-bench code!), plus
some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code.
It is designed for large projects where fast simulation performance is of
primary concern, and is especially well suited to generate executable models
of CPUs for embedded software design teams.
- verilator-dbgsym: debug symbols for verilator
