Ubuntu
verilator package

verilator 5.004-2 source package in Ubuntu

Changelog

verilator (5.004-2) unstable; urgency=medium

  * Team upload
  * Rebuild patch queue from patch-queue branch
    Added patch:
    Fix-VL_CPU_RELAX-on-MIPS-Armel-s390-sparc-3891.patch
  * d/rules: Re-add override_dh_auto_test
    dh_auto_test is failing on some architectures, for now ignore these
    architectures.
  * d/rules: Hack around keep original version config_rev
    The file src/config_rev is used to create the file src/config_rev.h.
    We modify the source file in d/rules which let dpkg-source detect unwanted
    modifications in case we try to build the twice. This adds a hack to work
    around this.
  * d/rules: Tune modification of version string data
    Use "(Debian $(DEB_VERSION))" instead of "none" in the version string.

 -- Carsten Schoenert <email address hidden>  Sat, 21 Jan 2023 11:08:36 +0100

Upload details

Uploaded by:
Debian Electronics Team
Uploaded to:
Sid
Original maintainer:
Debian Electronics Team
Architectures:
any
Section:
electronics
Urgency:
Medium Urgency

See full publishing history Publishing

Series Pocket Published Component Section

Downloads

File Size SHA-256 Checksum
verilator_5.004-2.dsc 2.1 KiB e90bdd11e557b34f9dd3df611dff80ac044fe0054ff203833c0fb909d350084e
verilator_5.004.orig.tar.gz 2.9 MiB 35866f556b6e1d1725dced54de0e2b765fb744db3cefd86a8b3a3a032b3f5aa0
verilator_5.004-2.debian.tar.xz 14.3 KiB 3df439ca98166e591adafac00b14d4ac5c085f0bac12a8408cc9249294dfac8b

Available diffs

No changes file available.

Binary packages built by this source

verilator: fast free Verilog simulator

 Verilator is the fastest free Verilog HDL simulator, and beats many commercial
 simulators. It compiles synthesizable Verilog (not test-bench code!), plus
 some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code.
 It is designed for large projects where fast simulation performance is of
 primary concern, and is especially well suited to generate executable models
 of CPUs for embedded software design teams.

verilator-dbgsym: debug symbols for verilator