verilator 5.004-1 source package in Ubuntu

Changelog

verilator (5.004-1) unstable; urgency=medium

  * Team upload

  [ أحمد المحمودي (Ahmed El-Mahmoudy) ]
  * New upstream version 4.038

  [ Steffen Möller ]
  * Update metadata - added refs to conda and guix

  [ Carsten Schoenert ]
  * d/gbp.conf: Adding default data for git-buildpackage
  * New upstream version 5.004
    This version is a new major release of verilator. It has significant
    changes and new feature. For an overview of the changes please have
    a look at https://github.com/verilator/verilator/blob/master/Changes
    or into the offline documentation shipped within the package at
    file:///usr/share/doc/verilator/html/changes.html or
    file:///usr/share/doc/verilator/verilator.pdf.
  * Rebuild patch queue from patch-queue branch
    Added patches:
    Add-manpages-for-missing-user-commands-using-help2man.patch
    Fix-to-use-same-std-flag-in-Verilator-and-Verilated-desig.patch
    Removed patches (included upstream):
    bison-3.7.patch
    reproducible_build.diff
    Removed patch (obsolete due upstream changes):
    interpreter.patch
  * d/*: Running wrap-and-sort -ast
  * d/{docs, doc-base}: Renamed to verilator.{docs, doc-base}
  * d/control: Add new build dependencies
    Due changes by upstream some new build dependencies are now required
    to build the documentation ans man pages.
  * d/control: Add additional Depends for verilator
    Some files of verilator are depending on Python 3 or Perl available
    on the system, the sphinxdoc sequencer requires also some additional
    installed packages for getting the HTML documentation usable.
  * d/rules: Update/add/modify various targets
    Tune the targets so we produce all related files and prepare the package
    installation.
  * d/verilator.docs: Updating due upstream changes
    Adjustments needed to get the correct files installed.
  * d/verilator.doc-base: Rewrite due upstream changes
  * d/watch: Move over to version 4 and git mode on GitHub
  * d/copyright: Update year data
  * d/u/metadate: Adjust and add some new data
  * d/verilator.lintian-overrides: Add stuff we can ignore
  * d/s/lintian-overrides: Ignore too some source related stuff
  * d/control: Bump Standards-Version to 4.6.2
    No further modifications needed.
  * CI: Rename to salsa-ci.yml
  * d/rules: Drop override for dh_auto_test
  * d/rules: s/UNKNOWN_REV/none in version string
  * d/README.source: Add basic information about source

 -- Carsten Schoenert <email address hidden>  Wed, 18 Jan 2023 18:39:22 +0100

Upload details

Uploaded by:
Debian Electronics Team
Uploaded to:
Sid
Original maintainer:
Debian Electronics Team
Architectures:
any
Section:
electronics
Urgency:
Medium Urgency

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File Size SHA-256 Checksum
verilator_5.004-1.dsc 2.1 KiB 2d35a8058e12613f8094b7a8ed03a27c28621043de7d21394fa84af0faa82dd8
verilator_5.004.orig.tar.gz 2.9 MiB 35866f556b6e1d1725dced54de0e2b765fb744db3cefd86a8b3a3a032b3f5aa0
verilator_5.004-1.debian.tar.xz 13.2 KiB 25fc341a37bce39629d961febf7d68e12baca1ff15011486f9c1f535ef20075b

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Binary packages built by this source

verilator: fast free Verilog simulator

 Verilator is the fastest free Verilog HDL simulator, and beats many commercial
 simulators. It compiles synthesizable Verilog (not test-bench code!), plus
 some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code.
 It is designed for large projects where fast simulation performance is of
 primary concern, and is especially well suited to generate executable models
 of CPUs for embedded software design teams.

verilator-dbgsym: debug symbols for verilator