verilator 4.038-1 source package in Ubuntu


verilator (4.038-1) unstable; urgency=medium

  * New upstream version 4.038
    + Fix test suite failure on 32-bit archs. (Closes: #962855)
  * Refresh patches
  * Add bison-3.7.patch to fix build problem with bison 3.7 (Closes: #966909)

 -- أحمد المحمودي (Ahmed El-Mahmoudy) <email address hidden>  Thu, 27 Aug 2020 07:31:46 +0200

Upload details

Uploaded by:
Debian Electronics Team on 2020-08-27
Uploaded to:
Original maintainer:
Debian Electronics Team
Medium Urgency

See full publishing history Publishing

Series Pocket Published Component Section
Hirsute release on 2020-10-23 universe electronics
Groovy release on 2020-08-27 universe electronics


File Size SHA-256 Checksum
verilator_4.038-1.dsc 1.7 KiB 226fa7fd0c77ce442c3013c462837436b53977ec33c6dcaa148706dd9fe31d1b
verilator_4.038.orig.tar.gz 2.6 MiB fa004493216034ac3e26b21b814441bd5801592f4f269c5a4672e3351d73b515
verilator_4.038-1.debian.tar.xz 9.4 KiB 9ab0fcd0923b316fcfd27cfa188a47b55dec8c1b7a8ac600006166a0829820dd

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No changes file available.

Binary packages built by this source

verilator: fast free Verilog simulator

 Verilator is the fastest free Verilog HDL simulator, and beats many commercial
 simulators. It compiles synthesizable Verilog (not test-bench code!), plus
 some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code.
 It is designed for large projects where fast simulation performance is of
 primary concern, and is especially well suited to generate executable models
 of CPUs for embedded software design teams.

verilator-dbgsym: debug symbols for verilator