verilator 4.028-1 source package in Ubuntu

Changelog

verilator (4.028-1) unstable; urgency=medium

  * New upstream version 4.028
  * Update standards version to 4.5.0
  * Drop typos.diff patch, applied upstream
  * Add interpreter.patch to set perl interpreter path

 -- أحمد المحمودي (Ahmed El-Mahmoudy) <email address hidden>  Sun, 09 Feb 2020 17:10:40 +0100

Upload details

Uploaded by:
Debian Electronics Team on 2020-02-09
Uploaded to:
Sid
Original maintainer:
Debian Electronics Team
Architectures:
any
Section:
electronics
Urgency:
Medium Urgency

See full publishing history Publishing

Series Pocket Published Component Section
Focal release on 2020-02-10 universe electronics

Downloads

File Size SHA-256 Checksum
verilator_4.028-1.dsc 1.7 KiB c22c8097e897c7c1108f57a2e4c1cf2e3c60b1ace24a514fed45c274623861b9
verilator_4.028.orig.tar.gz 2.3 MiB 344c859b105eb4d382ab89fbc515fd3bf915dc17bf75f90e918141afac1489e6
verilator_4.028-1.debian.tar.xz 8.8 KiB 095fb3d9cfadaaa6e869f37ad94dd76b6bcfabf6f8ef36781334bd3720ecf80e

Available diffs

No changes file available.

Binary packages built by this source

verilator: fast free Verilog simulator

 Verilator is the fastest free Verilog HDL simulator, and beats many commercial
 simulators. It compiles synthesizable Verilog (not test-bench code!), plus
 some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code.
 It is designed for large projects where fast simulation performance is of
 primary concern, and is especially well suited to generate executable models
 of CPUs for embedded software design teams.

verilator-dbgsym: debug symbols for verilator