Ubuntu
verilator package

verilator 4.026-1 source package in Ubuntu

Changelog

verilator (4.026-1) unstable; urgency=medium

  * New upstream version 4.026
  * Drop shebang.diff patch, no longer needed.
  * Refresh typos.diff patch
  * Update copyright years
  * Forward typos.diff patch upstream

 -- أحمد المحمودي (Ahmed El-Mahmoudy) <email address hidden>  Sun, 12 Jan 2020 03:06:03 +0100

Upload details

Uploaded by:
Debian Electronics Team
Uploaded to:
Sid
Original maintainer:
Debian Electronics Team
Architectures:
any
Section:
electronics
Urgency:
Medium Urgency

See full publishing history Publishing

Series Pocket Published Component Section

Downloads

File Size SHA-256 Checksum
verilator_4.026-1.dsc 1.7 KiB 1663beba3eb32b0506851b2f56d4f16fe8be459b0817c69540613d88c63fe89d
verilator_4.026.orig.tar.gz 2.3 MiB 6afb8ab04ab4e29e36f4b4cb04bb2c711e0af11843e41028ee1ea0d31eef9fac
verilator_4.026-1.debian.tar.xz 8.7 KiB 1939b0db016740b076f4d1f688dbd4000a33db154e813f0adf23596f1234b662

Available diffs

No changes file available.

Binary packages built by this source

verilator: fast free Verilog simulator

 Verilator is the fastest free Verilog HDL simulator, and beats many commercial
 simulators. It compiles synthesizable Verilog (not test-bench code!), plus
 some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code.
 It is designed for large projects where fast simulation performance is of
 primary concern, and is especially well suited to generate executable models
 of CPUs for embedded software design teams.

verilator-dbgsym: debug symbols for verilator