verilator 3.856-1 source package in Ubuntu

Changelog

verilator (3.856-1) unstable; urgency=medium


  * New upstream release.

 -- أحمد المحمودي (Ahmed El-Mahmoudy) <email address hidden>  Sun, 16 Mar 2014 21:30:31 +0200

Upload details

Uploaded by:
Debian Electronics Team
Uploaded to:
Sid
Original maintainer:
Debian Electronics Team
Architectures:
any
Section:
electronics
Urgency:
Medium Urgency

See full publishing history Publishing

Series Pocket Published Component Section
Trusty release universe electronics

Downloads

File Size SHA-256 Checksum
verilator_3.856-1.dsc 1.6 KiB d9d2440441348cd43128cfc36e95b25c39143f105e9c84b150c6e78ff2d058ef
verilator_3.856.orig.tar.gz 1.9 MiB 5f73c68e674988f4cfeca9ddbeb27eb2d49a8cd31927d95b16c69d7dbc4be1cd
verilator_3.856-1.debian.tar.xz 6.8 KiB 71067fc01620c40353739789ef718bd9d3d2f5abcc0d60833962bf36cef34790

Available diffs

No changes file available.

Binary packages built by this source

verilator: fast free Verilog simulator

 Verilator is the fastest free Verilog HDL simulator, and beats many commercial
 simulators. It compiles synthesizable Verilog (not test-bench code!), plus
 some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code.
 It is designed for large projects where fast simulation performance is of
 primary concern, and is especially well suited to generate executable models
 of CPUs for embedded software design teams.