diff -Nru u-boot-2021.01+dfsg/debian/bin/update-substvars u-boot-2021.01+dfsg/debian/bin/update-substvars --- u-boot-2021.01+dfsg/debian/bin/update-substvars 2021-03-06 21:48:06.000000000 +0000 +++ u-boot-2021.01+dfsg/debian/bin/update-substvars 2021-05-13 22:11:00.000000000 +0100 @@ -14,5 +14,9 @@ printf "uboot:Built-Using=$(dpkg-query -f '${source:Package} (= ${source:Version}) [arm64]' -W arm-trusted-firmware)\n"\ >> debian/${package}.substvars ;; + sifive) + printf "uboot:Built-Using=$(dpkg-query -f '${source:Package} (= ${source:Version}) [riscv64]' -W opensbi)\n"\ + >> debian/${package}.substvars + ;; esac done diff -Nru u-boot-2021.01+dfsg/debian/changelog u-boot-2021.01+dfsg/debian/changelog --- u-boot-2021.01+dfsg/debian/changelog 2021-03-12 23:00:43.000000000 +0000 +++ u-boot-2021.01+dfsg/debian/changelog 2021-05-18 11:07:17.000000000 +0100 @@ -1,3 +1,38 @@ +u-boot (2021.01+dfsg-4ubuntu1) impish; urgency=medium + + * Merge from Debian unstable (LP: #1928777). Remaining changes: + - d/p/rpi-config-tweaks.patch: Configuration adjustments to the RPi + configs + - Enable FIT signing support + - Limit key names to keys within the keydir. + - Enable Ubuntu support for the Nitrogen6x board + - Add d/p/ubuntu-nitrogen6q2g-config-tweaks.patch to tweak the + nitrogen6q2g configs to better fit our Ubuntu usage. + - Start building the nitrogen6x2g target for u-boot. + - d/p/rpi-board-dt.patch: use the board's device-tree instead of an + embedded one + - Enable u-boot spl for unleashed. + - Add d/p/rpi-cm4-sdhci.patch for CM4 eMMC support + - Add d/p/rpi-8gb-pci.patch for Pi400 and Pi4-8Gb support + - Add d/p/rpi-maxargs.patch for new Core 18 boot-env + - Import meta-sifive u-boot patches. + - Enable sifive_hifive_unmatched_fu740 target. + - Build-depend on opensbi with fu740 errata fix. + - Set default FDT files for the sifive boards. + - Set USE_PREBOOT on unmatched board too (just like unleashed & qemu), + otherwise u-boot's fdtfile from itb is not used (i.e. when extlinux.conf + does not specify fdtdir). LP: #1923162 + - Unapply unmatched patches, whilst building unleashed platform. Fixes + failure to boot from sd-card on Unleashed. LP: #1924761 + - Skip processing fdtdir on qemu-riscv64_smode target, as it crashes the + riscv qemu VM. LP: #1925267 LP: #1923162 + - sifive-unleashed-default-fdt-files.patch: split into unleashed & + unmatched separate patches, for ease of upstreaming to meta-sifive and + u-boot upstreams. Also this ensures that unleashed target is built with + fdtfile= set, as unleashed target unapplies lots of patches. + + -- Dave Jones Tue, 18 May 2021 11:07:17 +0100 + u-boot (2021.01+dfsg-4) unstable; urgency=medium [ Arnaud Ferraris ] @@ -13,6 +48,83 @@ -- Vagrant Cascadian Fri, 12 Mar 2021 15:00:43 -0800 +u-boot (2021.01+dfsg-3ubuntu9) hirsute; urgency=medium + + * sifive-unleashed-default-fdt-files.patch: split into unleashed & + unmatched separate patches, for ease of upstreaming to meta-sifive and + u-boot upstreams. Also this ensures that unleashed target is built + with fdtfile= set, as unleashed target unapplies lots of patches. + + -- Dimitri John Ledkov Wed, 21 Apr 2021 18:05:00 +0100 + +u-boot (2021.01+dfsg-3ubuntu8) hirsute; urgency=medium + + * Skip processing fdtdir on qemu-riscv64_smode target, as it crashes the + riscv qemu VM. LP: #1925267 LP: #1923162 + + -- Dimitri John Ledkov Wed, 21 Apr 2021 01:25:13 +0100 + +u-boot (2021.01+dfsg-3ubuntu7) hirsute; urgency=medium + + * Unapply unmatched patches, whilst building unleashed platform. Fixes + failure to boot from sd-card on Unleashed. LP: #1924761 + + -- Dimitri John Ledkov Fri, 16 Apr 2021 14:07:49 +0100 + +u-boot (2021.01+dfsg-3ubuntu6) hirsute; urgency=medium + + * Set USE_PREBOOT on unmatched board too (just like unleashed & qemu), + otherwise u-boot's fdtfile from itb is not used (i.e. when + extlinux.conf does not specify fdtdir). LP: #1923162 + + -- Dimitri John Ledkov Tue, 13 Apr 2021 14:52:32 +0100 + +u-boot (2021.01+dfsg-3ubuntu5) hirsute; urgency=medium + + * Set default FDT files for the sifive boards. + + -- Dimitri John Ledkov Tue, 16 Mar 2021 18:03:09 +0000 + +u-boot (2021.01+dfsg-3ubuntu4) hirsute; urgency=medium + + * Update patch for unmatched. + + -- Dimitri John Ledkov Mon, 15 Mar 2021 21:26:35 +0000 + +u-boot (2021.01+dfsg-3ubuntu3) hirsute; urgency=medium + + * Update patches for unmatched. + + -- Dimitri John Ledkov Mon, 15 Mar 2021 16:29:23 +0000 + +u-boot (2021.01+dfsg-3ubuntu2) hirsute; urgency=medium + + * Import meta-sifive u-boot patches. + * Enable sifive_hifive_unmatched_fu740 target. + * Build-depend on opensbi with fu740 errata fix. + + -- Dimitri John Ledkov Wed, 10 Mar 2021 12:27:57 +0000 + +u-boot (2021.01+dfsg-3ubuntu1) hirsute; urgency=medium + + * Merge from Debian unstable. Remaining changes: + - d/p/rpi-config-tweaks.patch: Configuration adjustments to the RPi + configs + - Enable FIT signing support + - Limit key names to keys within the keydir. + - Enable Ubuntu support for the Nitrogen6x board + - Add d/p/ubuntu-nitrogen6q2g-config-tweaks.patch to tweak the + nitrogen6q2g configs to better fit our Ubuntu usage. + - Start building the nitrogen6x2g target for u-boot. + - d/p/rpi-board-dt.patch: use the board's device-tree instead of an + embedded one + - Enable u-boot spl for unleashed. + - Add d/p/rpi-cm4-sdhci.patch for CM4 eMMC support + - Add d/p/rpi-8gb-pci.patch for Pi400 and Pi4-8Gb support + - Add d/p/rpi-maxargs.patch for new Core 18 boot-env + + -- Dave Jones Wed, 10 Mar 2021 12:02:04 +0000 + u-boot (2021.01+dfsg-3) unstable; urgency=medium [ Domenico Andreoli ] @@ -45,6 +157,33 @@ -- Vagrant Cascadian Mon, 01 Mar 2021 00:00:18 -0800 +u-boot (2021.01+dfsg-2ubuntu1) hirsute; urgency=medium + + * Merge from Debian unstable. Remaining changes: + - d/p/rpi-config-tweaks.patch: Configuration adjustments to the RPi + configs + - Enable FIT signing support + - Limit key names to keys within the keydir. + - Enable Ubuntu support for the Nitrogen6x board + - Add d/p/ubuntu-nitrogen6q2g-config-tweaks.patch to tweak the + nitrogen6q2g configs to better fit our Ubuntu usage. + - Start building the nitrogen6x2g target for u-boot. + - d/p/rpi-board-dt.patch: use the board's device-tree instead of an + embedded one + - Enable u-boot spl for unleashed. + - Add d/p/rpi-cm4-sdhci.patch for CM4 eMMC support + - Add d/p/rpi-8gb-pci.patch for Pi400 and Pi4-8Gb support + - Add d/p/rpi-maxargs.patch for new Core 18 boot-env + * Dropped changes, included in Debian: + - Enable FIT signing support + - Enable CONFIG_FIT_SIGNATURE so we can sign FIT images. + - Add libssl-dev to Build-Depends: to enable crypto functionality. + * Dropped changes, no longer needed: + - Added d/u-boot-rpi.postinst to install u-boot binaries + (previously unnoted) + + -- Dave Jones Thu, 18 Feb 2021 18:15:04 +0000 + u-boot (2021.01+dfsg-2) unstable; urgency=medium * debian/patches: Disable USE_PREBOOT on rockpro64 and pinebook-pro to @@ -160,6 +299,63 @@ -- Vagrant Cascadian Mon, 04 Jan 2021 19:59:11 -0800 +u-boot (2020.10+dfsg-1ubuntu6) hirsute; urgency=medium + + * Add d/p/rpi-8gb-pci.patch for Pi400 and Pi4-8Gb support (LP: #1906552) + * Add d/p/rpi-cm4-sdhci.patch for CM4 eMMC support + * Add d/p/rpi-maxargs.patch for new Core 18 boot-env (LP: #1910094) + * Remove redundant d/targets entries + + -- Dave Jones Thu, 10 Dec 2020 23:44:09 +0000 + +u-boot (2020.10+dfsg-1ubuntu5) hirsute; urgency=medium + + * Use flat binary rather than ELF OpenSBI; U-Boot SPL doesn't support ELF. + * Switch back to generic OpenSBI, as modern versions detect the platform. + + -- William Grant Mon, 21 Dec 2020 10:32:59 +1100 + +u-boot (2020.10+dfsg-1ubuntu4) hirsute; urgency=medium + + * Use the right opensbi fw_dynamic for fu540. + + -- Dimitri John Ledkov Tue, 08 Dec 2020 09:04:00 +0000 + +u-boot (2020.10+dfsg-1ubuntu3) hirsute; urgency=medium + + * Enable u-boot spl for unleashed. LP: #1905274 + + -- Dimitri John Ledkov Mon, 23 Nov 2020 12:51:03 +0000 + +u-boot (2020.10+dfsg-1ubuntu2) hirsute; urgency=medium + + * No-change rebuild to build with python3.9 as default. + + -- Matthias Klose Thu, 19 Nov 2020 18:38:58 +0100 + +u-boot (2020.10+dfsg-1ubuntu1) hirsute; urgency=low + + * Merge from Debian unstable. Remaining changes: + - Enable Ubuntu support for the Nitrogen6x board (LP: #1838064) + - Add d/p/ubuntu-nitrogen6q2g-config-tweaks.patch to tweak the + nitrogen6q2g configs to better fit our Ubuntu usage. + - Start building the nitrogen6x2g target for u-boot. + - Enable FIT signing support (LP: #1831942) + - Enable CONFIG_FIT_SIGNATURE so we can sign FIT images. + - Add libssl-dev to Build-Depends: to enable crypto functionality. + - Limit key names to keys within the keydir. + - d/p/rpi-config-tweaks.patch: Configuration adjustments to the RPi + configs + - d/p/rpi-board-dt.patch: use the board's device-tree instead of an + embedded one + + * Removed obsolete patches/changes: + - d/p/lzo-to-lzno.patch: use gzip instead of lzo compression for FIT + images as lzop in Ubuntu is in universe. This should be temporary and in + the next releases ideally we should follow what Debian does. + + -- Dave Jones Tue, 06 Oct 2020 03:18:18 +0000 + u-boot (2020.10+dfsg-1) unstable; urgency=medium * New upstream release. @@ -245,6 +441,53 @@ -- Vagrant Cascadian Mon, 18 May 2020 17:16:07 -0700 +u-boot (2020.04+dfsg-2ubuntu1) groovy; urgency=medium + + * Merge with 2020.04+dfsg-2 from Debian unstable. Remaining changes: + - Enable Ubuntu support for the Nitrogen6x board (LP: #1838064) + - Add d/p/ubuntu-nitrogen6q2g-config-tweaks.patch to tweak the + nitrogen6q2g configs to better fit our Ubuntu usage. + - Start building the nitrogen6x2g target for u-boot. + - Enable FIT signing support (LP: #1831942) + - Enable CONFIG_FIT_SIGNATURE so we can sign FIT images. + - Add libssl-dev to Build-Depends: to enable crypto functionality. + - Limit key names to keys within the keydir. + - d/p/rpi-config-tweaks.patch: Configuration adjustments to the RPi + configs + - d/p/lzo-to-lzno.patch: use gzip instead of lzo compression for FIT + images as lzop in Ubuntu is in universe. This should be temporary and in + the next releases ideally we should follow what Debian does. + - d/p/rpi-board-dt.patch: use the board's device-tree instead of an + embedded one + + * Removed obsolete patches/changes: + - Handle differing root partition labels during migration + - Add script to migrate old boot configurations to split, selective style + - Don't attempt config migration when /boot/firmware is a chroot + - Use vc4-fkms-v3d overlay on all models of Raspberry Pi + - Do not include the vc4-fkms-v3d overlay; this breaks book on the 3A+ + - Ensure boot.scr is from recent flash-kernel + - d/p/rpi-import-mkknlimg.patch import tools/mkknlimg from Xenial/raspi2 - + scripts/mkknlimg @ 83a3ebb + - Remove redundant d/p/rpi-import-mkknlimg.patch + - d/p/ubuntu-nitrogen6q2g-temporary-config-fixup.patch: + Fix bad CRC issue. The env size and redundant environment config + variables have not yet been migrated to Kconfig, so setting them in + _defconfig has no effect. Set those manually. + + * Removed patches obsoleted/merged by upstream: + - Use python2 for the build. + - Added d/p/python2.patch to fix-up remaining scripts still using bare + "python" + - d/p/am57xx/omap5_distro_bootcmd + - Correct odroid README paths + - Add d/p/rpi4.patch to support Raspberry Pi 4 boot + - Avoid device-tree memory fixup on Raspberry Pi 4; this allows access to + the all the RAM on models with more than 1Gb + - Add missing build dependency on arm/arm64 + + -- Dave Jones Sat, 16 May 2020 01:02:53 +0000 + u-boot (2020.04+dfsg-2) unstable; urgency=medium * debian/patches: @@ -390,6 +633,68 @@ -- Vagrant Cascadian Tue, 24 Sep 2019 01:03:23 -0700 +u-boot (2019.07+dfsg-1ubuntu6) focal; urgency=medium + + [ Ethan Hsieh ] + * d/p/ubuntu-nitrogen6q2g-temporary-config-fixup.patch: + Fix bad CRC issue. The env size and redundant environment config variables + have not yet been migrated to Kconfig, so setting them in _defconfig has + no effect. Set those manually. + + -- Łukasz 'sil2100' Zemczak Tue, 11 Feb 2020 11:43:57 +0100 + +u-boot (2019.07+dfsg-1ubuntu5) focal; urgency=medium + + [ Matthias Klose ] + * Use python2 for the build. + + [ Dave Jones ] + * Added d/p/python2.patch to fix-up remaining scripts still using bare + "python" + + -- Dave Jones Fri, 24 Jan 2020 11:29:15 +0000 + +u-boot (2019.07+dfsg-1ubuntu4) focal; urgency=medium + + * Do not include the vc4-fkms-v3d overlay; this breaks book on the 3A+ + (LP: #1848247) + * Handle differing root partition labels during migration + * Ensure boot.scr is from recent flash-kernel + + -- Dave Jones Fri, 17 Jan 2020 13:31:35 +0000 + +u-boot (2019.07+dfsg-1ubuntu3) eoan; urgency=medium + + * Avoid device-tree memory fixup on Raspberry Pi 4; this allows access to + the all the RAM on models with more than 1Gb (LP: #1847500) + + -- Dave Jones Sat, 12 Oct 2019 01:02:29 +0100 + +u-boot (2019.07+dfsg-1ubuntu2) eoan; urgency=medium + + * Don't attempt config migration when /boot/firmware is a chroot + * Use vc4-fkms-v3d overlay on all models of Raspberry Pi + + -- Dave Jones Wed, 09 Oct 2019 12:35:06 +0100 + +u-boot (2019.07+dfsg-1ubuntu1) eoan; urgency=medium + + * New upstream release to support Pi 4 boot (LP: #1846329) + * Removed patches applied upstream: + - d/p/dreamplug/Commit-ARM-CPU-arm926ejs-Consolidate-cache-routines-.patch + - d/p/mkimage/0001-fdt-Fix-mkimage-list-to-try-every-header-type.patch + - d/p/sunxi/teres-i.patch + * Updated patch: + - d/p/am57xx/omap5_distro_bootcmd + * Add missing build dependency on arm/arm64 + * Correct odroid README paths + * Add d/p/rpi4.patch to support Raspberry Pi 4 boot + * Remove redundant d/p/rpi-import-mkknlimg.patch + * Add script to migrate old boot configurations to split, selective style + * Use the board's device-tree instead of an embedded one + + -- Dave Jones Tue, 23 Jul 2019 10:02:04 +0000 + u-boot (2019.07+dfsg-1) experimental; urgency=medium * New upstream release. @@ -496,6 +801,48 @@ -- Vagrant Cascadian Fri, 03 May 2019 16:58:13 -0700 +u-boot (2019.04+dfsg-2ubuntu3) eoan; urgency=medium + + [ Shrirang Bagul ] + * Enable Ubuntu support for the Nitrogen6x board (LP: #1838064) + - Add d/p/ubuntu-nitrogen6q2g-config-tweaks.patch to tweak the + nitrogen6q2g configs to better fit our Ubuntu usage. + - Start building the nitrogen6x2g target for u-boot. + + -- Łukasz 'sil2100' Zemczak Tue, 03 Sep 2019 11:39:53 +0200 + +u-boot (2019.04+dfsg-2ubuntu2) eoan; urgency=low + + * Enable FIT signing support (LP: #1831942) + - Enable CONFIG_FIT_SIGNATURE so we can sign FIT images. + - Add libssl-dev to Build-Depends: to enable crypto functionality. + - Limit key names to keys within the keydir. + + -- Andy Whitcroft Mon, 10 Jun 2019 15:44:35 +0100 + +u-boot (2019.04+dfsg-2ubuntu1) eoan; urgency=medium + + * Merge with 2019.04+dfsg-2 from Debian experimental. Remaining changes: + - d/p/rpi-import-mkknlimg.patch import tools/mkknlimg from Xenial/raspi2 - + scripts/mkknlimg @ 83a3ebb + - d/p/rpi2-rpi3-config-tweaks.patch: basing on the earlier + rpi2-config-tweaks.patch, make configuration adjustments to the rpi2 and + rpi3 configs. + - d/u-boot-rpi.postinst: support the fact that we now ship multiple uboot + binaries for multiple Pi platforms in one package. Try to determine + which device we're running on and use the right binary during + upgrade/installation. * debian/patches: + - d/p/lzo-to-lzno.patch: use gzip instead of lzo compression for FIT + images as lzop in Ubuntu is in universe. This should be temporary and in + the next releases ideally we should follow what Debian does. + - debian/control: Add missing dependency on binutils (for strings) + (LP: #1814930) + - debian/patches: Refreshed patches. + * Obsoleted; applied upstream: + - Removed d/p/odroid-xu3/bootdelay + + -- Dave Jones Mon, 03 Jun 2019 14:41:23 +0000 + u-boot (2019.04+dfsg-2) experimental; urgency=medium [ Vagrant Cascadian ] @@ -696,6 +1043,29 @@ -- Vagrant Cascadian Mon, 09 Jul 2018 13:34:06 -0700 +u-boot (2018.07~rc3+dfsg1-0ubuntu2) disco; urgency=medium + + * d/control: Add missing dependency on binutils (for strings) (LP: #1814930) + + -- Dave Jones Wed, 06 Feb 2019 16:40:22 +0000 + +u-boot (2018.07~rc3+dfsg1-0ubuntu1) disco; urgency=medium + + * New interim upstream release. + - We pull in an rc version because that's the u-boot version we use in + our current core18 images and we want to provide 'feature parity'. + * debian/control: + - Added missing build-deps bison and flex. + * debian/patches: + - Refresh am57xx/omap5_distro_bootcmd. + - Refreshed patches. + - Removed odroid-xu3/bootdelay which was applied upstream. + - Add lzo-to-lzno.patch to use gzip instead of lzo compression for FIT + images as lzop in Ubuntu is in universe. This should be temporary and + in the next releases ideally we should follow what Debian does. + + -- Dave Jones Fri, 11 Jan 2019 16:43:27 +0000 + u-boot (2018.07~rc2+dfsg-1) experimental; urgency=medium * New upstream release candidate: @@ -757,6 +1127,26 @@ -- Vagrant Cascadian Tue, 17 Apr 2018 16:05:55 -0700 +u-boot (2018.03+dfsg1-2ubuntu2) disco; urgency=medium + + * debian/u-boot-rpi.postinst: + - Support the fact that we now ship multiple uboot binaries for multiple + Pi platforms in one package. Try to determine which device we're running + on and use the right binary during upgrade/installation. + + -- Łukasz 'sil2100' Zemczak Thu, 29 Nov 2018 01:16:07 +0100 + +u-boot (2018.03+dfsg1-2ubuntu1) cosmic; urgency=low + + * Merge from Debian unstable. Remaining changes: + - rpi-import-mkknlimg.patch import tools/mkknlimg from Xenial/raspi2 - + scripts/mkknlimg @ 83a3ebb + * debian/patches/rpi2-rpi3-config-tweaks.patch: basing on the earlier + rpi2-config-tweaks.patch, make configuration adjustments to the rpi2 and + rpi3 configs. + + -- Łukasz 'sil2100' Zemczak Fri, 27 Apr 2018 12:38:24 +0100 + u-boot (2018.03+dfsg1-2) unstable; urgency=medium [ Riku Voipio ] @@ -1233,6 +1623,26 @@ -- Vagrant Cascadian Sat, 30 Apr 2016 18:53:04 -0700 +u-boot (2016.03+dfsg1-6ubuntu2) zesty; urgency=medium + + * From upstream u-boot: (LP: #1636838) + - debian/patches/rpi-import-mkknlimg.patch: import tools/mkknlimg from + Xenial/raspi2 - scripts/mkknlimg @ 83a3ebb + - debian/u-boot-rpi.postinst: pass u-boot.bin through mkknlimg before + installing it as /boot/firmware/uboot.bin + - debian/patches/serial-pl01x-Add-support-for-devices-with-the-rate-p.patch: + Skip serial clock initialization when it's done by the firmware. + + -- Paolo Pisati Wed, 09 Nov 2016 17:09:29 +0200 + +u-boot (2016.03+dfsg1-6ubuntu1) yakkety; urgency=low + + * Merge from Debian unstable. Remaining changes: + - debian/patches/rpi2-config-tweaks.patch: configuration adjustments + to the RPi2 config. + + -- Steve Langasek Wed, 06 Jul 2016 17:30:44 -0700 + u-boot (2016.03+dfsg1-6) unstable; urgency=medium [ Vagrant Cascadian ] @@ -1254,6 +1664,14 @@ -- Vagrant Cascadian Tue, 28 Jun 2016 09:38:27 +0200 +u-boot (2016.03+dfsg1-5ubuntu1) yakkety; urgency=low + + * Merge from Debian unstable. Remaining changes: + - debian/patches/rpi2-config-tweaks.patch: configuration adjustments + to the RPi2 config. + + -- Steve Langasek Fri, 10 Jun 2016 21:46:33 -0700 + u-boot (2016.03+dfsg1-5) unstable; urgency=medium [ Vagrant Cascadian ] @@ -1279,6 +1697,14 @@ -- Vagrant Cascadian Sun, 29 May 2016 14:29:59 -0700 +u-boot (2016.03+dfsg1-4ubuntu1) yakkety; urgency=low + + * Merge from Debian unstable. Remaining changes: + - debian/patches/rpi2-config-tweaks.patch: configuration adjustments + to the RPi2 config. + + -- Steve Langasek Tue, 26 Apr 2016 21:06:04 -0700 + u-boot (2016.03+dfsg1-4) unstable; urgency=medium * Add patch to fix detected ram size on Firefly boards by reverting @@ -1337,6 +1763,14 @@ -- Vagrant Cascadian Tue, 16 Feb 2016 15:01:48 -0800 +u-boot (2016.01+dfsg1-2ubuntu1) xenial; urgency=low + + * Merge from Debian unstable. Remaining changes: + - debian/patches/rpi2-config-tweaks.patch: configuration adjustments + to the RPi2 config. + + -- Steve Langasek Thu, 11 Feb 2016 21:55:38 -0800 + u-boot (2016.01+dfsg1-2) unstable; urgency=medium * u-boot-omap: @@ -1350,6 +1784,13 @@ -- Vagrant Cascadian Mon, 08 Feb 2016 20:14:04 -0800 +u-boot (2016.01+dfsg1-1ubuntu1) xenial; urgency=medium + + * debian/patches/rpi2-config-tweaks.patch: configuration adjustments + to the RPi2 config. + + -- Steve Langasek Tue, 02 Feb 2016 11:43:50 -0800 + u-boot (2016.01+dfsg1-1) unstable; urgency=medium * u-boot-sunxi: Enable orangepi_plus target. @@ -2412,3 +2853,4 @@ * Initial packaging. closes: #583605. -- Clint Adams Fri, 28 May 2010 16:20:39 -0400 + diff -Nru u-boot-2021.01+dfsg/debian/control u-boot-2021.01+dfsg/debian/control --- u-boot-2021.01+dfsg/debian/control 2021-03-06 21:48:06.000000000 +0000 +++ u-boot-2021.01+dfsg/debian/control 2021-05-18 11:07:17.000000000 +0100 @@ -1,7 +1,8 @@ Source: u-boot Section: admin Priority: optional -Maintainer: Vagrant Cascadian +Maintainer: Ubuntu Developers +XSBC-Original-Maintainer: Vagrant Cascadian Uploaders: Loïc Minier , Clint Adams Build-Depends: arm-trusted-firmware (>= 2.4+dfsg) [arm64], @@ -15,6 +16,7 @@ libc6:armhf [armhf] , libc6:armel [armel] , libc6:riscv64 [riscv64] , + opensbi (>= 0.9-1ubuntu2~), libpython3-dev:native [linux-any], libssl-dev, python3:any [linux-any], @@ -22,6 +24,7 @@ python3-pkg-resources [linux-any], swig [linux-any], lzop [armhf], + quilt [riscv64], Build-Depends-Indep: # For u-boot-qemu targets gcc-i686-linux-gnu [!i386], @@ -210,6 +213,7 @@ Architecture: armel armhf arm64 Multi-Arch: same Depends: ${misc:Depends} +Breaks: flash-kernel (<< 3.104) Description: A boot loader for Raspberry PI systems Das U-Boot is a cross-platform bootloader for embedded systems, used as the default boot loader by several board vendors. It is @@ -224,6 +228,7 @@ Package: u-boot-sifive Architecture: riscv64 Multi-Arch: same +Built-Using: ${uboot:Built-Using} Depends: ${misc:Depends} Description: A boot loader for SiFive systems Das U-Boot is a cross-platform bootloader for embedded systems, diff -Nru u-boot-2021.01+dfsg/debian/patches/riscv64/0001-clk-sifive-fu540-prci-Extract-prci-core-to-common-ba.patch u-boot-2021.01+dfsg/debian/patches/riscv64/0001-clk-sifive-fu540-prci-Extract-prci-core-to-common-ba.patch --- u-boot-2021.01+dfsg/debian/patches/riscv64/0001-clk-sifive-fu540-prci-Extract-prci-core-to-common-ba.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/riscv64/0001-clk-sifive-fu540-prci-Extract-prci-core-to-common-ba.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,1671 @@ +From 0aa078320deda89f704a657f62a14768b562e733 Mon Sep 17 00:00:00 2001 +From: Pragnesh Patel +Date: Wed, 26 Aug 2020 16:41:57 +0530 +Subject: [PATCH 01/41] clk: sifive: fu540-prci: Extract prci core to common + base + +Extract common core of prci driver to an independent file, it could +allow other chips to reuse it. Separate SoCs-dependent code 'fu540' +from prci core, then we can easily add 'fu740' later. + +Signed-off-by: Pragnesh Patel +--- + drivers/clk/sifive/Makefile | 2 + + drivers/clk/sifive/fu540-prci.c | 769 ++------------------------------------- + drivers/clk/sifive/fu540-prci.h | 22 ++ + drivers/clk/sifive/sifive-prci.c | 558 ++++++++++++++++++++++++++++ + drivers/clk/sifive/sifive-prci.h | 224 ++++++++++++ + 5 files changed, 827 insertions(+), 748 deletions(-) + create mode 100644 drivers/clk/sifive/fu540-prci.h + create mode 100644 drivers/clk/sifive/sifive-prci.c + create mode 100644 drivers/clk/sifive/sifive-prci.h + +diff --git a/drivers/clk/sifive/Makefile b/drivers/clk/sifive/Makefile +index b224279..ea03494 100644 +--- a/drivers/clk/sifive/Makefile ++++ b/drivers/clk/sifive/Makefile +@@ -1,3 +1,5 @@ + # SPDX-License-Identifier: GPL-2.0+ + ++obj-y += sifive-prci.o ++ + obj-$(CONFIG_CLK_SIFIVE_FU540_PRCI) += fu540-prci.o +diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c +index 1b4d81d..ceb2c6f 100644 +--- a/drivers/clk/sifive/fu540-prci.c ++++ b/drivers/clk/sifive/fu540-prci.c +@@ -5,6 +5,8 @@ + * Copyright (C) 2018 SiFive, Inc. + * Wesley Terpstra + * Paul Walmsley ++ * Zong Li ++ * Pragnesh Patel + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as +@@ -15,632 +17,48 @@ + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * +- * The FU540 PRCI implements clock and reset control for the SiFive +- * FU540-C000 chip. This driver assumes that it has sole control +- * over all PRCI resources. +- * +- * This driver is based on the PRCI driver written by Wesley Terpstra. +- * +- * Refer, commit 999529edf517ed75b56659d456d221b2ee56bb60 of: +- * https://github.com/riscv/riscv-linux +- * + * References: + * - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset" + */ + +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include + #include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-/* +- * EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects: +- * hfclk and rtcclk +- */ +-#define EXPECTED_CLK_PARENT_COUNT 2 +- +-/* +- * Register offsets and bitmasks +- */ +- +-/* COREPLLCFG0 */ +-#define PRCI_COREPLLCFG0_OFFSET 0x4 +-#define PRCI_COREPLLCFG0_DIVR_SHIFT 0 +-#define PRCI_COREPLLCFG0_DIVR_MASK (0x3f << PRCI_COREPLLCFG0_DIVR_SHIFT) +-#define PRCI_COREPLLCFG0_DIVF_SHIFT 6 +-#define PRCI_COREPLLCFG0_DIVF_MASK (0x1ff << PRCI_COREPLLCFG0_DIVF_SHIFT) +-#define PRCI_COREPLLCFG0_DIVQ_SHIFT 15 +-#define PRCI_COREPLLCFG0_DIVQ_MASK (0x7 << PRCI_COREPLLCFG0_DIVQ_SHIFT) +-#define PRCI_COREPLLCFG0_RANGE_SHIFT 18 +-#define PRCI_COREPLLCFG0_RANGE_MASK (0x7 << PRCI_COREPLLCFG0_RANGE_SHIFT) +-#define PRCI_COREPLLCFG0_BYPASS_SHIFT 24 +-#define PRCI_COREPLLCFG0_BYPASS_MASK (0x1 << PRCI_COREPLLCFG0_BYPASS_SHIFT) +-#define PRCI_COREPLLCFG0_FSE_SHIFT 25 +-#define PRCI_COREPLLCFG0_FSE_MASK (0x1 << PRCI_COREPLLCFG0_FSE_SHIFT) +-#define PRCI_COREPLLCFG0_LOCK_SHIFT 31 +-#define PRCI_COREPLLCFG0_LOCK_MASK (0x1 << PRCI_COREPLLCFG0_LOCK_SHIFT) +- +-/* COREPLLCFG1 */ +-#define PRCI_COREPLLCFG1_OFFSET 0x8 +-#define PRCI_COREPLLCFG1_CKE_SHIFT 31 +-#define PRCI_COREPLLCFG1_CKE_MASK (0x1 << PRCI_COREPLLCFG1_CKE_SHIFT) +- +-/* DDRPLLCFG0 */ +-#define PRCI_DDRPLLCFG0_OFFSET 0xc +-#define PRCI_DDRPLLCFG0_DIVR_SHIFT 0 +-#define PRCI_DDRPLLCFG0_DIVR_MASK (0x3f << PRCI_DDRPLLCFG0_DIVR_SHIFT) +-#define PRCI_DDRPLLCFG0_DIVF_SHIFT 6 +-#define PRCI_DDRPLLCFG0_DIVF_MASK (0x1ff << PRCI_DDRPLLCFG0_DIVF_SHIFT) +-#define PRCI_DDRPLLCFG0_DIVQ_SHIFT 15 +-#define PRCI_DDRPLLCFG0_DIVQ_MASK (0x7 << PRCI_DDRPLLCFG0_DIVQ_SHIFT) +-#define PRCI_DDRPLLCFG0_RANGE_SHIFT 18 +-#define PRCI_DDRPLLCFG0_RANGE_MASK (0x7 << PRCI_DDRPLLCFG0_RANGE_SHIFT) +-#define PRCI_DDRPLLCFG0_BYPASS_SHIFT 24 +-#define PRCI_DDRPLLCFG0_BYPASS_MASK (0x1 << PRCI_DDRPLLCFG0_BYPASS_SHIFT) +-#define PRCI_DDRPLLCFG0_FSE_SHIFT 25 +-#define PRCI_DDRPLLCFG0_FSE_MASK (0x1 << PRCI_DDRPLLCFG0_FSE_SHIFT) +-#define PRCI_DDRPLLCFG0_LOCK_SHIFT 31 +-#define PRCI_DDRPLLCFG0_LOCK_MASK (0x1 << PRCI_DDRPLLCFG0_LOCK_SHIFT) +- +-/* DDRPLLCFG1 */ +-#define PRCI_DDRPLLCFG1_OFFSET 0x10 +-#define PRCI_DDRPLLCFG1_CKE_SHIFT 31 +-#define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT) +- +-/* GEMGXLPLLCFG0 */ +-#define PRCI_GEMGXLPLLCFG0_OFFSET 0x1c +-#define PRCI_GEMGXLPLLCFG0_DIVR_SHIFT 0 +-#define PRCI_GEMGXLPLLCFG0_DIVR_MASK \ +- (0x3f << PRCI_GEMGXLPLLCFG0_DIVR_SHIFT) +-#define PRCI_GEMGXLPLLCFG0_DIVF_SHIFT 6 +-#define PRCI_GEMGXLPLLCFG0_DIVF_MASK \ +- (0x1ff << PRCI_GEMGXLPLLCFG0_DIVF_SHIFT) +-#define PRCI_GEMGXLPLLCFG0_DIVQ_SHIFT 15 +-#define PRCI_GEMGXLPLLCFG0_DIVQ_MASK (0x7 << PRCI_GEMGXLPLLCFG0_DIVQ_SHIFT) +-#define PRCI_GEMGXLPLLCFG0_RANGE_SHIFT 18 +-#define PRCI_GEMGXLPLLCFG0_RANGE_MASK \ +- (0x7 << PRCI_GEMGXLPLLCFG0_RANGE_SHIFT) +-#define PRCI_GEMGXLPLLCFG0_BYPASS_SHIFT 24 +-#define PRCI_GEMGXLPLLCFG0_BYPASS_MASK \ +- (0x1 << PRCI_GEMGXLPLLCFG0_BYPASS_SHIFT) +-#define PRCI_GEMGXLPLLCFG0_FSE_SHIFT 25 +-#define PRCI_GEMGXLPLLCFG0_FSE_MASK \ +- (0x1 << PRCI_GEMGXLPLLCFG0_FSE_SHIFT) +-#define PRCI_GEMGXLPLLCFG0_LOCK_SHIFT 31 +-#define PRCI_GEMGXLPLLCFG0_LOCK_MASK (0x1 << PRCI_GEMGXLPLLCFG0_LOCK_SHIFT) +- +-/* GEMGXLPLLCFG1 */ +-#define PRCI_GEMGXLPLLCFG1_OFFSET 0x20 +-#define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 31 +-#define PRCI_GEMGXLPLLCFG1_CKE_MASK (0x1 << PRCI_GEMGXLPLLCFG1_CKE_SHIFT) +- +-/* CORECLKSEL */ +-#define PRCI_CORECLKSEL_OFFSET 0x24 +-#define PRCI_CORECLKSEL_CORECLKSEL_SHIFT 0 +-#define PRCI_CORECLKSEL_CORECLKSEL_MASK \ +- (0x1 << PRCI_CORECLKSEL_CORECLKSEL_SHIFT) +- +-/* DEVICESRESETREG */ +-#define PRCI_DEVICESRESETREG_OFFSET 0x28 +-#define PRCI_DEVICERESETCNT 5 +- +-#define PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_MASK \ +- (0x1 << PRCI_RST_DDR_CTRL_N) +-#define PRCI_DEVICESRESETREG_DDR_AXI_RST_N_MASK \ +- (0x1 << PRCI_RST_DDR_AXI_N) +-#define PRCI_DEVICESRESETREG_DDR_AHB_RST_N_MASK \ +- (0x1 << PRCI_RST_DDR_AHB_N) +-#define PRCI_DEVICESRESETREG_DDR_PHY_RST_N_MASK \ +- (0x1 << PRCI_RST_DDR_PHY_N) +-#define PRCI_DEVICESRESETREG_GEMGXL_RST_N_MASK \ +- (0x1 << PRCI_RST_GEMGXL_N) +- +-/* CLKMUXSTATUSREG */ +-#define PRCI_CLKMUXSTATUSREG_OFFSET 0x2c +-#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT 1 +-#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK \ +- (0x1 << PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT) +- +-/* PROCMONCFG */ +-#define PRCI_PROCMONCFG_OFFSET 0xF0 +-#define PRCI_PROCMONCFG_CORE_CLOCK_SHIFT 24 +-#define PRCI_PROCMONCFG_CORE_CLOCK_MASK \ +- (0x1 << PRCI_PROCMONCFG_CORE_CLOCK_SHIFT) +- +-/* +- * Private structures +- */ +- +-/** +- * struct __prci_data - per-device-instance data +- * @va: base virtual address of the PRCI IP block +- * @parent: parent clk instance +- * +- * PRCI per-device instance data +- */ +-struct __prci_data { +- void *va; +- struct clk parent_hfclk; +- struct clk parent_rtcclk; +-}; +- +-/** +- * struct __prci_wrpll_data - WRPLL configuration and integration data +- * @c: WRPLL current configuration record +- * @enable_bypass: fn ptr to code to bypass the WRPLL (if applicable; else NULL) +- * @disable_bypass: fn ptr to code to not bypass the WRPLL (or NULL) +- * @cfg0_offs: WRPLL CFG0 register offset (in bytes) from the PRCI base address +- * @cfg1_offs: WRPLL CFG1 register offset (in bytes) from the PRCI base address +- * @release_reset: fn ptr to code to release clock reset +- * +- * @enable_bypass and @disable_bypass are used for WRPLL instances +- * that contain a separate external glitchless clock mux downstream +- * from the PLL. The WRPLL internal bypass mux is not glitchless. +- */ +-struct __prci_wrpll_data { +- struct wrpll_cfg c; +- void (*enable_bypass)(struct __prci_data *pd); +- void (*disable_bypass)(struct __prci_data *pd); +- u8 cfg0_offs; +- u8 cfg1_offs; +- void (*release_reset)(struct __prci_data *pd); +-}; +- +-struct __prci_clock; +- +-/* struct __prci_clock_ops - clock operations */ +-struct __prci_clock_ops { +- int (*set_rate)(struct __prci_clock *pc, +- unsigned long rate, +- unsigned long parent_rate); +- unsigned long (*round_rate)(struct __prci_clock *pc, +- unsigned long rate, +- unsigned long *parent_rate); +- unsigned long (*recalc_rate)(struct __prci_clock *pc, +- unsigned long parent_rate); +- int (*enable_clk)(struct __prci_clock *pc, bool enable); +-}; +- +-/** +- * struct __prci_clock - describes a clock device managed by PRCI +- * @name: user-readable clock name string - should match the manual +- * @parent_name: parent name for this clock +- * @ops: struct __prci_clock_ops for control +- * @pwd: WRPLL-specific data, associated with this clock (if not NULL) +- * @pd: PRCI-specific data associated with this clock (if not NULL) +- * +- * PRCI clock data. Used by the PRCI driver to register PRCI-provided +- * clocks to the Linux clock infrastructure. +- */ +-struct __prci_clock { +- const char *name; +- const char *parent_name; +- const struct __prci_clock_ops *ops; +- struct __prci_wrpll_data *pwd; +- struct __prci_data *pd; +-}; +- +-/* +- * Private functions +- */ +- +-/** +- * __prci_readl() - read from a PRCI register +- * @pd: PRCI context +- * @offs: register offset to read from (in bytes, from PRCI base address) +- * +- * Read the register located at offset @offs from the base virtual +- * address of the PRCI register target described by @pd, and return +- * the value to the caller. +- * +- * Context: Any context. +- * +- * Return: the contents of the register described by @pd and @offs. +- */ +-static u32 __prci_readl(struct __prci_data *pd, u32 offs) +-{ +- return readl(pd->va + offs); +-} +- +-static void __prci_writel(u32 v, u32 offs, struct __prci_data *pd) +-{ +- writel(v, pd->va + offs); +-} +- +-/* WRPLL-related private functions */ +- +-/** +- * __prci_wrpll_unpack() - unpack WRPLL configuration registers into parameters +- * @c: ptr to a struct wrpll_cfg record to write config into +- * @r: value read from the PRCI PLL configuration register +- * +- * Given a value @r read from an FU540 PRCI PLL configuration register, +- * split it into fields and populate it into the WRPLL configuration record +- * pointed to by @c. +- * +- * The COREPLLCFG0 macros are used below, but the other *PLLCFG0 macros +- * have the same register layout. +- * +- * Context: Any context. +- */ +-static void __prci_wrpll_unpack(struct wrpll_cfg *c, u32 r) +-{ +- u32 v; +- +- v = r & PRCI_COREPLLCFG0_DIVR_MASK; +- v >>= PRCI_COREPLLCFG0_DIVR_SHIFT; +- c->divr = v; +- +- v = r & PRCI_COREPLLCFG0_DIVF_MASK; +- v >>= PRCI_COREPLLCFG0_DIVF_SHIFT; +- c->divf = v; +- +- v = r & PRCI_COREPLLCFG0_DIVQ_MASK; +- v >>= PRCI_COREPLLCFG0_DIVQ_SHIFT; +- c->divq = v; +- +- v = r & PRCI_COREPLLCFG0_RANGE_MASK; +- v >>= PRCI_COREPLLCFG0_RANGE_SHIFT; +- c->range = v; +- +- c->flags &= (WRPLL_FLAGS_INT_FEEDBACK_MASK | +- WRPLL_FLAGS_EXT_FEEDBACK_MASK); +- +- /* external feedback mode not supported */ +- c->flags |= WRPLL_FLAGS_INT_FEEDBACK_MASK; +-} +- +-/** +- * __prci_wrpll_pack() - pack PLL configuration parameters into a register value +- * @c: pointer to a struct wrpll_cfg record containing the PLL's cfg +- * +- * Using a set of WRPLL configuration values pointed to by @c, +- * assemble a PRCI PLL configuration register value, and return it to +- * the caller. +- * +- * Context: Any context. Caller must ensure that the contents of the +- * record pointed to by @c do not change during the execution +- * of this function. +- * +- * Returns: a value suitable for writing into a PRCI PLL configuration +- * register +- */ +-static u32 __prci_wrpll_pack(const struct wrpll_cfg *c) +-{ +- u32 r = 0; +- +- r |= c->divr << PRCI_COREPLLCFG0_DIVR_SHIFT; +- r |= c->divf << PRCI_COREPLLCFG0_DIVF_SHIFT; +- r |= c->divq << PRCI_COREPLLCFG0_DIVQ_SHIFT; +- r |= c->range << PRCI_COREPLLCFG0_RANGE_SHIFT; +- +- /* external feedback mode not supported */ +- r |= PRCI_COREPLLCFG0_FSE_MASK; +- +- return r; +-} +- +-/** +- * __prci_wrpll_read_cfg0() - read the WRPLL configuration from the PRCI +- * @pd: PRCI context +- * @pwd: PRCI WRPLL metadata +- * +- * Read the current configuration of the PLL identified by @pwd from +- * the PRCI identified by @pd, and store it into the local configuration +- * cache in @pwd. +- * +- * Context: Any context. Caller must prevent the records pointed to by +- * @pd and @pwd from changing during execution. +- */ +-static void __prci_wrpll_read_cfg0(struct __prci_data *pd, +- struct __prci_wrpll_data *pwd) +-{ +- __prci_wrpll_unpack(&pwd->c, __prci_readl(pd, pwd->cfg0_offs)); +-} +- +-/** +- * __prci_wrpll_write_cfg0() - write WRPLL configuration into the PRCI +- * @pd: PRCI context +- * @pwd: PRCI WRPLL metadata +- * @c: WRPLL configuration record to write +- * +- * Write the WRPLL configuration described by @c into the WRPLL +- * configuration register identified by @pwd in the PRCI instance +- * described by @c. Make a cached copy of the WRPLL's current +- * configuration so it can be used by other code. +- * +- * Context: Any context. Caller must prevent the records pointed to by +- * @pd and @pwd from changing during execution. +- */ +-static void __prci_wrpll_write_cfg0(struct __prci_data *pd, +- struct __prci_wrpll_data *pwd, +- struct wrpll_cfg *c) +-{ +- __prci_writel(__prci_wrpll_pack(c), pwd->cfg0_offs, pd); +- +- memcpy(&pwd->c, c, sizeof(*c)); +-} +- +-/** +- * __prci_wrpll_write_cfg1() - write Clock enable/disable configuration +- * into the PRCI +- * @pd: PRCI context +- * @pwd: PRCI WRPLL metadata +- * @enable: Clock enable or disable value +- */ +-static void __prci_wrpll_write_cfg1(struct __prci_data *pd, +- struct __prci_wrpll_data *pwd, +- u32 enable) +-{ +- __prci_writel(enable, pwd->cfg1_offs, pd); +-} +- +-/* Core clock mux control */ +- +-/** +- * __prci_coreclksel_use_hfclk() - switch the CORECLK mux to output HFCLK +- * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg +- * +- * Switch the CORECLK mux to the HFCLK input source; return once complete. +- * +- * Context: Any context. Caller must prevent concurrent changes to the +- * PRCI_CORECLKSEL_OFFSET register. +- */ +-static void __prci_coreclksel_use_hfclk(struct __prci_data *pd) +-{ +- u32 r; +- +- r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); +- r |= PRCI_CORECLKSEL_CORECLKSEL_MASK; +- __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd); +- +- r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */ +-} +- +-/** +- * __prci_coreclksel_use_corepll() - switch the CORECLK mux to output COREPLL +- * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg +- * +- * Switch the CORECLK mux to the PLL output clock; return once complete. +- * +- * Context: Any context. Caller must prevent concurrent changes to the +- * PRCI_CORECLKSEL_OFFSET register. +- */ +-static void __prci_coreclksel_use_corepll(struct __prci_data *pd) +-{ +- u32 r; +- +- r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); +- r &= ~PRCI_CORECLKSEL_CORECLKSEL_MASK; +- __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd); +- +- r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */ +-} +- +-static unsigned long sifive_fu540_prci_wrpll_recalc_rate( +- struct __prci_clock *pc, +- unsigned long parent_rate) +-{ +- struct __prci_wrpll_data *pwd = pc->pwd; + +- return wrpll_calc_output_rate(&pwd->c, parent_rate); +-} +- +-static unsigned long sifive_fu540_prci_wrpll_round_rate( +- struct __prci_clock *pc, +- unsigned long rate, +- unsigned long *parent_rate) +-{ +- struct __prci_wrpll_data *pwd = pc->pwd; +- struct wrpll_cfg c; +- +- memcpy(&c, &pwd->c, sizeof(c)); +- +- wrpll_configure_for_rate(&c, rate, *parent_rate); +- +- return wrpll_calc_output_rate(&c, *parent_rate); +-} +- +-static int sifive_fu540_prci_wrpll_set_rate(struct __prci_clock *pc, +- unsigned long rate, +- unsigned long parent_rate) +-{ +- struct __prci_wrpll_data *pwd = pc->pwd; +- struct __prci_data *pd = pc->pd; +- int r; +- +- r = wrpll_configure_for_rate(&pwd->c, rate, parent_rate); +- if (r) +- return r; +- +- if (pwd->enable_bypass) +- pwd->enable_bypass(pd); +- +- __prci_wrpll_write_cfg0(pd, pwd, &pwd->c); +- +- udelay(wrpll_calc_max_lock_us(&pwd->c)); +- +- if (pwd->disable_bypass) +- pwd->disable_bypass(pd); +- +- return 0; +-} +- +-static int sifive_fu540_prci_clock_enable(struct __prci_clock *pc, bool enable) +-{ +- struct __prci_wrpll_data *pwd = pc->pwd; +- struct __prci_data *pd = pc->pd; +- +- if (enable) { +- __prci_wrpll_write_cfg1(pd, pwd, PRCI_COREPLLCFG1_CKE_MASK); +- +- if (pwd->release_reset) +- pwd->release_reset(pd); +- } else { +- u32 r; +- +- r = __prci_readl(pd, pwd->cfg1_offs); +- r &= ~PRCI_COREPLLCFG1_CKE_MASK; +- +- __prci_wrpll_write_cfg1(pd, pwd, r); +- } +- +- return 0; +-} +- +-static const struct __prci_clock_ops sifive_fu540_prci_wrpll_clk_ops = { +- .set_rate = sifive_fu540_prci_wrpll_set_rate, +- .round_rate = sifive_fu540_prci_wrpll_round_rate, +- .recalc_rate = sifive_fu540_prci_wrpll_recalc_rate, +- .enable_clk = sifive_fu540_prci_clock_enable, +-}; +- +-/* TLCLKSEL clock integration */ +- +-static unsigned long sifive_fu540_prci_tlclksel_recalc_rate( +- struct __prci_clock *pc, +- unsigned long parent_rate) +-{ +- struct __prci_data *pd = pc->pd; +- u32 v; +- u8 div; +- +- v = __prci_readl(pd, PRCI_CLKMUXSTATUSREG_OFFSET); +- v &= PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK; +- div = v ? 1 : 2; +- +- return div_u64(parent_rate, div); +-} +- +-static const struct __prci_clock_ops sifive_fu540_prci_tlclksel_clk_ops = { +- .recalc_rate = sifive_fu540_prci_tlclksel_recalc_rate, +-}; +- +-static int __prci_consumer_reset(const char *rst_name, bool trigger) +-{ +- struct udevice *dev; +- struct reset_ctl rst_sig; +- int ret; +- +- ret = uclass_get_device_by_driver(UCLASS_RESET, +- DM_GET_DRIVER(sifive_reset), +- &dev); +- if (ret) { +- dev_err(dev, "Reset driver not found: %d\n", ret); +- return ret; +- } +- +- ret = reset_get_by_name(dev, rst_name, &rst_sig); +- if (ret) { +- dev_err(dev, "failed to get %s reset\n", rst_name); +- return ret; +- } +- +- if (reset_valid(&rst_sig)) { +- if (trigger) +- ret = reset_deassert(&rst_sig); +- else +- ret = reset_assert(&rst_sig); +- if (ret) { +- dev_err(dev, "failed to trigger reset id = %ld\n", +- rst_sig.id); +- return ret; +- } +- } +- +- return ret; +-} +- +-/** +- * __prci_ddr_release_reset() - Release DDR reset +- * @pd: struct __prci_data * for the PRCI containing the DDRCLK mux reg +- * +- */ +-static void __prci_ddr_release_reset(struct __prci_data *pd) +-{ +- /* Release DDR ctrl reset */ +- __prci_consumer_reset("ddr_ctrl", true); +- +- /* HACK to get the '1 full controller clock cycle'. */ +- asm volatile ("fence"); +- +- /* Release DDR AXI reset */ +- __prci_consumer_reset("ddr_axi", true); +- +- /* Release DDR AHB reset */ +- __prci_consumer_reset("ddr_ahb", true); +- +- /* Release DDR PHY reset */ +- __prci_consumer_reset("ddr_phy", true); +- +- /* HACK to get the '1 full controller clock cycle'. */ +- asm volatile ("fence"); +- +- /* +- * These take like 16 cycles to actually propagate. We can't go sending +- * stuff before they come out of reset. So wait. +- */ +- for (int i = 0; i < 256; i++) +- asm volatile ("nop"); +-} +- +-/** +- * __prci_ethernet_release_reset() - Release ethernet reset +- * @pd: struct __prci_data * for the PRCI containing the Ethernet CLK mux reg +- * +- */ +-static void __prci_ethernet_release_reset(struct __prci_data *pd) +-{ +- /* Release GEMGXL reset */ +- __prci_consumer_reset("gemgxl_reset", true); +- +- /* Procmon => core clock */ +- __prci_writel(PRCI_PROCMONCFG_CORE_CLOCK_MASK, PRCI_PROCMONCFG_OFFSET, +- pd); +-} +- +-/* +- * PRCI integration data for each WRPLL instance +- */ ++#include "sifive-prci.h" + ++/* PRCI integration data for each WRPLL instance */ + static struct __prci_wrpll_data __prci_corepll_data = { + .cfg0_offs = PRCI_COREPLLCFG0_OFFSET, + .cfg1_offs = PRCI_COREPLLCFG1_OFFSET, +- .enable_bypass = __prci_coreclksel_use_hfclk, +- .disable_bypass = __prci_coreclksel_use_corepll, ++ .enable_bypass = sifive_prci_coreclksel_use_hfclk, ++ .disable_bypass = sifive_prci_coreclksel_use_corepll, + }; + + static struct __prci_wrpll_data __prci_ddrpll_data = { + .cfg0_offs = PRCI_DDRPLLCFG0_OFFSET, + .cfg1_offs = PRCI_DDRPLLCFG1_OFFSET, +- .release_reset = __prci_ddr_release_reset, ++ .release_reset = sifive_prci_ddr_release_reset, + }; + + static struct __prci_wrpll_data __prci_gemgxlpll_data = { + .cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET, + .cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET, +- .release_reset = __prci_ethernet_release_reset, ++ .release_reset = sifive_prci_ethernet_release_reset, + }; + +-/* +- * List of clock controls provided by the PRCI +- */ ++/* Linux clock framework integration */ ++static const struct __prci_clock_ops sifive_fu540_prci_wrpll_clk_ops = { ++ .set_rate = sifive_prci_wrpll_set_rate, ++ .round_rate = sifive_prci_wrpll_round_rate, ++ .recalc_rate = sifive_prci_wrpll_recalc_rate, ++ .enable_clk = sifive_prci_clock_enable, ++}; + +-static struct __prci_clock __prci_init_clocks[] = { ++static const struct __prci_clock_ops sifive_fu540_prci_tlclksel_clk_ops = { ++ .recalc_rate = sifive_prci_tlclksel_recalc_rate, ++}; ++ ++/* List of clock controls provided by the PRCI */ ++struct __prci_clock __prci_init_clocks_fu540[] = { + [PRCI_CLK_COREPLL] = { + .name = "corepll", + .parent_name = "hfclk", +@@ -665,148 +83,3 @@ static struct __prci_clock __prci_init_clocks[] = { + .ops = &sifive_fu540_prci_tlclksel_clk_ops, + }, + }; +- +-static ulong sifive_fu540_prci_parent_rate(struct __prci_clock *pc) +-{ +- ulong parent_rate; +- struct __prci_clock *p; +- +- if (strcmp(pc->parent_name, "corepll") == 0) { +- p = &__prci_init_clocks[PRCI_CLK_COREPLL]; +- if (!p->pd || !p->ops->recalc_rate) +- return -ENXIO; +- +- return p->ops->recalc_rate(p, sifive_fu540_prci_parent_rate(p)); +- } +- +- if (strcmp(pc->parent_name, "rtcclk") == 0) +- parent_rate = clk_get_rate(&pc->pd->parent_rtcclk); +- else +- parent_rate = clk_get_rate(&pc->pd->parent_hfclk); +- +- return parent_rate; +-} +- +-static ulong sifive_fu540_prci_get_rate(struct clk *clk) +-{ +- struct __prci_clock *pc; +- +- if (ARRAY_SIZE(__prci_init_clocks) <= clk->id) +- return -ENXIO; +- +- pc = &__prci_init_clocks[clk->id]; +- if (!pc->pd || !pc->ops->recalc_rate) +- return -ENXIO; +- +- return pc->ops->recalc_rate(pc, sifive_fu540_prci_parent_rate(pc)); +-} +- +-static ulong sifive_fu540_prci_set_rate(struct clk *clk, ulong rate) +-{ +- int err; +- struct __prci_clock *pc; +- +- if (ARRAY_SIZE(__prci_init_clocks) <= clk->id) +- return -ENXIO; +- +- pc = &__prci_init_clocks[clk->id]; +- if (!pc->pd || !pc->ops->set_rate) +- return -ENXIO; +- +- err = pc->ops->set_rate(pc, rate, sifive_fu540_prci_parent_rate(pc)); +- if (err) +- return err; +- +- return rate; +-} +- +-static int sifive_fu540_prci_enable(struct clk *clk) +-{ +- struct __prci_clock *pc; +- int ret = 0; +- +- if (ARRAY_SIZE(__prci_init_clocks) <= clk->id) +- return -ENXIO; +- +- pc = &__prci_init_clocks[clk->id]; +- if (!pc->pd) +- return -ENXIO; +- +- if (pc->ops->enable_clk) +- ret = pc->ops->enable_clk(pc, 1); +- +- return ret; +-} +- +-static int sifive_fu540_prci_disable(struct clk *clk) +-{ +- struct __prci_clock *pc; +- int ret = 0; +- +- if (ARRAY_SIZE(__prci_init_clocks) <= clk->id) +- return -ENXIO; +- +- pc = &__prci_init_clocks[clk->id]; +- if (!pc->pd) +- return -ENXIO; +- +- if (pc->ops->enable_clk) +- ret = pc->ops->enable_clk(pc, 0); +- +- return ret; +-} +- +-static int sifive_fu540_prci_probe(struct udevice *dev) +-{ +- int i, err; +- struct __prci_clock *pc; +- struct __prci_data *pd = dev_get_priv(dev); +- +- pd->va = (void *)dev_read_addr(dev); +- if (IS_ERR(pd->va)) +- return PTR_ERR(pd->va); +- +- err = clk_get_by_index(dev, 0, &pd->parent_hfclk); +- if (err) +- return err; +- +- err = clk_get_by_index(dev, 1, &pd->parent_rtcclk); +- if (err) +- return err; +- +- for (i = 0; i < ARRAY_SIZE(__prci_init_clocks); ++i) { +- pc = &__prci_init_clocks[i]; +- pc->pd = pd; +- if (pc->pwd) +- __prci_wrpll_read_cfg0(pd, pc->pwd); +- } +- +- return 0; +-} +- +-static struct clk_ops sifive_fu540_prci_ops = { +- .set_rate = sifive_fu540_prci_set_rate, +- .get_rate = sifive_fu540_prci_get_rate, +- .enable = sifive_fu540_prci_enable, +- .disable = sifive_fu540_prci_disable, +-}; +- +-static int sifive_fu540_clk_bind(struct udevice *dev) +-{ +- return sifive_reset_bind(dev, PRCI_DEVICERESETCNT); +-} +- +-static const struct udevice_id sifive_fu540_prci_ids[] = { +- { .compatible = "sifive,fu540-c000-prci" }, +- { } +-}; +- +-U_BOOT_DRIVER(sifive_fu540_prci) = { +- .name = "sifive-fu540-prci", +- .id = UCLASS_CLK, +- .of_match = sifive_fu540_prci_ids, +- .probe = sifive_fu540_prci_probe, +- .ops = &sifive_fu540_prci_ops, +- .priv_auto_alloc_size = sizeof(struct __prci_data), +- .bind = sifive_fu540_clk_bind, +-}; +diff --git a/drivers/clk/sifive/fu540-prci.h b/drivers/clk/sifive/fu540-prci.h +new file mode 100644 +index 0000000..8cbe85d +--- /dev/null ++++ b/drivers/clk/sifive/fu540-prci.h +@@ -0,0 +1,22 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Copyright (C) 2020 SiFive, Inc. ++ * Zong Li ++ * Pragnesh Patel ++ */ ++ ++#ifndef __SIFIVE_CLK_FU540_PRCI_H ++#define __SIFIVE_CLK_FU540_PRCI_H ++ ++#include "sifive-prci.h" ++ ++#define NUM_CLOCK_FU540 4 ++ ++extern struct __prci_clock __prci_init_clocks_fu540[NUM_CLOCK_FU540]; ++ ++static const struct prci_clk_desc prci_clk_fu540 = { ++ .clks = __prci_init_clocks_fu540, ++ .num_clks = ARRAY_SIZE(__prci_init_clocks_fu540), ++}; ++ ++#endif /* __SIFIVE_CLK_FU540_PRCI_H */ +diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c +new file mode 100644 +index 0000000..b96491b +--- /dev/null ++++ b/drivers/clk/sifive/sifive-prci.c +@@ -0,0 +1,558 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) 2018-2019 SiFive, Inc. ++ * Wesley Terpstra ++ * Paul Walmsley ++ * Zong Li ++ * Pragnesh Patel ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * The PRCI implements clock and reset control for the SiFive chip. ++ * This driver assumes that it has sole control over all PRCI resources. ++ * ++ * This driver is based on the PRCI driver written by Wesley Terpstra: ++ * https://github.com/riscv/riscv-linux/commit/999529edf517ed75b56659d456d221b2ee56bb60 ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "fu540-prci.h" ++ ++/* ++ * Private functions ++ */ ++ ++/** ++ * __prci_readl() - read from a PRCI register ++ * @pd: PRCI context ++ * @offs: register offset to read from (in bytes, from PRCI base address) ++ * ++ * Read the register located at offset @offs from the base virtual ++ * address of the PRCI register target described by @pd, and return ++ * the value to the caller. ++ * ++ * Context: Any context. ++ * ++ * Return: the contents of the register described by @pd and @offs. ++ */ ++static u32 __prci_readl(struct __prci_data *pd, u32 offs) ++{ ++ return readl(pd->va + offs); ++} ++ ++static void __prci_writel(u32 v, u32 offs, struct __prci_data *pd) ++{ ++ writel(v, pd->va + offs); ++} ++ ++/* WRPLL-related private functions */ ++ ++/** ++ * __prci_wrpll_unpack() - unpack WRPLL configuration registers into parameters ++ * @c: ptr to a struct wrpll_cfg record to write config into ++ * @r: value read from the PRCI PLL configuration register ++ * ++ * Given a value @r read from an FU540 PRCI PLL configuration register, ++ * split it into fields and populate it into the WRPLL configuration record ++ * pointed to by @c. ++ * ++ * The COREPLLCFG0 macros are used below, but the other *PLLCFG0 macros ++ * have the same register layout. ++ * ++ * Context: Any context. ++ */ ++static void __prci_wrpll_unpack(struct wrpll_cfg *c, u32 r) ++{ ++ u32 v; ++ ++ v = r & PRCI_COREPLLCFG0_DIVR_MASK; ++ v >>= PRCI_COREPLLCFG0_DIVR_SHIFT; ++ c->divr = v; ++ ++ v = r & PRCI_COREPLLCFG0_DIVF_MASK; ++ v >>= PRCI_COREPLLCFG0_DIVF_SHIFT; ++ c->divf = v; ++ ++ v = r & PRCI_COREPLLCFG0_DIVQ_MASK; ++ v >>= PRCI_COREPLLCFG0_DIVQ_SHIFT; ++ c->divq = v; ++ ++ v = r & PRCI_COREPLLCFG0_RANGE_MASK; ++ v >>= PRCI_COREPLLCFG0_RANGE_SHIFT; ++ c->range = v; ++ ++ c->flags &= (WRPLL_FLAGS_INT_FEEDBACK_MASK | ++ WRPLL_FLAGS_EXT_FEEDBACK_MASK); ++ ++ /* external feedback mode not supported */ ++ c->flags |= WRPLL_FLAGS_INT_FEEDBACK_MASK; ++} ++ ++/** ++ * __prci_wrpll_pack() - pack PLL configuration parameters into a register value ++ * @c: pointer to a struct wrpll_cfg record containing the PLL's cfg ++ * ++ * Using a set of WRPLL configuration values pointed to by @c, ++ * assemble a PRCI PLL configuration register value, and return it to ++ * the caller. ++ * ++ * Context: Any context. Caller must ensure that the contents of the ++ * record pointed to by @c do not change during the execution ++ * of this function. ++ * ++ * Returns: a value suitable for writing into a PRCI PLL configuration ++ * register ++ */ ++static u32 __prci_wrpll_pack(const struct wrpll_cfg *c) ++{ ++ u32 r = 0; ++ ++ r |= c->divr << PRCI_COREPLLCFG0_DIVR_SHIFT; ++ r |= c->divf << PRCI_COREPLLCFG0_DIVF_SHIFT; ++ r |= c->divq << PRCI_COREPLLCFG0_DIVQ_SHIFT; ++ r |= c->range << PRCI_COREPLLCFG0_RANGE_SHIFT; ++ ++ /* external feedback mode not supported */ ++ r |= PRCI_COREPLLCFG0_FSE_MASK; ++ ++ return r; ++} ++ ++/** ++ * __prci_wrpll_read_cfg0() - read the WRPLL configuration from the PRCI ++ * @pd: PRCI context ++ * @pwd: PRCI WRPLL metadata ++ * ++ * Read the current configuration of the PLL identified by @pwd from ++ * the PRCI identified by @pd, and store it into the local configuration ++ * cache in @pwd. ++ * ++ * Context: Any context. Caller must prevent the records pointed to by ++ * @pd and @pwd from changing during execution. ++ */ ++static void __prci_wrpll_read_cfg0(struct __prci_data *pd, ++ struct __prci_wrpll_data *pwd) ++{ ++ __prci_wrpll_unpack(&pwd->c, __prci_readl(pd, pwd->cfg0_offs)); ++} ++ ++/** ++ * __prci_wrpll_write_cfg0() - write WRPLL configuration into the PRCI ++ * @pd: PRCI context ++ * @pwd: PRCI WRPLL metadata ++ * @c: WRPLL configuration record to write ++ * ++ * Write the WRPLL configuration described by @c into the WRPLL ++ * configuration register identified by @pwd in the PRCI instance ++ * described by @c. Make a cached copy of the WRPLL's current ++ * configuration so it can be used by other code. ++ * ++ * Context: Any context. Caller must prevent the records pointed to by ++ * @pd and @pwd from changing during execution. ++ */ ++static void __prci_wrpll_write_cfg0(struct __prci_data *pd, ++ struct __prci_wrpll_data *pwd, ++ struct wrpll_cfg *c) ++{ ++ __prci_writel(__prci_wrpll_pack(c), pwd->cfg0_offs, pd); ++ ++ memcpy(&pwd->c, c, sizeof(*c)); ++} ++ ++/** ++ * __prci_wrpll_write_cfg1() - write Clock enable/disable configuration ++ * into the PRCI ++ * @pd: PRCI context ++ * @pwd: PRCI WRPLL metadata ++ * @enable: Clock enable or disable value ++ */ ++static void __prci_wrpll_write_cfg1(struct __prci_data *pd, ++ struct __prci_wrpll_data *pwd, ++ u32 enable) ++{ ++ __prci_writel(enable, pwd->cfg1_offs, pd); ++} ++ ++unsigned long sifive_prci_wrpll_recalc_rate(struct __prci_clock *pc, ++ unsigned long parent_rate) ++{ ++ struct __prci_wrpll_data *pwd = pc->pwd; ++ ++ return wrpll_calc_output_rate(&pwd->c, parent_rate); ++} ++ ++unsigned long sifive_prci_wrpll_round_rate(struct __prci_clock *pc, ++ unsigned long rate, ++ unsigned long *parent_rate) ++{ ++ struct __prci_wrpll_data *pwd = pc->pwd; ++ struct wrpll_cfg c; ++ ++ memcpy(&c, &pwd->c, sizeof(c)); ++ ++ wrpll_configure_for_rate(&c, rate, *parent_rate); ++ ++ return wrpll_calc_output_rate(&c, *parent_rate); ++} ++ ++int sifive_prci_wrpll_set_rate(struct __prci_clock *pc, ++ unsigned long rate, ++ unsigned long parent_rate) ++{ ++ struct __prci_wrpll_data *pwd = pc->pwd; ++ struct __prci_data *pd = pc->pd; ++ int r; ++ ++ r = wrpll_configure_for_rate(&pwd->c, rate, parent_rate); ++ if (r) ++ return r; ++ ++ if (pwd->enable_bypass) ++ pwd->enable_bypass(pd); ++ ++ __prci_wrpll_write_cfg0(pd, pwd, &pwd->c); ++ ++ udelay(wrpll_calc_max_lock_us(&pwd->c)); ++ ++ if (pwd->disable_bypass) ++ pwd->disable_bypass(pd); ++ ++ return 0; ++} ++ ++int sifive_prci_clock_enable(struct __prci_clock *pc, bool enable) ++{ ++ struct __prci_wrpll_data *pwd = pc->pwd; ++ struct __prci_data *pd = pc->pd; ++ ++ if (enable) { ++ __prci_wrpll_write_cfg1(pd, pwd, PRCI_COREPLLCFG1_CKE_MASK); ++ ++ if (pwd->release_reset) ++ pwd->release_reset(pd); ++ } else { ++ u32 r; ++ ++ r = __prci_readl(pd, pwd->cfg1_offs); ++ r &= ~PRCI_COREPLLCFG1_CKE_MASK; ++ ++ __prci_wrpll_write_cfg1(pd, pwd, r); ++ } ++ ++ return 0; ++} ++ ++/* TLCLKSEL clock integration */ ++ ++unsigned long sifive_prci_tlclksel_recalc_rate(struct __prci_clock *pc, ++ unsigned long parent_rate) ++{ ++ struct __prci_data *pd = pc->pd; ++ u32 v; ++ u8 div; ++ ++ v = __prci_readl(pd, PRCI_CLKMUXSTATUSREG_OFFSET); ++ v &= PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK; ++ div = v ? 1 : 2; ++ ++ return div_u64(parent_rate, div); ++} ++ ++static int __prci_consumer_reset(const char *rst_name, bool trigger) ++{ ++ struct udevice *dev; ++ struct reset_ctl rst_sig; ++ int ret; ++ ++ ret = uclass_get_device_by_driver(UCLASS_RESET, ++ DM_GET_DRIVER(sifive_reset), ++ &dev); ++ if (ret) { ++ dev_err(dev, "Reset driver not found: %d\n", ret); ++ return ret; ++ } ++ ++ ret = reset_get_by_name(dev, rst_name, &rst_sig); ++ if (ret) { ++ dev_err(dev, "failed to get %s reset\n", rst_name); ++ return ret; ++ } ++ ++ if (reset_valid(&rst_sig)) { ++ if (trigger) ++ ret = reset_deassert(&rst_sig); ++ else ++ ret = reset_assert(&rst_sig); ++ if (ret) { ++ dev_err(dev, "failed to trigger reset id = %ld\n", ++ rst_sig.id); ++ return ret; ++ } ++ } ++ ++ return ret; ++} ++ ++/** ++ * sifive_prci_ddr_release_reset() - Release DDR reset ++ * @pd: struct __prci_data * for the PRCI containing the DDRCLK mux reg ++ * ++ */ ++void sifive_prci_ddr_release_reset(struct __prci_data *pd) ++{ ++ /* Release DDR ctrl reset */ ++ __prci_consumer_reset("ddr_ctrl", true); ++ ++ /* HACK to get the '1 full controller clock cycle'. */ ++ asm volatile ("fence"); ++ ++ /* Release DDR AXI reset */ ++ __prci_consumer_reset("ddr_axi", true); ++ ++ /* Release DDR AHB reset */ ++ __prci_consumer_reset("ddr_ahb", true); ++ ++ /* Release DDR PHY reset */ ++ __prci_consumer_reset("ddr_phy", true); ++ ++ /* HACK to get the '1 full controller clock cycle'. */ ++ asm volatile ("fence"); ++ ++ /* ++ * These take like 16 cycles to actually propagate. We can't go sending ++ * stuff before they come out of reset. So wait. ++ */ ++ for (int i = 0; i < 256; i++) ++ asm volatile ("nop"); ++} ++ ++/** ++ * sifive_prci_ethernet_release_reset() - Release ethernet reset ++ * @pd: struct __prci_data * for the PRCI containing the Ethernet CLK mux reg ++ * ++ */ ++void sifive_prci_ethernet_release_reset(struct __prci_data *pd) ++{ ++ /* Release GEMGXL reset */ ++ __prci_consumer_reset("gemgxl_reset", true); ++ ++ /* Procmon => core clock */ ++ __prci_writel(PRCI_PROCMONCFG_CORE_CLOCK_MASK, PRCI_PROCMONCFG_OFFSET, ++ pd); ++} ++ ++/* Core clock mux control */ ++ ++/** ++ * sifive_prci_coreclksel_use_hfclk() - switch the CORECLK mux to output HFCLK ++ * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg ++ * ++ * Switch the CORECLK mux to the HFCLK input source; return once complete. ++ * ++ * Context: Any context. Caller must prevent concurrent changes to the ++ * PRCI_CORECLKSEL_OFFSET register. ++ */ ++void sifive_prci_coreclksel_use_hfclk(struct __prci_data *pd) ++{ ++ u32 r; ++ ++ r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); ++ r |= PRCI_CORECLKSEL_CORECLKSEL_MASK; ++ __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd); ++ ++ r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */ ++} ++ ++/** ++ * sifive_prci_coreclksel_use_corepll() - switch the CORECLK mux to output COREPLL ++ * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg ++ * ++ * Switch the CORECLK mux to the PLL output clock; return once complete. ++ * ++ * Context: Any context. Caller must prevent concurrent changes to the ++ * PRCI_CORECLKSEL_OFFSET register. ++ */ ++void sifive_prci_coreclksel_use_corepll(struct __prci_data *pd) ++{ ++ u32 r; ++ ++ r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); ++ r &= ~PRCI_CORECLKSEL_CORECLKSEL_MASK; ++ __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd); ++ ++ r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */ ++} ++ ++static ulong sifive_prci_parent_rate(struct __prci_clock *pc, struct prci_clk_desc *data) ++{ ++ ulong parent_rate; ++ struct __prci_clock *p; ++ ++ if (strcmp(pc->parent_name, "corepll") == 0) { ++ p = &data->clks[PRCI_CLK_COREPLL]; ++ if (!p->pd || !p->ops->recalc_rate) ++ return -ENXIO; ++ ++ return p->ops->recalc_rate(p, sifive_prci_parent_rate(p, data)); ++ } ++ ++ if (strcmp(pc->parent_name, "rtcclk") == 0) ++ parent_rate = clk_get_rate(&pc->pd->parent_rtcclk); ++ else ++ parent_rate = clk_get_rate(&pc->pd->parent_hfclk); ++ ++ return parent_rate; ++} ++ ++static ulong sifive_prci_get_rate(struct clk *clk) ++{ ++ struct __prci_clock *pc; ++ struct prci_clk_desc *data = ++ (struct prci_clk_desc *)dev_get_driver_data(clk->dev); ++ ++ if (data->num_clks <= clk->id) ++ return -ENXIO; ++ ++ pc = &data->clks[clk->id]; ++ if (!pc->pd || !pc->ops->recalc_rate) ++ return -ENXIO; ++ ++ return pc->ops->recalc_rate(pc, sifive_prci_parent_rate(pc, data)); ++} ++ ++static ulong sifive_prci_set_rate(struct clk *clk, ulong rate) ++{ ++ int err; ++ struct __prci_clock *pc; ++ struct prci_clk_desc *data = ++ (struct prci_clk_desc *)dev_get_driver_data(clk->dev); ++ ++ if (data->num_clks <= clk->id) ++ return -ENXIO; ++ ++ pc = &data->clks[clk->id]; ++ if (!pc->pd || !pc->ops->set_rate) ++ return -ENXIO; ++ ++ err = pc->ops->set_rate(pc, rate, sifive_prci_parent_rate(pc, data)); ++ if (err) ++ return err; ++ ++ return rate; ++} ++ ++static int sifive_prci_enable(struct clk *clk) ++{ ++ struct __prci_clock *pc; ++ int ret = 0; ++ struct prci_clk_desc *data = ++ (struct prci_clk_desc *)dev_get_driver_data(clk->dev); ++ ++ if (data->num_clks <= clk->id) ++ return -ENXIO; ++ ++ pc = &data->clks[clk->id]; ++ if (!pc->pd) ++ return -ENXIO; ++ ++ if (pc->ops->enable_clk) ++ ret = pc->ops->enable_clk(pc, 1); ++ ++ return ret; ++} ++ ++static int sifive_prci_disable(struct clk *clk) ++{ ++ struct __prci_clock *pc; ++ int ret = 0; ++ struct prci_clk_desc *data = ++ (struct prci_clk_desc *)dev_get_driver_data(clk->dev); ++ ++ if (data->num_clks <= clk->id) ++ return -ENXIO; ++ ++ pc = &data->clks[clk->id]; ++ if (!pc->pd) ++ return -ENXIO; ++ ++ if (pc->ops->enable_clk) ++ ret = pc->ops->enable_clk(pc, 0); ++ ++ return ret; ++} ++ ++static int sifive_prci_probe(struct udevice *dev) ++{ ++ int i, err; ++ struct __prci_clock *pc; ++ struct __prci_data *pd = dev_get_priv(dev); ++ ++ struct prci_clk_desc *data = ++ (struct prci_clk_desc *)dev_get_driver_data(dev); ++ ++ pd->va = (void *)dev_read_addr(dev); ++ if (IS_ERR(pd->va)) ++ return PTR_ERR(pd->va); ++ ++ err = clk_get_by_index(dev, 0, &pd->parent_hfclk); ++ if (err) ++ return err; ++ ++ err = clk_get_by_index(dev, 1, &pd->parent_rtcclk); ++ if (err) ++ return err; ++ ++ for (i = 0; i < data->num_clks; ++i) { ++ pc = &data->clks[i]; ++ pc->pd = pd; ++ if (pc->pwd) ++ __prci_wrpll_read_cfg0(pd, pc->pwd); ++ } ++ ++ return 0; ++} ++ ++static struct clk_ops sifive_prci_ops = { ++ .set_rate = sifive_prci_set_rate, ++ .get_rate = sifive_prci_get_rate, ++ .enable = sifive_prci_enable, ++ .disable = sifive_prci_disable, ++}; ++ ++static int sifive_clk_bind(struct udevice *dev) ++{ ++ return sifive_reset_bind(dev, PRCI_DEVICERESETCNT); ++} ++ ++static const struct udevice_id sifive_prci_ids[] = { ++ { .compatible = "sifive,fu540-c000-prci", .data = (ulong)&prci_clk_fu540 }, ++ { } ++}; ++ ++U_BOOT_DRIVER(sifive_prci) = { ++ .name = "sifive-prci", ++ .id = UCLASS_CLK, ++ .of_match = sifive_prci_ids, ++ .probe = sifive_prci_probe, ++ .ops = &sifive_prci_ops, ++ .priv_auto_alloc_size = sizeof(struct __prci_data), ++ .bind = sifive_clk_bind, ++}; +diff --git a/drivers/clk/sifive/sifive-prci.h b/drivers/clk/sifive/sifive-prci.h +new file mode 100644 +index 0000000..7ea77aa +--- /dev/null ++++ b/drivers/clk/sifive/sifive-prci.h +@@ -0,0 +1,224 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Copyright (C) 2020 SiFive, Inc. ++ * Wesley Terpstra ++ * Paul Walmsley ++ * Zong Li ++ * Pragnesh Patel ++ */ ++ ++#ifndef __SIFIVE_CLK_SIFIVE_PRCI_H ++#define __SIFIVE_CLK_SIFIVE_PRCI_H ++ ++#include ++#include ++ ++/* ++ * EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects: ++ * hfclk and rtcclk ++ */ ++#define EXPECTED_CLK_PARENT_COUNT 2 ++ ++/* ++ * Register offsets and bitmasks ++ */ ++ ++/* COREPLLCFG0 */ ++#define PRCI_COREPLLCFG0_OFFSET 0x4 ++#define PRCI_COREPLLCFG0_DIVR_SHIFT 0 ++#define PRCI_COREPLLCFG0_DIVR_MASK (0x3f << PRCI_COREPLLCFG0_DIVR_SHIFT) ++#define PRCI_COREPLLCFG0_DIVF_SHIFT 6 ++#define PRCI_COREPLLCFG0_DIVF_MASK (0x1ff << PRCI_COREPLLCFG0_DIVF_SHIFT) ++#define PRCI_COREPLLCFG0_DIVQ_SHIFT 15 ++#define PRCI_COREPLLCFG0_DIVQ_MASK (0x7 << PRCI_COREPLLCFG0_DIVQ_SHIFT) ++#define PRCI_COREPLLCFG0_RANGE_SHIFT 18 ++#define PRCI_COREPLLCFG0_RANGE_MASK (0x7 << PRCI_COREPLLCFG0_RANGE_SHIFT) ++#define PRCI_COREPLLCFG0_BYPASS_SHIFT 24 ++#define PRCI_COREPLLCFG0_BYPASS_MASK (0x1 << PRCI_COREPLLCFG0_BYPASS_SHIFT) ++#define PRCI_COREPLLCFG0_FSE_SHIFT 25 ++#define PRCI_COREPLLCFG0_FSE_MASK (0x1 << PRCI_COREPLLCFG0_FSE_SHIFT) ++#define PRCI_COREPLLCFG0_LOCK_SHIFT 31 ++#define PRCI_COREPLLCFG0_LOCK_MASK (0x1 << PRCI_COREPLLCFG0_LOCK_SHIFT) ++ ++/* COREPLLCFG1 */ ++#define PRCI_COREPLLCFG1_OFFSET 0x8 ++#define PRCI_COREPLLCFG1_CKE_SHIFT 31 ++#define PRCI_COREPLLCFG1_CKE_MASK (0x1 << PRCI_COREPLLCFG1_CKE_SHIFT) ++ ++/* DDRPLLCFG0 */ ++#define PRCI_DDRPLLCFG0_OFFSET 0xc ++#define PRCI_DDRPLLCFG0_DIVR_SHIFT 0 ++#define PRCI_DDRPLLCFG0_DIVR_MASK (0x3f << PRCI_DDRPLLCFG0_DIVR_SHIFT) ++#define PRCI_DDRPLLCFG0_DIVF_SHIFT 6 ++#define PRCI_DDRPLLCFG0_DIVF_MASK (0x1ff << PRCI_DDRPLLCFG0_DIVF_SHIFT) ++#define PRCI_DDRPLLCFG0_DIVQ_SHIFT 15 ++#define PRCI_DDRPLLCFG0_DIVQ_MASK (0x7 << PRCI_DDRPLLCFG0_DIVQ_SHIFT) ++#define PRCI_DDRPLLCFG0_RANGE_SHIFT 18 ++#define PRCI_DDRPLLCFG0_RANGE_MASK (0x7 << PRCI_DDRPLLCFG0_RANGE_SHIFT) ++#define PRCI_DDRPLLCFG0_BYPASS_SHIFT 24 ++#define PRCI_DDRPLLCFG0_BYPASS_MASK (0x1 << PRCI_DDRPLLCFG0_BYPASS_SHIFT) ++#define PRCI_DDRPLLCFG0_FSE_SHIFT 25 ++#define PRCI_DDRPLLCFG0_FSE_MASK (0x1 << PRCI_DDRPLLCFG0_FSE_SHIFT) ++#define PRCI_DDRPLLCFG0_LOCK_SHIFT 31 ++#define PRCI_DDRPLLCFG0_LOCK_MASK (0x1 << PRCI_DDRPLLCFG0_LOCK_SHIFT) ++ ++/* DDRPLLCFG1 */ ++#define PRCI_DDRPLLCFG1_OFFSET 0x10 ++#define PRCI_DDRPLLCFG1_CKE_SHIFT 31 ++#define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT) ++ ++/* GEMGXLPLLCFG0 */ ++#define PRCI_GEMGXLPLLCFG0_OFFSET 0x1c ++#define PRCI_GEMGXLPLLCFG0_DIVR_SHIFT 0 ++#define PRCI_GEMGXLPLLCFG0_DIVR_MASK \ ++ (0x3f << PRCI_GEMGXLPLLCFG0_DIVR_SHIFT) ++#define PRCI_GEMGXLPLLCFG0_DIVF_SHIFT 6 ++#define PRCI_GEMGXLPLLCFG0_DIVF_MASK \ ++ (0x1ff << PRCI_GEMGXLPLLCFG0_DIVF_SHIFT) ++#define PRCI_GEMGXLPLLCFG0_DIVQ_SHIFT 15 ++#define PRCI_GEMGXLPLLCFG0_DIVQ_MASK (0x7 << PRCI_GEMGXLPLLCFG0_DIVQ_SHIFT) ++#define PRCI_GEMGXLPLLCFG0_RANGE_SHIFT 18 ++#define PRCI_GEMGXLPLLCFG0_RANGE_MASK \ ++ (0x7 << PRCI_GEMGXLPLLCFG0_RANGE_SHIFT) ++#define PRCI_GEMGXLPLLCFG0_BYPASS_SHIFT 24 ++#define PRCI_GEMGXLPLLCFG0_BYPASS_MASK \ ++ (0x1 << PRCI_GEMGXLPLLCFG0_BYPASS_SHIFT) ++#define PRCI_GEMGXLPLLCFG0_FSE_SHIFT 25 ++#define PRCI_GEMGXLPLLCFG0_FSE_MASK \ ++ (0x1 << PRCI_GEMGXLPLLCFG0_FSE_SHIFT) ++#define PRCI_GEMGXLPLLCFG0_LOCK_SHIFT 31 ++#define PRCI_GEMGXLPLLCFG0_LOCK_MASK (0x1 << PRCI_GEMGXLPLLCFG0_LOCK_SHIFT) ++ ++/* GEMGXLPLLCFG1 */ ++#define PRCI_GEMGXLPLLCFG1_OFFSET 0x20 ++#define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 31 ++#define PRCI_GEMGXLPLLCFG1_CKE_MASK (0x1 << PRCI_GEMGXLPLLCFG1_CKE_SHIFT) ++ ++/* CORECLKSEL */ ++#define PRCI_CORECLKSEL_OFFSET 0x24 ++#define PRCI_CORECLKSEL_CORECLKSEL_SHIFT 0 ++#define PRCI_CORECLKSEL_CORECLKSEL_MASK \ ++ (0x1 << PRCI_CORECLKSEL_CORECLKSEL_SHIFT) ++ ++/* DEVICESRESETREG */ ++#define PRCI_DEVICESRESETREG_OFFSET 0x28 ++#define PRCI_DEVICERESETCNT 5 ++ ++/* CLKMUXSTATUSREG */ ++#define PRCI_CLKMUXSTATUSREG_OFFSET 0x2c ++#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT 1 ++#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK \ ++ (0x1 << PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT) ++ ++/* PROCMONCFG */ ++#define PRCI_PROCMONCFG_OFFSET 0xF0 ++#define PRCI_PROCMONCFG_CORE_CLOCK_SHIFT 24 ++#define PRCI_PROCMONCFG_CORE_CLOCK_MASK \ ++ (0x1 << PRCI_PROCMONCFG_CORE_CLOCK_SHIFT) ++ ++/* ++ * Private structures ++ */ ++ ++/** ++ * struct __prci_data - per-device-instance data ++ * @va: base virtual address of the PRCI IP block ++ * @parent: parent clk instance ++ * ++ * PRCI per-device instance data ++ */ ++struct __prci_data { ++ void *va; ++ struct clk parent_hfclk; ++ struct clk parent_rtcclk; ++}; ++ ++/** ++ * struct __prci_wrpll_data - WRPLL configuration and integration data ++ * @c: WRPLL current configuration record ++ * @enable_bypass: fn ptr to code to bypass the WRPLL (if applicable; else NULL) ++ * @disable_bypass: fn ptr to code to not bypass the WRPLL (or NULL) ++ * @cfg0_offs: WRPLL CFG0 register offset (in bytes) from the PRCI base address ++ * @cfg1_offs: WRPLL CFG1 register offset (in bytes) from the PRCI base address ++ * @release_reset: fn ptr to code to release clock reset ++ * ++ * @enable_bypass and @disable_bypass are used for WRPLL instances ++ * that contain a separate external glitchless clock mux downstream ++ * from the PLL. The WRPLL internal bypass mux is not glitchless. ++ */ ++struct __prci_wrpll_data { ++ struct wrpll_cfg c; ++ void (*enable_bypass)(struct __prci_data *pd); ++ void (*disable_bypass)(struct __prci_data *pd); ++ u8 cfg0_offs; ++ u8 cfg1_offs; ++ void (*release_reset)(struct __prci_data *pd); ++}; ++ ++/** ++ * struct __prci_clock - describes a clock device managed by PRCI ++ * @name: user-readable clock name string - should match the manual ++ * @parent_name: parent name for this clock ++ * @ops: struct __prci_clock_ops for control ++ * @pwd: WRPLL-specific data, associated with this clock (if not NULL) ++ * @pd: PRCI-specific data associated with this clock (if not NULL) ++ * ++ * PRCI clock data. Used by the PRCI driver to register PRCI-provided ++ * clocks to the Linux clock infrastructure. ++ */ ++struct __prci_clock { ++ const char *name; ++ const char *parent_name; ++ const struct __prci_clock_ops *ops; ++ struct __prci_wrpll_data *pwd; ++ struct __prci_data *pd; ++}; ++ ++/* struct __prci_clock_ops - clock operations */ ++struct __prci_clock_ops { ++ int (*set_rate)(struct __prci_clock *pc, ++ unsigned long rate, ++ unsigned long parent_rate); ++ unsigned long (*round_rate)(struct __prci_clock *pc, ++ unsigned long rate, ++ unsigned long *parent_rate); ++ unsigned long (*recalc_rate)(struct __prci_clock *pc, ++ unsigned long parent_rate); ++ int (*enable_clk)(struct __prci_clock *pc, bool enable); ++}; ++ ++/* ++ * struct prci_clk_desc - describes the information of clocks of each SoCs ++ * @clks: point to a array of __prci_clock ++ * @num_clks: the number of element of clks ++ */ ++struct prci_clk_desc { ++ struct __prci_clock *clks; ++ size_t num_clks; ++}; ++ ++void sifive_prci_ethernet_release_reset(struct __prci_data *pd); ++void sifive_prci_ddr_release_reset(struct __prci_data *pd); ++ ++/* Core clock mux control */ ++void sifive_prci_coreclksel_use_hfclk(struct __prci_data *pd); ++void sifive_prci_coreclksel_use_corepll(struct __prci_data *pd); ++ ++unsigned long sifive_prci_wrpll_round_rate(struct __prci_clock *pc, ++ unsigned long rate, ++ unsigned long *parent_rate); ++ ++/* Linux clock framework integration */ ++int sifive_prci_wrpll_set_rate(struct __prci_clock *pc, ++ unsigned long rate, ++ unsigned long parent_rate); ++ ++unsigned long sifive_prci_wrpll_recalc_rate(struct __prci_clock *pc, ++ unsigned long parent_rate); ++ ++unsigned long sifive_prci_tlclksel_recalc_rate(struct __prci_clock *pc, ++ unsigned long parent_rate); ++ ++int sifive_prci_clock_enable(struct __prci_clock *pc, bool enable); ++ ++#endif /* __SIFIVE_CLK_SIFIVE_PRCI_H */ +-- +2.7.4 + diff -Nru u-boot-2021.01+dfsg/debian/patches/riscv64/0002-clk-sifive-fu540-prci-Use-common-name-for-prci-confi.patch u-boot-2021.01+dfsg/debian/patches/riscv64/0002-clk-sifive-fu540-prci-Use-common-name-for-prci-confi.patch --- u-boot-2021.01+dfsg/debian/patches/riscv64/0002-clk-sifive-fu540-prci-Use-common-name-for-prci-confi.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/riscv64/0002-clk-sifive-fu540-prci-Use-common-name-for-prci-confi.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,75 @@ +From 0607085796bda51e0bf4fbeb8b1ff1c40a6e4f2a Mon Sep 17 00:00:00 2001 +From: Pragnesh Patel +Date: Wed, 26 Aug 2020 16:54:10 +0530 +Subject: [PATCH 02/41] clk: sifive: fu540-prci: Use common name for prci + configuration + +Use generic name CLK_SIFIVE_PRCI instead of CLK_SIFIVE_FU540_PRCI. This +patch is prepared for fu740 support. + +Signed-off-by: Pragnesh Patel +--- + arch/riscv/cpu/fu540/Kconfig | 2 +- + drivers/clk/sifive/Kconfig | 6 +++--- + drivers/clk/sifive/Makefile | 2 +- + drivers/reset/Kconfig | 2 +- + 4 files changed, 6 insertions(+), 6 deletions(-) + +diff --git a/arch/riscv/cpu/fu540/Kconfig b/arch/riscv/cpu/fu540/Kconfig +index 61bd5c4..ecdc7f4 100644 +--- a/arch/riscv/cpu/fu540/Kconfig ++++ b/arch/riscv/cpu/fu540/Kconfig +@@ -18,7 +18,7 @@ config SIFIVE_FU540 + imply SPL_LOAD_FIT + imply SMP + imply CLK_SIFIVE +- imply CLK_SIFIVE_FU540_PRCI ++ imply CLK_SIFIVE_PRCI + imply SIFIVE_SERIAL + imply MACB + imply MII +diff --git a/drivers/clk/sifive/Kconfig b/drivers/clk/sifive/Kconfig +index c4d0a1f..2836904 100644 +--- a/drivers/clk/sifive/Kconfig ++++ b/drivers/clk/sifive/Kconfig +@@ -6,11 +6,11 @@ config CLK_SIFIVE + help + SoC drivers for SiFive Linux-capable SoCs. + +-config CLK_SIFIVE_FU540_PRCI +- bool "PRCI driver for SiFive FU540 SoCs" ++config CLK_SIFIVE_PRCI ++ bool "PRCI driver for SiFive SoCs" + depends on CLK_SIFIVE + select CLK_ANALOGBITS_WRPLL_CLN28HPC + help + Supports the Power Reset Clock interface (PRCI) IP block found in +- FU540 SoCs. If this kernel is meant to run on a SiFive FU540 SoC, ++ FU540 SoCs. If this kernel is meant to run on a SiFive FU540 SoC, + enable this driver. +diff --git a/drivers/clk/sifive/Makefile b/drivers/clk/sifive/Makefile +index ea03494..c4cee5b 100644 +--- a/drivers/clk/sifive/Makefile ++++ b/drivers/clk/sifive/Makefile +@@ -2,4 +2,4 @@ + + obj-y += sifive-prci.o + +-obj-$(CONFIG_CLK_SIFIVE_FU540_PRCI) += fu540-prci.o ++obj-$(CONFIG_CLK_SIFIVE_PRCI) += fu540-prci.o +diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig +index 33c2736..8b40e9e 100644 +--- a/drivers/reset/Kconfig ++++ b/drivers/reset/Kconfig +@@ -157,7 +157,7 @@ config RESET_IPQ419 + + config RESET_SIFIVE + bool "Reset Driver for SiFive SoC's" +- depends on DM_RESET && CLK_SIFIVE_FU540_PRCI && TARGET_SIFIVE_FU540 ++ depends on DM_RESET && CLK_SIFIVE_PRCI && TARGET_SIFIVE_FU540 + default y + help + PRCI module within SiFive SoC's provides mechanism to reset +-- +2.7.4 + diff -Nru u-boot-2021.01+dfsg/debian/patches/riscv64/0003-clk-sifive-fu740-Sync-up-DT-bindings-header-with-ups.patch u-boot-2021.01+dfsg/debian/patches/riscv64/0003-clk-sifive-fu740-Sync-up-DT-bindings-header-with-ups.patch --- u-boot-2021.01+dfsg/debian/patches/riscv64/0003-clk-sifive-fu740-Sync-up-DT-bindings-header-with-ups.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/riscv64/0003-clk-sifive-fu740-Sync-up-DT-bindings-header-with-ups.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,47 @@ +From f79b7968f72385487b0246e3cdaa269cf830985d Mon Sep 17 00:00:00 2001 +From: Pragnesh Patel +Date: Tue, 24 Nov 2020 20:02:50 +0530 +Subject: [PATCH 03/41] clk: sifive: fu740: Sync-up DT bindings header with + upstream Linux + +Sync the SiFive FU740-C000 SoC DT bindings header from Linux + +Signed-off-by: Pragnesh Patel +--- + include/dt-bindings/clock/sifive-fu740-prci.h | 24 ++++++++++++++++++++++++ + 1 file changed, 24 insertions(+) + create mode 100644 include/dt-bindings/clock/sifive-fu740-prci.h + +diff --git a/include/dt-bindings/clock/sifive-fu740-prci.h b/include/dt-bindings/clock/sifive-fu740-prci.h +new file mode 100644 +index 0000000..6ee4c6d +--- /dev/null ++++ b/include/dt-bindings/clock/sifive-fu740-prci.h +@@ -0,0 +1,24 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Copyright (C) 2018-2019 SiFive, Inc. ++ * Wesley Terpstra ++ * Paul Walmsley ++ * Zong Li ++ * Pragnesh Patel ++ */ ++ ++#ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H ++#define __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H ++ ++/* Clock indexes for use by Device Tree data and the PRCI driver */ ++ ++#define PRCI_CLK_COREPLL 0 ++#define PRCI_CLK_DDRPLL 1 ++#define PRCI_CLK_GEMGXLPLL 2 ++#define PRCI_CLK_DVFSCOREPLL 3 ++#define PRCI_CLK_HFPCLKPLL 4 ++#define PRCI_CLK_CLTXPLL 5 ++#define PRCI_CLK_TLCLK 6 ++#define PRCI_CLK_PCLK 7 ++ ++#endif +-- +2.7.4 + diff -Nru u-boot-2021.01+dfsg/debian/patches/riscv64/0004-clk-sifive-fu740-prci-Add-a-driver-for-the-SiFive-FU.patch u-boot-2021.01+dfsg/debian/patches/riscv64/0004-clk-sifive-fu740-prci-Add-a-driver-for-the-SiFive-FU.patch --- u-boot-2021.01+dfsg/debian/patches/riscv64/0004-clk-sifive-fu740-prci-Add-a-driver-for-the-SiFive-FU.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/riscv64/0004-clk-sifive-fu740-prci-Add-a-driver-for-the-SiFive-FU.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,536 @@ +From ffee242fab5ddaad3e27eb6728de88bf107f45f2 Mon Sep 17 00:00:00 2001 +From: Pragnesh Patel +Date: Wed, 26 Aug 2020 20:24:27 +0530 +Subject: [PATCH 04/41] clk: sifive: fu740-prci: Add a driver for the SiFive + FU740 PRCI IP block + +Add driver code for the SiFive FU740 PRCI IP block. This IP block +handles reset and clock control for the SiFive FU740 device and +implements SoC-level clock tree controls and dividers. + +Signed-off-by: Pragnesh Patel +--- + drivers/clk/sifive/Kconfig | 4 +- + drivers/clk/sifive/Makefile | 2 +- + drivers/clk/sifive/fu740-prci.c | 127 +++++++++++++++++++++++++++++++++ + drivers/clk/sifive/fu740-prci.h | 22 ++++++ + drivers/clk/sifive/sifive-prci.c | 148 ++++++++++++++++++++++++++++++++++++++- + drivers/clk/sifive/sifive-prci.h | 96 ++++++++++++++++++++++++- + 6 files changed, 392 insertions(+), 7 deletions(-) + create mode 100644 drivers/clk/sifive/fu740-prci.c + create mode 100644 drivers/clk/sifive/fu740-prci.h + +diff --git a/drivers/clk/sifive/Kconfig b/drivers/clk/sifive/Kconfig +index 2836904..20fc004 100644 +--- a/drivers/clk/sifive/Kconfig ++++ b/drivers/clk/sifive/Kconfig +@@ -12,5 +12,5 @@ config CLK_SIFIVE_PRCI + select CLK_ANALOGBITS_WRPLL_CLN28HPC + help + Supports the Power Reset Clock interface (PRCI) IP block found in +- FU540 SoCs. If this kernel is meant to run on a SiFive FU540 SoC, +- enable this driver. ++ FU540/FU740 SoCs. If this kernel is meant to run on a SiFive FU540/ ++ FU740 SoCs, enable this driver. +diff --git a/drivers/clk/sifive/Makefile b/drivers/clk/sifive/Makefile +index c4cee5b..51348b1 100644 +--- a/drivers/clk/sifive/Makefile ++++ b/drivers/clk/sifive/Makefile +@@ -2,4 +2,4 @@ + + obj-y += sifive-prci.o + +-obj-$(CONFIG_CLK_SIFIVE_PRCI) += fu540-prci.o ++obj-$(CONFIG_CLK_SIFIVE_PRCI) += fu540-prci.o fu740-prci.o +diff --git a/drivers/clk/sifive/fu740-prci.c b/drivers/clk/sifive/fu740-prci.c +new file mode 100644 +index 0000000..218029b +--- /dev/null ++++ b/drivers/clk/sifive/fu740-prci.c +@@ -0,0 +1,127 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) 2018-2019 SiFive, Inc. ++ * Wesley Terpstra ++ * Paul Walmsley ++ * Zong Li ++ * Pragnesh Patel ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include "sifive-prci.h" ++ ++/* PRCI integration data for each WRPLL instance */ ++static struct __prci_wrpll_data __prci_corepll_data = { ++ .cfg0_offs = PRCI_COREPLLCFG0_OFFSET, ++ .cfg1_offs = PRCI_COREPLLCFG1_OFFSET, ++ .enable_bypass = sifive_prci_coreclksel_use_hfclk, ++ .disable_bypass = sifive_prci_coreclksel_use_final_corepll, ++}; ++ ++static struct __prci_wrpll_data __prci_ddrpll_data = { ++ .cfg0_offs = PRCI_DDRPLLCFG0_OFFSET, ++ .cfg1_offs = PRCI_DDRPLLCFG1_OFFSET, ++ .release_reset = sifive_prci_ddr_release_reset, ++}; ++ ++static struct __prci_wrpll_data __prci_gemgxlpll_data = { ++ .cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET, ++ .cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET, ++ .release_reset = sifive_prci_ethernet_release_reset, ++}; ++ ++static struct __prci_wrpll_data __prci_dvfscorepll_data = { ++ .cfg0_offs = PRCI_DVFSCOREPLLCFG0_OFFSET, ++ .cfg1_offs = PRCI_DVFSCOREPLLCFG1_OFFSET, ++ .enable_bypass = sifive_prci_corepllsel_use_corepll, ++ .disable_bypass = sifive_prci_corepllsel_use_dvfscorepll, ++}; ++ ++static struct __prci_wrpll_data __prci_hfpclkpll_data = { ++ .cfg0_offs = PRCI_HFPCLKPLLCFG0_OFFSET, ++ .cfg1_offs = PRCI_HFPCLKPLLCFG1_OFFSET, ++ .enable_bypass = sifive_prci_hfpclkpllsel_use_hfclk, ++ .disable_bypass = sifive_prci_hfpclkpllsel_use_hfpclkpll, ++}; ++ ++static struct __prci_wrpll_data __prci_cltxpll_data = { ++ .cfg0_offs = PRCI_CLTXPLLCFG0_OFFSET, ++ .cfg1_offs = PRCI_CLTXPLLCFG1_OFFSET, ++ .release_reset = sifive_prci_cltx_release_reset, ++}; ++ ++/* Linux clock framework integration */ ++ ++static const struct __prci_clock_ops sifive_fu740_prci_wrpll_clk_ops = { ++ .set_rate = sifive_prci_wrpll_set_rate, ++ .round_rate = sifive_prci_wrpll_round_rate, ++ .recalc_rate = sifive_prci_wrpll_recalc_rate, ++ .enable_clk = sifive_prci_clock_enable, ++}; ++ ++static const struct __prci_clock_ops sifive_fu740_prci_tlclksel_clk_ops = { ++ .recalc_rate = sifive_prci_tlclksel_recalc_rate, ++}; ++ ++static const struct __prci_clock_ops sifive_fu740_prci_hfpclkplldiv_clk_ops = { ++ .recalc_rate = sifive_prci_hfpclkplldiv_recalc_rate, ++}; ++ ++/* List of clock controls provided by the PRCI */ ++struct __prci_clock __prci_init_clocks_fu740[] = { ++ [PRCI_CLK_COREPLL] = { ++ .name = "corepll", ++ .parent_name = "hfclk", ++ .ops = &sifive_fu740_prci_wrpll_clk_ops, ++ .pwd = &__prci_corepll_data, ++ }, ++ [PRCI_CLK_DDRPLL] = { ++ .name = "ddrpll", ++ .parent_name = "hfclk", ++ .ops = &sifive_fu740_prci_wrpll_clk_ops, ++ .pwd = &__prci_ddrpll_data, ++ }, ++ [PRCI_CLK_GEMGXLPLL] = { ++ .name = "gemgxlpll", ++ .parent_name = "hfclk", ++ .ops = &sifive_fu740_prci_wrpll_clk_ops, ++ .pwd = &__prci_gemgxlpll_data, ++ }, ++ [PRCI_CLK_DVFSCOREPLL] = { ++ .name = "dvfscorepll", ++ .parent_name = "hfclk", ++ .ops = &sifive_fu740_prci_wrpll_clk_ops, ++ .pwd = &__prci_dvfscorepll_data, ++ }, ++ [PRCI_CLK_HFPCLKPLL] = { ++ .name = "hfpclkpll", ++ .parent_name = "hfclk", ++ .ops = &sifive_fu740_prci_wrpll_clk_ops, ++ .pwd = &__prci_hfpclkpll_data, ++ }, ++ [PRCI_CLK_CLTXPLL] = { ++ .name = "cltxpll", ++ .parent_name = "hfclk", ++ .ops = &sifive_fu740_prci_wrpll_clk_ops, ++ .pwd = &__prci_cltxpll_data, ++ }, ++ [PRCI_CLK_TLCLK] = { ++ .name = "tlclk", ++ .parent_name = "corepll", ++ .ops = &sifive_fu740_prci_tlclksel_clk_ops, ++ }, ++ [PRCI_CLK_PCLK] = { ++ .name = "pclk", ++ .parent_name = "hfpclkpll", ++ .ops = &sifive_fu740_prci_hfpclkplldiv_clk_ops, ++ }, ++}; +diff --git a/drivers/clk/sifive/fu740-prci.h b/drivers/clk/sifive/fu740-prci.h +new file mode 100644 +index 0000000..4db6b79 +--- /dev/null ++++ b/drivers/clk/sifive/fu740-prci.h +@@ -0,0 +1,22 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Copyright (C) 2020 SiFive, Inc. ++ * Zong Li ++ * Pragnesh Patel ++ */ ++ ++#ifndef __SIFIVE_CLK_FU740_PRCI_H ++#define __SIFIVE_CLK_FU740_PRCI_H ++ ++#include "sifive-prci.h" ++ ++#define NUM_CLOCK_FU740 8 ++ ++extern struct __prci_clock __prci_init_clocks_fu740[NUM_CLOCK_FU740]; ++ ++static const struct prci_clk_desc prci_clk_fu740 = { ++ .clks = __prci_init_clocks_fu740, ++ .num_clks = ARRAY_SIZE(__prci_init_clocks_fu740), ++}; ++ ++#endif /* __SIFIVE_CLK_FU740_PRCI_H */ +diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c +index b96491b..514bd36 100644 +--- a/drivers/clk/sifive/sifive-prci.c ++++ b/drivers/clk/sifive/sifive-prci.c +@@ -27,7 +27,6 @@ + #include + #include + #include +-#include + #include + #include + #include +@@ -35,6 +34,7 @@ + #include + + #include "fu540-prci.h" ++#include "fu740-prci.h" + + /* + * Private functions +@@ -276,6 +276,123 @@ unsigned long sifive_prci_tlclksel_recalc_rate(struct __prci_clock *pc, + return div_u64(parent_rate, div); + } + ++/* HFPCLK clock integration */ ++ ++unsigned long sifive_prci_hfpclkplldiv_recalc_rate(struct __prci_clock *pc, ++ unsigned long parent_rate) ++{ ++ struct __prci_data *pd = pc->pd; ++ u32 div = __prci_readl(pd, PRCI_HFPCLKPLLDIV_OFFSET); ++ ++ return div_u64(parent_rate, div + 2); ++} ++ ++/** ++ * sifive_prci_coreclksel_use_final_corepll() - switch the CORECLK mux to output ++ * FINAL_COREPLL ++ * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg ++ * ++ * Switch the CORECLK mux to the final COREPLL output clock; return once ++ * complete. ++ * ++ * Context: Any context. Caller must prevent concurrent changes to the ++ * PRCI_CORECLKSEL_OFFSET register. ++ */ ++void sifive_prci_coreclksel_use_final_corepll(struct __prci_data *pd) ++{ ++ u32 r; ++ ++ r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); ++ r &= ~PRCI_CORECLKSEL_CORECLKSEL_MASK; ++ __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd); ++ ++ r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */ ++} ++ ++/** ++ * sifive_prci_corepllsel_use_dvfscorepll() - switch the COREPLL mux to ++ * output DVFS_COREPLL ++ * @pd: struct __prci_data * for the PRCI containing the COREPLL mux reg ++ * ++ * Switch the COREPLL mux to the DVFSCOREPLL output clock; return once complete. ++ * ++ * Context: Any context. Caller must prevent concurrent changes to the ++ * PRCI_COREPLLSEL_OFFSET register. ++ */ ++void sifive_prci_corepllsel_use_dvfscorepll(struct __prci_data *pd) ++{ ++ u32 r; ++ ++ r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET); ++ r |= PRCI_COREPLLSEL_COREPLLSEL_MASK; ++ __prci_writel(r, PRCI_COREPLLSEL_OFFSET, pd); ++ ++ r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET); /* barrier */ ++} ++ ++/** ++ * sifive_prci_corepllsel_use_corepll() - switch the COREPLL mux to ++ * output COREPLL ++ * @pd: struct __prci_data * for the PRCI containing the COREPLL mux reg ++ * ++ * Switch the COREPLL mux to the COREPLL output clock; return once complete. ++ * ++ * Context: Any context. Caller must prevent concurrent changes to the ++ * PRCI_COREPLLSEL_OFFSET register. ++ */ ++void sifive_prci_corepllsel_use_corepll(struct __prci_data *pd) ++{ ++ u32 r; ++ ++ r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET); ++ r &= ~PRCI_COREPLLSEL_COREPLLSEL_MASK; ++ __prci_writel(r, PRCI_COREPLLSEL_OFFSET, pd); ++ ++ r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET); /* barrier */ ++} ++ ++/** ++ * sifive_prci_hfpclkpllsel_use_hfclk() - switch the HFPCLKPLL mux to ++ * output HFCLK ++ * @pd: struct __prci_data * for the PRCI containing the HFPCLKPLL mux reg ++ * ++ * Switch the HFPCLKPLL mux to the HFCLK input source; return once complete. ++ * ++ * Context: Any context. Caller must prevent concurrent changes to the ++ * PRCI_HFPCLKPLLSEL_OFFSET register. ++ */ ++void sifive_prci_hfpclkpllsel_use_hfclk(struct __prci_data *pd) ++{ ++ u32 r; ++ ++ r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET); ++ r |= PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_MASK; ++ __prci_writel(r, PRCI_HFPCLKPLLSEL_OFFSET, pd); ++ ++ r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET); /* barrier */ ++} ++ ++/** ++ * sifive_prci_hfpclkpllsel_use_hfpclkpll() - switch the HFPCLKPLL mux to ++ * output HFPCLKPLL ++ * @pd: struct __prci_data * for the PRCI containing the HFPCLKPLL mux reg ++ * ++ * Switch the HFPCLKPLL mux to the HFPCLKPLL output clock; return once complete. ++ * ++ * Context: Any context. Caller must prevent concurrent changes to the ++ * PRCI_HFPCLKPLLSEL_OFFSET register. ++ */ ++void sifive_prci_hfpclkpllsel_use_hfpclkpll(struct __prci_data *pd) ++{ ++ u32 r; ++ ++ r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET); ++ r &= ~PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_MASK; ++ __prci_writel(r, PRCI_HFPCLKPLLSEL_OFFSET, pd); ++ ++ r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET); /* barrier */ ++} ++ + static int __prci_consumer_reset(const char *rst_name, bool trigger) + { + struct udevice *dev; +@@ -357,6 +474,20 @@ void sifive_prci_ethernet_release_reset(struct __prci_data *pd) + /* Procmon => core clock */ + __prci_writel(PRCI_PROCMONCFG_CORE_CLOCK_MASK, PRCI_PROCMONCFG_OFFSET, + pd); ++ ++ /* Release Chiplink reset */ ++ __prci_consumer_reset("cltx_reset", true); ++} ++ ++/** ++ * sifive_prci_cltx_release_reset() - Release cltx reset ++ * @pd: struct __prci_data * for the PRCI containing the Ethernet CLK mux reg ++ * ++ */ ++void sifive_prci_cltx_release_reset(struct __prci_data *pd) ++{ ++ /* Release CLTX reset */ ++ __prci_consumer_reset("cltx_reset", true); + } + + /* Core clock mux control */ +@@ -404,10 +535,20 @@ void sifive_prci_coreclksel_use_corepll(struct __prci_data *pd) + static ulong sifive_prci_parent_rate(struct __prci_clock *pc, struct prci_clk_desc *data) + { + ulong parent_rate; ++ ulong i; + struct __prci_clock *p; + +- if (strcmp(pc->parent_name, "corepll") == 0) { +- p = &data->clks[PRCI_CLK_COREPLL]; ++ if (strcmp(pc->parent_name, "corepll") == 0 || ++ strcmp(pc->parent_name, "hfpclkpll") == 0) { ++ for (i = 0; i < data->num_clks; i++) { ++ if (strcmp(pc->parent_name, data->clks[i].name) == 0) ++ break; ++ } ++ ++ if (i >= data->num_clks) ++ return -ENXIO; ++ ++ p = &data->clks[i]; + if (!p->pd || !p->ops->recalc_rate) + return -ENXIO; + +@@ -544,6 +685,7 @@ static int sifive_clk_bind(struct udevice *dev) + + static const struct udevice_id sifive_prci_ids[] = { + { .compatible = "sifive,fu540-c000-prci", .data = (ulong)&prci_clk_fu540 }, ++ { .compatible = "sifive,fu740-c000-prci", .data = (ulong)&prci_clk_fu740 }, + { } + }; + +diff --git a/drivers/clk/sifive/sifive-prci.h b/drivers/clk/sifive/sifive-prci.h +index 7ea77aa..af81ff8 100644 +--- a/drivers/clk/sifive/sifive-prci.h ++++ b/drivers/clk/sifive/sifive-prci.h +@@ -102,7 +102,7 @@ + + /* DEVICESRESETREG */ + #define PRCI_DEVICESRESETREG_OFFSET 0x28 +-#define PRCI_DEVICERESETCNT 5 ++#define PRCI_DEVICERESETCNT 6 + + /* CLKMUXSTATUSREG */ + #define PRCI_CLKMUXSTATUSREG_OFFSET 0x2c +@@ -110,6 +110,91 @@ + #define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK \ + (0x1 << PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT) + ++/* CLTXPLLCFG0 */ ++#define PRCI_CLTXPLLCFG0_OFFSET 0x30 ++#define PRCI_CLTXPLLCFG0_DIVR_SHIFT 0 ++#define PRCI_CLTXPLLCFG0_DIVR_MASK (0x3f << PRCI_CLTXPLLCFG0_DIVR_SHIFT) ++#define PRCI_CLTXPLLCFG0_DIVF_SHIFT 6 ++#define PRCI_CLTXPLLCFG0_DIVF_MASK (0x1ff << PRCI_CLTXPLLCFG0_DIVF_SHIFT) ++#define PRCI_CLTXPLLCFG0_DIVQ_SHIFT 15 ++#define PRCI_CLTXPLLCFG0_DIVQ_MASK (0x7 << PRCI_CLTXPLLCFG0_DIVQ_SHIFT) ++#define PRCI_CLTXPLLCFG0_RANGE_SHIFT 18 ++#define PRCI_CLTXPLLCFG0_RANGE_MASK (0x7 << PRCI_CLTXPLLCFG0_RANGE_SHIFT) ++#define PRCI_CLTXPLLCFG0_BYPASS_SHIFT 24 ++#define PRCI_CLTXPLLCFG0_BYPASS_MASK (0x1 << PRCI_CLTXPLLCFG0_BYPASS_SHIFT) ++#define PRCI_CLTXPLLCFG0_FSE_SHIFT 25 ++#define PRCI_CLTXPLLCFG0_FSE_MASK (0x1 << PRCI_CLTXPLLCFG0_FSE_SHIFT) ++#define PRCI_CLTXPLLCFG0_LOCK_SHIFT 31 ++#define PRCI_CLTXPLLCFG0_LOCK_MASK (0x1 << PRCI_CLTXPLLCFG0_LOCK_SHIFT) ++ ++/* CLTXPLLCFG1 */ ++#define PRCI_CLTXPLLCFG1_OFFSET 0x34 ++#define PRCI_CLTXPLLCFG1_CKE_SHIFT 24 ++#define PRCI_CLTXPLLCFG1_CKE_MASK (0x1 << PRCI_CLTXPLLCFG1_CKE_SHIFT) ++ ++/* DVFSCOREPLLCFG0 */ ++#define PRCI_DVFSCOREPLLCFG0_OFFSET 0x38 ++ ++/* DVFSCOREPLLCFG1 */ ++#define PRCI_DVFSCOREPLLCFG1_OFFSET 0x3c ++#define PRCI_DVFSCOREPLLCFG1_CKE_SHIFT 24 ++#define PRCI_DVFSCOREPLLCFG1_CKE_MASK (0x1 << PRCI_DVFSCOREPLLCFG1_CKE_SHIFT) ++ ++/* COREPLLSEL */ ++#define PRCI_COREPLLSEL_OFFSET 0x40 ++#define PRCI_COREPLLSEL_COREPLLSEL_SHIFT 0 ++#define PRCI_COREPLLSEL_COREPLLSEL_MASK \ ++ (0x1 << PRCI_COREPLLSEL_COREPLLSEL_SHIFT) ++ ++/* HFPCLKPLLCFG0 */ ++#define PRCI_HFPCLKPLLCFG0_OFFSET 0x50 ++#define PRCI_HFPCLKPLL_CFG0_DIVR_SHIFT 0 ++#define PRCI_HFPCLKPLL_CFG0_DIVR_MASK \ ++ (0x3f << PRCI_HFPCLKPLLCFG0_DIVR_SHIFT) ++#define PRCI_HFPCLKPLL_CFG0_DIVF_SHIFT 6 ++#define PRCI_HFPCLKPLL_CFG0_DIVF_MASK \ ++ (0x1ff << PRCI_HFPCLKPLLCFG0_DIVF_SHIFT) ++#define PRCI_HFPCLKPLL_CFG0_DIVQ_SHIFT 15 ++#define PRCI_HFPCLKPLL_CFG0_DIVQ_MASK \ ++ (0x7 << PRCI_HFPCLKPLLCFG0_DIVQ_SHIFT) ++#define PRCI_HFPCLKPLL_CFG0_RANGE_SHIFT 18 ++#define PRCI_HFPCLKPLL_CFG0_RANGE_MASK \ ++ (0x7 << PRCI_HFPCLKPLLCFG0_RANGE_SHIFT) ++#define PRCI_HFPCLKPLL_CFG0_BYPASS_SHIFT 24 ++#define PRCI_HFPCLKPLL_CFG0_BYPASS_MASK \ ++ (0x1 << PRCI_HFPCLKPLLCFG0_BYPASS_SHIFT) ++#define PRCI_HFPCLKPLL_CFG0_FSE_SHIFT 25 ++#define PRCI_HFPCLKPLL_CFG0_FSE_MASK \ ++ (0x1 << PRCI_HFPCLKPLLCFG0_FSE_SHIFT) ++#define PRCI_HFPCLKPLL_CFG0_LOCK_SHIFT 31 ++#define PRCI_HFPCLKPLL_CFG0_LOCK_MASK \ ++ (0x1 << PRCI_HFPCLKPLLCFG0_LOCK_SHIFT) ++ ++/* HFPCLKPLLCFG1 */ ++#define PRCI_HFPCLKPLLCFG1_OFFSET 0x54 ++#define PRCI_HFPCLKPLLCFG1_CKE_SHIFT 24 ++#define PRCI_HFPCLKPLLCFG1_CKE_MASK \ ++ (0x1 << PRCI_HFPCLKPLLCFG1_CKE_SHIFT) ++ ++/* HFPCLKPLLSEL */ ++#define PRCI_HFPCLKPLLSEL_OFFSET 0x58 ++#define PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_SHIFT 0 ++#define PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_MASK \ ++ (0x1 << PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_SHIFT) ++ ++/* HFPCLKPLLDIV */ ++#define PRCI_HFPCLKPLLDIV_OFFSET 0x5c ++ ++/* PRCIPLL */ ++#define PRCI_PRCIPLL_OFFSET 0xe0 ++ ++#define PRCI_PRCIPLL_CLTXPLL (0x1 << 0) ++#define PRCI_PRCIPLL_GEMGXLPLL (0x1 << 1) ++#define PRCI_PRCIPLL_DDRPLL (0x1 << 2) ++#define PRCI_PRCIPLL_HFPCLKPLL (0x1 << 3) ++#define PRCI_PRCIPLL_DVFSCOREPLL (0x1 << 4) ++#define PRCI_PRCIPLL_COREPLL (0x1 << 5) ++ + /* PROCMONCFG */ + #define PRCI_PROCMONCFG_OFFSET 0xF0 + #define PRCI_PROCMONCFG_CORE_CLOCK_SHIFT 24 +@@ -199,10 +284,16 @@ struct prci_clk_desc { + + void sifive_prci_ethernet_release_reset(struct __prci_data *pd); + void sifive_prci_ddr_release_reset(struct __prci_data *pd); ++void sifive_prci_cltx_release_reset(struct __prci_data *pd); + + /* Core clock mux control */ + void sifive_prci_coreclksel_use_hfclk(struct __prci_data *pd); + void sifive_prci_coreclksel_use_corepll(struct __prci_data *pd); ++void sifive_prci_coreclksel_use_final_corepll(struct __prci_data *pd); ++void sifive_prci_corepllsel_use_dvfscorepll(struct __prci_data *pd); ++void sifive_prci_corepllsel_use_corepll(struct __prci_data *pd); ++void sifive_prci_hfpclkpllsel_use_hfclk(struct __prci_data *pd); ++void sifive_prci_hfpclkpllsel_use_hfpclkpll(struct __prci_data *pd); + + unsigned long sifive_prci_wrpll_round_rate(struct __prci_clock *pc, + unsigned long rate, +@@ -219,6 +310,9 @@ unsigned long sifive_prci_wrpll_recalc_rate(struct __prci_clock *pc, + unsigned long sifive_prci_tlclksel_recalc_rate(struct __prci_clock *pc, + unsigned long parent_rate); + ++unsigned long sifive_prci_hfpclkplldiv_recalc_rate(struct __prci_clock *pc, ++ unsigned long parent_rate); ++ + int sifive_prci_clock_enable(struct __prci_clock *pc, bool enable); + + #endif /* __SIFIVE_CLK_SIFIVE_PRCI_H */ +-- +2.7.4 + diff -Nru u-boot-2021.01+dfsg/debian/patches/riscv64/0005-clk-sifive-select-PLL-clock-as-input-source-after-en.patch u-boot-2021.01+dfsg/debian/patches/riscv64/0005-clk-sifive-select-PLL-clock-as-input-source-after-en.patch --- u-boot-2021.01+dfsg/debian/patches/riscv64/0005-clk-sifive-select-PLL-clock-as-input-source-after-en.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/riscv64/0005-clk-sifive-select-PLL-clock-as-input-source-after-en.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,49 @@ +From 84fd726a035283257844e3ec39e6d95309a00c50 Mon Sep 17 00:00:00 2001 +From: Pragnesh Patel +Date: Tue, 24 Nov 2020 18:36:54 +0530 +Subject: [PATCH 05/41] clk: sifive: select PLL clock as input source after + enabling PLL clock output + +PLL clock output needs to be enabled first and then any selection +register can use PLL clock as a input source. + +Signed-off-by: Pragnesh Patel +--- + drivers/clk/sifive/sifive-prci.c | 9 ++++++--- + 1 file changed, 6 insertions(+), 3 deletions(-) + +diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c +index 514bd36..2fc426e 100644 +--- a/drivers/clk/sifive/sifive-prci.c ++++ b/drivers/clk/sifive/sifive-prci.c +@@ -232,9 +232,6 @@ int sifive_prci_wrpll_set_rate(struct __prci_clock *pc, + + udelay(wrpll_calc_max_lock_us(&pwd->c)); + +- if (pwd->disable_bypass) +- pwd->disable_bypass(pd); +- + return 0; + } + +@@ -246,11 +243,17 @@ int sifive_prci_clock_enable(struct __prci_clock *pc, bool enable) + if (enable) { + __prci_wrpll_write_cfg1(pd, pwd, PRCI_COREPLLCFG1_CKE_MASK); + ++ if (pwd->disable_bypass) ++ pwd->disable_bypass(pd); ++ + if (pwd->release_reset) + pwd->release_reset(pd); + } else { + u32 r; + ++ if (pwd->enable_bypass) ++ pwd->enable_bypass(pd); ++ + r = __prci_readl(pd, pwd->cfg1_offs); + r &= ~PRCI_COREPLLCFG1_CKE_MASK; + +-- +2.7.4 + diff -Nru u-boot-2021.01+dfsg/debian/patches/riscv64/0006-clk-sifive-fu740-prci-set-HFPCLKPLL-rate-to-260-Mhz.patch u-boot-2021.01+dfsg/debian/patches/riscv64/0006-clk-sifive-fu740-prci-set-HFPCLKPLL-rate-to-260-Mhz.patch --- u-boot-2021.01+dfsg/debian/patches/riscv64/0006-clk-sifive-fu740-prci-set-HFPCLKPLL-rate-to-260-Mhz.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/riscv64/0006-clk-sifive-fu740-prci-set-HFPCLKPLL-rate-to-260-Mhz.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,61 @@ +From 9edcb33fe4b9faba329165e5642b0f216f745577 Mon Sep 17 00:00:00 2001 +From: Pragnesh Patel +Date: Tue, 24 Nov 2020 19:06:44 +0530 +Subject: [PATCH 06/41] clk: sifive: fu740-prci: set HFPCLKPLL rate to 260 Mhz + +HFPCLKPLL is a intermediate clock PLL so no peripheral driver is able +to set the rate of HFPCLKPLL, so setting the same in probe function. + +Signed-off-by: Pragnesh Patel +--- + drivers/clk/sifive/sifive-prci.c | 27 +++++++++++++++++++++++++++ + 1 file changed, 27 insertions(+) + +diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c +index 2fc426e..5858004 100644 +--- a/drivers/clk/sifive/sifive-prci.c ++++ b/drivers/clk/sifive/sifive-prci.c +@@ -32,6 +32,7 @@ + #include + #include + #include ++#include + + #include "fu540-prci.h" + #include "fu740-prci.h" +@@ -671,6 +672,32 @@ static int sifive_prci_probe(struct udevice *dev) + __prci_wrpll_read_cfg0(pd, pc->pwd); + } + ++#if IS_ENABLED(CONFIG_SPL_BUILD) ++ if (device_is_compatible(dev, "sifive,fu740-c000-prci")) { ++ u32 prci_pll_reg; ++ unsigned long parent_rate; ++ ++ prci_pll_reg = readl(pd->va + PRCI_PRCIPLL_OFFSET); ++ ++ if (prci_pll_reg & PRCI_PRCIPLL_HFPCLKPLL) { ++ /* ++ * Only initialize the HFPCLK PLL. In this case the design uses hfpclk to ++ * drive Chiplink ++ */ ++ pc = &data->clks[PRCI_CLK_HFPCLKPLL]; ++ parent_rate = sifive_prci_parent_rate(pc, data); ++ sifive_prci_wrpll_set_rate(pc, 260000000, parent_rate); ++ pc->ops->enable_clk(pc, 1); ++ } else if (prci_pll_reg & PRCI_PRCIPLL_CLTXPLL) { ++ /* CLTX pll init */ ++ pc = &data->clks[PRCI_CLK_CLTXPLL]; ++ parent_rate = sifive_prci_parent_rate(pc, data); ++ sifive_prci_wrpll_set_rate(pc, 260000000, parent_rate); ++ pc->ops->enable_clk(pc, 1); ++ } ++ } ++#endif ++ + return 0; + } + +-- +2.7.4 + diff -Nru u-boot-2021.01+dfsg/debian/patches/riscv64/0007-riscv-dts-Add-SiFive-FU740-C000-SoC-dts-from-Linux.patch u-boot-2021.01+dfsg/debian/patches/riscv64/0007-riscv-dts-Add-SiFive-FU740-C000-SoC-dts-from-Linux.patch --- u-boot-2021.01+dfsg/debian/patches/riscv64/0007-riscv-dts-Add-SiFive-FU740-C000-SoC-dts-from-Linux.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/riscv64/0007-riscv-dts-Add-SiFive-FU740-C000-SoC-dts-from-Linux.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,320 @@ +From c9f9042a2ffff252f5a80836b8f2f3acd6d0ffa5 Mon Sep 17 00:00:00 2001 +From: Pragnesh Patel +Date: Mon, 17 Feb 2020 16:45:07 +0530 +Subject: [PATCH 07/41] riscv: dts: Add SiFive FU740-C000 SoC dts from Linux + +Sync the SiFive FU740-C000 SoC dts from Linux + +Idea is to periodically sync the dts from Linux instead of +tweaking internal changes one after another, so better not +add any intermediate changes in between. This would help to +maintain the dts files easy and meaningful since we are +reusing device tree files from Linux. + +Signed-off-by: Pragnesh Patel +--- + arch/riscv/dts/fu740-c000.dtsi | 292 +++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 292 insertions(+) + create mode 100644 arch/riscv/dts/fu740-c000.dtsi + +diff --git a/arch/riscv/dts/fu740-c000.dtsi b/arch/riscv/dts/fu740-c000.dtsi +new file mode 100644 +index 0000000..ee0ab3f +--- /dev/null ++++ b/arch/riscv/dts/fu740-c000.dtsi +@@ -0,0 +1,292 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* Copyright (c) 2019 SiFive, Inc */ ++ ++/dts-v1/; ++ ++#include ++ ++/ { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ compatible = "sifive,fu740-c000", "sifive,fu740"; ++ ++ aliases { ++ serial0 = &uart0; ++ serial1 = &uart1; ++ ethernet0 = ð0; ++ }; ++ ++ chosen { ++ }; ++ ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ cpu0: cpu@0 { ++ compatible = "sifive,bullet0", "riscv"; ++ device_type = "cpu"; ++ i-cache-block-size = <64>; ++ i-cache-sets = <128>; ++ i-cache-size = <16384>; ++ next-level-cache = <&ccache>; ++ reg = <0x0>; ++ riscv,isa = "rv64imac"; ++ status = "disabled"; ++ cpu0_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu1: cpu@1 { ++ compatible = "sifive,bullet0", "riscv"; ++ d-cache-block-size = <64>; ++ d-cache-sets = <64>; ++ d-cache-size = <32768>; ++ d-tlb-sets = <1>; ++ d-tlb-size = <40>; ++ device_type = "cpu"; ++ i-cache-block-size = <64>; ++ i-cache-sets = <128>; ++ i-cache-size = <32768>; ++ i-tlb-sets = <1>; ++ i-tlb-size = <40>; ++ mmu-type = "riscv,sv39"; ++ next-level-cache = <&ccache>; ++ reg = <0x1>; ++ riscv,isa = "rv64imafdc"; ++ tlb-split; ++ cpu1_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu2: cpu@2 { ++ compatible = "sifive,bullet0", "riscv"; ++ d-cache-block-size = <64>; ++ d-cache-sets = <64>; ++ d-cache-size = <32768>; ++ d-tlb-sets = <1>; ++ d-tlb-size = <40>; ++ device_type = "cpu"; ++ i-cache-block-size = <64>; ++ i-cache-sets = <128>; ++ i-cache-size = <32768>; ++ i-tlb-sets = <1>; ++ i-tlb-size = <40>; ++ mmu-type = "riscv,sv39"; ++ next-level-cache = <&ccache>; ++ reg = <0x2>; ++ riscv,isa = "rv64imafdc"; ++ tlb-split; ++ cpu2_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu3: cpu@3 { ++ compatible = "sifive,bullet0", "riscv"; ++ d-cache-block-size = <64>; ++ d-cache-sets = <64>; ++ d-cache-size = <32768>; ++ d-tlb-sets = <1>; ++ d-tlb-size = <40>; ++ device_type = "cpu"; ++ i-cache-block-size = <64>; ++ i-cache-sets = <128>; ++ i-cache-size = <32768>; ++ i-tlb-sets = <1>; ++ i-tlb-size = <40>; ++ mmu-type = "riscv,sv39"; ++ next-level-cache = <&ccache>; ++ reg = <0x3>; ++ riscv,isa = "rv64imafdc"; ++ tlb-split; ++ cpu3_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu4: cpu@4 { ++ compatible = "sifive,bullet0", "riscv"; ++ d-cache-block-size = <64>; ++ d-cache-sets = <64>; ++ d-cache-size = <32768>; ++ d-tlb-sets = <1>; ++ d-tlb-size = <40>; ++ device_type = "cpu"; ++ i-cache-block-size = <64>; ++ i-cache-sets = <128>; ++ i-cache-size = <32768>; ++ i-tlb-sets = <1>; ++ i-tlb-size = <40>; ++ mmu-type = "riscv,sv39"; ++ next-level-cache = <&ccache>; ++ reg = <0x4>; ++ riscv,isa = "rv64imafdc"; ++ tlb-split; ++ cpu4_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ }; ++ soc { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ compatible = "sifive,fu740-c000", "sifive,fu740", "simple-bus"; ++ ranges; ++ plic0: interrupt-controller@c000000 { ++ #interrupt-cells = <1>; ++ compatible = "sifive,plic-1.0.0"; ++ reg = <0x0 0xc000000 0x0 0x4000000>; ++ riscv,ndev = <69>; ++ interrupt-controller; ++ interrupts-extended = < ++ &cpu0_intc 0xffffffff ++ &cpu1_intc 0xffffffff &cpu1_intc 9 ++ &cpu2_intc 0xffffffff &cpu2_intc 9 ++ &cpu3_intc 0xffffffff &cpu3_intc 9 ++ &cpu4_intc 0xffffffff &cpu4_intc 9>; ++ }; ++ prci: clock-controller@10000000 { ++ compatible = "sifive,fu740-c000-prci"; ++ reg = <0x0 0x10000000 0x0 0x1000>; ++ clocks = <&hfclk>, <&rtcclk>; ++ #clock-cells = <1>; ++ }; ++ uart0: serial@10010000 { ++ compatible = "sifive,fu740-c000-uart", "sifive,uart0"; ++ reg = <0x0 0x10010000 0x0 0x1000>; ++ interrupt-parent = <&plic0>; ++ interrupts = <39>; ++ clocks = <&prci PRCI_CLK_PCLK>; ++ status = "disabled"; ++ }; ++ uart1: serial@10011000 { ++ compatible = "sifive,fu740-c000-uart", "sifive,uart0"; ++ reg = <0x0 0x10011000 0x0 0x1000>; ++ interrupt-parent = <&plic0>; ++ interrupts = <40>; ++ clocks = <&prci PRCI_CLK_PCLK>; ++ status = "disabled"; ++ }; ++ i2c0: i2c@10030000 { ++ compatible = "sifive,fu740-c000-i2c", "sifive,i2c0"; ++ reg = <0x0 0x10030000 0x0 0x1000>; ++ interrupt-parent = <&plic0>; ++ interrupts = <52>; ++ clocks = <&prci PRCI_CLK_PCLK>; ++ reg-shift = <2>; ++ reg-io-width = <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ i2c1: i2c@10031000 { ++ compatible = "sifive,fu740-c000-i2c", "sifive,i2c0"; ++ reg = <0x0 0x10031000 0x0 0x1000>; ++ interrupt-parent = <&plic0>; ++ interrupts = <53>; ++ clocks = <&prci PRCI_CLK_PCLK>; ++ reg-shift = <2>; ++ reg-io-width = <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ qspi0: spi@10040000 { ++ compatible = "sifive,fu740-c000-spi", "sifive,spi0"; ++ reg = <0x0 0x10040000 0x0 0x1000 ++ 0x0 0x20000000 0x0 0x10000000>; ++ interrupt-parent = <&plic0>; ++ interrupts = <41>; ++ clocks = <&prci PRCI_CLK_PCLK>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ qspi1: spi@10041000 { ++ compatible = "sifive,fu740-c000-spi", "sifive,spi0"; ++ reg = <0x0 0x10041000 0x0 0x1000 ++ 0x0 0x30000000 0x0 0x10000000>; ++ interrupt-parent = <&plic0>; ++ interrupts = <42>; ++ clocks = <&prci PRCI_CLK_PCLK>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ spi0: spi@10050000 { ++ compatible = "sifive,fu740-c000-spi", "sifive,spi0"; ++ reg = <0x0 0x10050000 0x0 0x1000>; ++ interrupt-parent = <&plic0>; ++ interrupts = <43>; ++ clocks = <&prci PRCI_CLK_PCLK>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ eth0: ethernet@10090000 { ++ compatible = "sifive,fu540-c000-gem"; ++ interrupt-parent = <&plic0>; ++ interrupts = <55>; ++ reg = <0x0 0x10090000 0x0 0x2000 ++ 0x0 0x100a0000 0x0 0x1000>; ++ local-mac-address = [00 00 00 00 00 00]; ++ clock-names = "pclk", "hclk"; ++ clocks = <&prci PRCI_CLK_GEMGXLPLL>, ++ <&prci PRCI_CLK_GEMGXLPLL>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ pwm0: pwm@10020000 { ++ compatible = "sifive,fu740-c000-pwm", "sifive,pwm0"; ++ reg = <0x0 0x10020000 0x0 0x1000>; ++ interrupt-parent = <&plic0>; ++ interrupts = <44 45 46 47>; ++ clocks = <&prci PRCI_CLK_PCLK>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ pwm1: pwm@10021000 { ++ compatible = "sifive,fu740-c000-pwm", "sifive,pwm0"; ++ reg = <0x0 0x10021000 0x0 0x1000>; ++ interrupt-parent = <&plic0>; ++ interrupts = <48 49 50 51>; ++ clocks = <&prci PRCI_CLK_PCLK>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ccache: cache-controller@2010000 { ++ compatible = "sifive,fu740-c000-ccache", "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-sets = <2048>; ++ cache-size = <2097152>; ++ cache-unified; ++ interrupt-parent = <&plic0>; ++ interrupts = <19 20 21 22>; ++ reg = <0x0 0x2010000 0x0 0x1000>; ++ }; ++ gpio: gpio@10060000 { ++ compatible = "sifive,fu740-c000-gpio", "sifive,gpio0"; ++ interrupt-parent = <&plic0>; ++ interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>, ++ <30>, <31>, <32>, <33>, <34>, <35>, <36>, ++ <37>, <38>; ++ reg = <0x0 0x10060000 0x0 0x1000>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ clocks = <&prci PRCI_CLK_PCLK>; ++ status = "disabled"; ++ }; ++ }; ++}; +-- +2.7.4 + diff -Nru u-boot-2021.01+dfsg/debian/patches/riscv64/0008-riscv-dts-Add-hifive-unmatched-a00-dts-from-Linux.patch u-boot-2021.01+dfsg/debian/patches/riscv64/0008-riscv-dts-Add-hifive-unmatched-a00-dts-from-Linux.patch --- u-boot-2021.01+dfsg/debian/patches/riscv64/0008-riscv-dts-Add-hifive-unmatched-a00-dts-from-Linux.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/riscv64/0008-riscv-dts-Add-hifive-unmatched-a00-dts-from-Linux.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,288 @@ +From 6ab49aff1cb45450bff9985cef8ee0e91244fbd0 Mon Sep 17 00:00:00 2001 +From: Pragnesh Patel +Date: Mon, 17 Feb 2020 18:25:38 +0530 +Subject: [PATCH 08/41] riscv: dts: Add hifive-unmatched-a00 dts from Linux + +Sync the hifive-unmatched-a00 dts from Linux + +Signed-off-by: Pragnesh Patel +--- + arch/riscv/dts/Makefile | 1 + + arch/riscv/dts/hifive-unmatched-a00.dts | 253 ++++++++++++++++++++++++++++++++ + 2 files changed, 254 insertions(+) + create mode 100644 arch/riscv/dts/hifive-unmatched-a00.dts + +diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile +index 3a6f96c..895382f 100644 +--- a/arch/riscv/dts/Makefile ++++ b/arch/riscv/dts/Makefile +@@ -2,6 +2,7 @@ + + dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb + dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb ++dtb-$(CONFIG_TARGET_SIFIVE_HIFIVE_UNMATCHED_FU740) += hifive-unmatched-a00.dtb + dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb + + targets += $(dtb-y) +diff --git a/arch/riscv/dts/hifive-unmatched-a00.dts b/arch/riscv/dts/hifive-unmatched-a00.dts +new file mode 100644 +index 0000000..6588512 +--- /dev/null ++++ b/arch/riscv/dts/hifive-unmatched-a00.dts +@@ -0,0 +1,253 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* Copyright (c) 2019 SiFive, Inc */ ++ ++#include "fu740-c000.dtsi" ++#include ++ ++/* Clock frequency (in Hz) of the PCB crystal for rtcclk */ ++#define RTCCLK_FREQ 1000000 ++ ++/ { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ model = "SiFive HiFive Unmatched A00"; ++ compatible = "sifive,hifive-unmatched-a00", "sifive,fu740-c000", ++ "sifive,fu740"; ++ ++ chosen { ++ stdout-path = "serial0"; ++ }; ++ ++ cpus { ++ timebase-frequency = ; ++ }; ++ ++ memory@80000000 { ++ device_type = "memory"; ++ reg = <0x0 0x80000000 0x2 0x00000000>; ++ }; ++ ++ soc { ++ }; ++ ++ hfclk: hfclk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <26000000>; ++ clock-output-names = "hfclk"; ++ }; ++ ++ rtcclk: rtcclk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = ; ++ clock-output-names = "rtcclk"; ++ }; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; ++ ++&uart1 { ++ status = "okay"; ++}; ++ ++&i2c0 { ++ status = "okay"; ++ ++ temperature-sensor@4c { ++ compatible = "ti,tmp451"; ++ reg = <0x4c>; ++ interrupt-parent = <&gpio>; ++ interrupts = <6 IRQ_TYPE_LEVEL_LOW>; ++ }; ++ ++ pmic@58 { ++ compatible = "dlg,da9063"; ++ reg = <0x58>; ++ interrupt-parent = <&gpio>; ++ interrupts = <1 IRQ_TYPE_LEVEL_LOW>; ++ interrupt-controller; ++ ++ regulators { ++ vdd_bcore1: bcore1 { ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ regulator-min-microamp = <5000000>; ++ regulator-max-microamp = <5000000>; ++ regulator-always-on; ++ }; ++ ++ vdd_bcore2: bcore2 { ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ regulator-min-microamp = <5000000>; ++ regulator-max-microamp = <5000000>; ++ regulator-always-on; ++ }; ++ ++ vdd_bpro: bpro { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-min-microamp = <2500000>; ++ regulator-max-microamp = <2500000>; ++ regulator-always-on; ++ }; ++ ++ vdd_bperi: bperi { ++ regulator-min-microvolt = <1050000>; ++ regulator-max-microvolt = <1050000>; ++ regulator-min-microamp = <1500000>; ++ regulator-max-microamp = <1500000>; ++ regulator-always-on; ++ }; ++ ++ vdd_bmem: bmem { ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-min-microamp = <3000000>; ++ regulator-max-microamp = <3000000>; ++ regulator-always-on; ++ }; ++ ++ vdd_bio: bio { ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-min-microamp = <3000000>; ++ regulator-max-microamp = <3000000>; ++ regulator-always-on; ++ }; ++ ++ vdd_ldo1: ldo1 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-min-microamp = <100000>; ++ regulator-max-microamp = <100000>; ++ regulator-always-on; ++ }; ++ ++ vdd_ldo2: ldo2 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-min-microamp = <200000>; ++ regulator-max-microamp = <200000>; ++ regulator-always-on; ++ }; ++ ++ vdd_ldo3: ldo3 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-min-microamp = <200000>; ++ regulator-max-microamp = <200000>; ++ regulator-always-on; ++ }; ++ ++ vdd_ldo4: ldo4 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-min-microamp = <200000>; ++ regulator-max-microamp = <200000>; ++ regulator-always-on; ++ }; ++ ++ vdd_ldo5: ldo5 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-min-microamp = <100000>; ++ regulator-max-microamp = <100000>; ++ regulator-always-on; ++ }; ++ ++ vdd_ldo6: ldo6 { ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-min-microamp = <200000>; ++ regulator-max-microamp = <200000>; ++ regulator-always-on; ++ }; ++ ++ vdd_ldo7: ldo7 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-min-microamp = <200000>; ++ regulator-max-microamp = <200000>; ++ regulator-always-on; ++ }; ++ ++ vdd_ldo8: ldo8 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-min-microamp = <200000>; ++ regulator-max-microamp = <200000>; ++ regulator-always-on; ++ }; ++ ++ vdd_ld09: ldo9 { ++ regulator-min-microvolt = <1050000>; ++ regulator-max-microvolt = <1050000>; ++ regulator-min-microamp = <200000>; ++ regulator-max-microamp = <200000>; ++ }; ++ ++ vdd_ldo10: ldo10 { ++ regulator-min-microvolt = <1000000>; ++ regulator-max-microvolt = <1000000>; ++ regulator-min-microamp = <300000>; ++ regulator-max-microamp = <300000>; ++ }; ++ ++ vdd_ldo11: ldo11 { ++ regulator-min-microvolt = <2500000>; ++ regulator-max-microvolt = <2500000>; ++ regulator-min-microamp = <300000>; ++ regulator-max-microamp = <300000>; ++ regulator-always-on; ++ }; ++ }; ++ }; ++}; ++ ++&qspi0 { ++ status = "okay"; ++ flash@0 { ++ compatible = "issi,is25wp256", "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <50000000>; ++ m25p,fast-read; ++ spi-tx-bus-width = <4>; ++ spi-rx-bus-width = <4>; ++ }; ++}; ++ ++&spi0 { ++ status = "okay"; ++ mmc@0 { ++ compatible = "mmc-spi-slot"; ++ reg = <0>; ++ spi-max-frequency = <20000000>; ++ voltage-ranges = <3300 3300>; ++ disable-wp; ++ }; ++}; ++ ++ð0 { ++ status = "okay"; ++ phy-mode = "gmii"; ++ phy-handle = <&phy0>; ++ phy0: ethernet-phy@0 { ++ reg = <0>; ++ }; ++}; ++ ++&pwm0 { ++ status = "okay"; ++}; ++ ++&pwm1 { ++ status = "okay"; ++}; ++ ++&gpio { ++ status = "okay"; ++}; +-- +2.7.4 + diff -Nru u-boot-2021.01+dfsg/debian/patches/riscv64/0009-riscv-cpu-fu740-Add-support-for-cpu-fu740.patch u-boot-2021.01+dfsg/debian/patches/riscv64/0009-riscv-cpu-fu740-Add-support-for-cpu-fu740.patch --- u-boot-2021.01+dfsg/debian/patches/riscv64/0009-riscv-cpu-fu740-Add-support-for-cpu-fu740.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/riscv64/0009-riscv-cpu-fu740-Add-support-for-cpu-fu740.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,252 @@ +From 502bdc0955f1f38ff93f3d9c1f2bb6c4cd771718 Mon Sep 17 00:00:00 2001 +From: Pragnesh Patel +Date: Mon, 19 Oct 2020 18:34:50 +0530 +Subject: [PATCH 09/41] riscv: cpu: fu740: Add support for cpu fu740 + +Add SiFive fu740 cpu to support RISC-V arch + +Signed-off-by: Pragnesh Patel +--- + arch/riscv/Kconfig | 1 + + arch/riscv/cpu/fu740/Kconfig | 37 ++++++++++++++++++++++++++++++ + arch/riscv/cpu/fu740/Makefile | 7 ++++++ + arch/riscv/cpu/fu740/cpu.c | 22 ++++++++++++++++++ + arch/riscv/cpu/fu740/dram.c | 38 +++++++++++++++++++++++++++++++ + arch/riscv/include/asm/arch-fu740/clk.h | 14 ++++++++++++ + arch/riscv/include/asm/arch-fu740/gpio.h | 38 +++++++++++++++++++++++++++++++ + arch/riscv/include/asm/arch-fu740/reset.h | 13 +++++++++++ + 8 files changed, 170 insertions(+) + create mode 100644 arch/riscv/cpu/fu740/Kconfig + create mode 100644 arch/riscv/cpu/fu740/Makefile + create mode 100644 arch/riscv/cpu/fu740/cpu.c + create mode 100644 arch/riscv/cpu/fu740/dram.c + create mode 100644 arch/riscv/include/asm/arch-fu740/clk.h + create mode 100644 arch/riscv/include/asm/arch-fu740/gpio.h + create mode 100644 arch/riscv/include/asm/arch-fu740/reset.h + +diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig +index 30b0540..00791d9 100644 +--- a/arch/riscv/Kconfig ++++ b/arch/riscv/Kconfig +@@ -61,6 +61,7 @@ source "board/sipeed/maix/Kconfig" + # platform-specific options below + source "arch/riscv/cpu/ax25/Kconfig" + source "arch/riscv/cpu/fu540/Kconfig" ++source "arch/riscv/cpu/fu740/Kconfig" + source "arch/riscv/cpu/generic/Kconfig" + + # architecture-specific options below +diff --git a/arch/riscv/cpu/fu740/Kconfig b/arch/riscv/cpu/fu740/Kconfig +new file mode 100644 +index 0000000..b62fba6 +--- /dev/null ++++ b/arch/riscv/cpu/fu740/Kconfig +@@ -0,0 +1,37 @@ ++# SPDX-License-Identifier: GPL-2.0+ ++# ++# Copyright (C) 2020 SiFive, Inc ++# Pragnesh Patel ++ ++config SIFIVE_FU740 ++ bool ++ select ARCH_EARLY_INIT_R ++ select RAM ++ select SPL_RAM if SPL ++ imply CPU ++ imply CPU_RISCV ++ imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) ++ imply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE) ++ imply CMD_CPU ++ imply SPL_CPU_SUPPORT ++ imply SPL_OPENSBI ++ imply SPL_LOAD_FIT ++ imply SMP ++ imply CLK_SIFIVE ++ imply CLK_SIFIVE_PRCI ++ imply SIFIVE_SERIAL ++ imply MACB ++ imply MII ++ imply SPI ++ imply SPI_SIFIVE ++ imply MMC ++ imply MMC_SPI ++ imply MMC_BROKEN_CD ++ imply CMD_MMC ++ imply DM_GPIO ++ imply SIFIVE_GPIO ++ imply CMD_GPIO ++ imply MISC ++ imply SIFIVE_OTP ++ imply DM_PWM ++ imply PWM_SIFIVE +diff --git a/arch/riscv/cpu/fu740/Makefile b/arch/riscv/cpu/fu740/Makefile +new file mode 100644 +index 0000000..44700d9 +--- /dev/null ++++ b/arch/riscv/cpu/fu740/Makefile +@@ -0,0 +1,7 @@ ++# SPDX-License-Identifier: GPL-2.0+ ++# ++# Copyright (C) 2020 SiFive, Inc ++# Pragnesh Patel ++ ++obj-y += dram.o ++obj-y += cpu.o +diff --git a/arch/riscv/cpu/fu740/cpu.c b/arch/riscv/cpu/fu740/cpu.c +new file mode 100644 +index 0000000..f13c189 +--- /dev/null ++++ b/arch/riscv/cpu/fu740/cpu.c +@@ -0,0 +1,22 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) 2018, Bin Meng ++ */ ++ ++#include ++#include ++ ++/* ++ * cleanup_before_linux() is called just before we call linux ++ * it prepares the processor for linux ++ * ++ * we disable interrupt and caches. ++ */ ++int cleanup_before_linux(void) ++{ ++ disable_interrupts(); ++ ++ cache_flush(); ++ ++ return 0; ++} +diff --git a/arch/riscv/cpu/fu740/dram.c b/arch/riscv/cpu/fu740/dram.c +new file mode 100644 +index 0000000..1dc77ef +--- /dev/null ++++ b/arch/riscv/cpu/fu740/dram.c +@@ -0,0 +1,38 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) 2018, Bin Meng ++ */ ++ ++#include ++#include ++#include ++#include ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++int dram_init(void) ++{ ++ return fdtdec_setup_mem_size_base(); ++} ++ ++int dram_init_banksize(void) ++{ ++ return fdtdec_setup_memory_banksize(); ++} ++ ++ulong board_get_usable_ram_top(ulong total_size) ++{ ++#ifdef CONFIG_64BIT ++ /* ++ * Ensure that we run from first 4GB so that all ++ * addresses used by U-Boot are 32bit addresses. ++ * ++ * This in-turn ensures that 32bit DMA capable ++ * devices work fine because DMA mapping APIs will ++ * provide 32bit DMA addresses only. ++ */ ++ if (gd->ram_top > SZ_4G) ++ return SZ_4G; ++#endif ++ return gd->ram_top; ++} +diff --git a/arch/riscv/include/asm/arch-fu740/clk.h b/arch/riscv/include/asm/arch-fu740/clk.h +new file mode 100644 +index 0000000..d71ed43 +--- /dev/null ++++ b/arch/riscv/include/asm/arch-fu740/clk.h +@@ -0,0 +1,14 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright (c) 2020 SiFive Inc ++ * ++ * Authors: ++ * Pragnesh Patel ++ */ ++ ++#ifndef __CLK_SIFIVE_H ++#define __CLK_SIFIVE_H ++ ++/* Note: This is a placeholder header for driver compilation. */ ++ ++#endif +diff --git a/arch/riscv/include/asm/arch-fu740/gpio.h b/arch/riscv/include/asm/arch-fu740/gpio.h +new file mode 100644 +index 0000000..9edc39c +--- /dev/null ++++ b/arch/riscv/include/asm/arch-fu740/gpio.h +@@ -0,0 +1,38 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright (C) 2020 SiFive, Inc. ++ */ ++ ++#ifndef _GPIO_SIFIVE_H ++#define _GPIO_SIFIVE_H ++ ++#define GPIO_INPUT_VAL 0x00 ++#define GPIO_INPUT_EN 0x04 ++#define GPIO_OUTPUT_EN 0x08 ++#define GPIO_OUTPUT_VAL 0x0C ++#define GPIO_RISE_IE 0x18 ++#define GPIO_RISE_IP 0x1C ++#define GPIO_FALL_IE 0x20 ++#define GPIO_FALL_IP 0x24 ++#define GPIO_HIGH_IE 0x28 ++#define GPIO_HIGH_IP 0x2C ++#define GPIO_LOW_IE 0x30 ++#define GPIO_LOW_IP 0x34 ++#define GPIO_OUTPUT_XOR 0x40 ++ ++#define NR_GPIOS 16 ++ ++enum gpio_state { ++ LOW, ++ HIGH ++}; ++ ++/* Details about a GPIO bank */ ++struct sifive_gpio_platdata { ++ void *base; /* address of registers in physical memory */ ++}; ++ ++#define SIFIVE_GENERIC_GPIO_NR(port, index) \ ++ (((port) * NR_GPIOS) + ((index) & (NR_GPIOS - 1))) ++ ++#endif /* _GPIO_SIFIVE_H */ +diff --git a/arch/riscv/include/asm/arch-fu740/reset.h b/arch/riscv/include/asm/arch-fu740/reset.h +new file mode 100644 +index 0000000..e42797a +--- /dev/null ++++ b/arch/riscv/include/asm/arch-fu740/reset.h +@@ -0,0 +1,13 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright (c) 2020 SiFive, Inc. ++ * ++ * Author: Sagar Kadam ++ */ ++ ++#ifndef __RESET_SIFIVE_H ++#define __RESET_SIFIVE_H ++ ++int sifive_reset_bind(struct udevice *dev, ulong count); ++ ++#endif +-- +2.7.4 + diff -Nru u-boot-2021.01+dfsg/debian/patches/riscv64/0010-riscv-Add-SiFive-HiFive-Unmatched-FU740-board-suppor.patch u-boot-2021.01+dfsg/debian/patches/riscv64/0010-riscv-Add-SiFive-HiFive-Unmatched-FU740-board-suppor.patch --- u-boot-2021.01+dfsg/debian/patches/riscv64/0010-riscv-Add-SiFive-HiFive-Unmatched-FU740-board-suppor.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/riscv64/0010-riscv-Add-SiFive-HiFive-Unmatched-FU740-board-suppor.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,229 @@ +From 84d7dffc522d9d72e09ff808df461409b2655771 Mon Sep 17 00:00:00 2001 +From: Pragnesh Patel +Date: Wed, 21 Oct 2020 12:37:16 +0530 +Subject: [PATCH 10/41] riscv: Add SiFive HiFive Unmatched FU740 board support + +This patch adds SiFive HiFive Unmatched FU740 board support. +The SiFive HiFive Unmatched FU740 defconfig by default builds +U-Boot for S-Mode. + +Signed-off-by: Pragnesh Patel +--- + arch/riscv/Kconfig | 4 ++ + board/sifive/hifive_unmatched_fu740/Kconfig | 39 ++++++++++++++++++ + board/sifive/hifive_unmatched_fu740/MAINTAINERS | 8 ++++ + board/sifive/hifive_unmatched_fu740/Makefile | 5 +++ + .../hifive-unmatched-fu740.c | 17 ++++++++ + configs/sifive_hifive_unmatched_fu740_defconfig | 12 ++++++ + drivers/reset/Kconfig | 2 +- + include/configs/sifive-hifive-unmatched-fu740.h | 47 ++++++++++++++++++++++ + 8 files changed, 133 insertions(+), 1 deletion(-) + create mode 100644 board/sifive/hifive_unmatched_fu740/Kconfig + create mode 100644 board/sifive/hifive_unmatched_fu740/MAINTAINERS + create mode 100644 board/sifive/hifive_unmatched_fu740/Makefile + create mode 100644 board/sifive/hifive_unmatched_fu740/hifive-unmatched-fu740.c + create mode 100644 configs/sifive_hifive_unmatched_fu740_defconfig + create mode 100644 include/configs/sifive-hifive-unmatched-fu740.h + +diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig +index 00791d9..e1c57ca 100644 +--- a/arch/riscv/Kconfig ++++ b/arch/riscv/Kconfig +@@ -20,6 +20,9 @@ config TARGET_QEMU_VIRT + config TARGET_SIFIVE_FU540 + bool "Support SiFive FU540 Board" + ++config TARGET_SIFIVE_HIFIVE_UNMATCHED_FU740 ++ bool "Support SiFive hifive-unmatched FU740 Board" ++ + config TARGET_SIPEED_MAIX + bool "Support Sipeed Maix Board" + +@@ -56,6 +59,7 @@ source "board/AndesTech/ax25-ae350/Kconfig" + source "board/emulation/qemu-riscv/Kconfig" + source "board/microchip/mpfs_icicle/Kconfig" + source "board/sifive/fu540/Kconfig" ++source "board/sifive/hifive_unmatched_fu740/Kconfig" + source "board/sipeed/maix/Kconfig" + + # platform-specific options below +diff --git a/board/sifive/hifive_unmatched_fu740/Kconfig b/board/sifive/hifive_unmatched_fu740/Kconfig +new file mode 100644 +index 0000000..3b9b0ae +--- /dev/null ++++ b/board/sifive/hifive_unmatched_fu740/Kconfig +@@ -0,0 +1,39 @@ ++if TARGET_SIFIVE_HIFIVE_UNMATCHED_FU740 ++ ++config SYS_BOARD ++ default "hifive_unmatched_fu740" ++ ++config SYS_VENDOR ++ default "sifive" ++ ++config SYS_CPU ++ default "fu740" ++ ++config SYS_CONFIG_NAME ++ default "sifive-hifive-unmatched-fu740" ++ ++config SYS_TEXT_BASE ++ default 0x80000000 if !RISCV_SMODE ++ default 0x80200000 if RISCV_SMODE ++ ++config BOARD_SPECIFIC_OPTIONS # dummy ++ def_bool y ++ select SIFIVE_FU740 ++ imply CMD_DHCP ++ imply CMD_EXT2 ++ imply CMD_EXT4 ++ imply CMD_FAT ++ imply CMD_FS_GENERIC ++ imply CMD_NET ++ imply CMD_PING ++ imply CMD_SF ++ imply DOS_PARTITION ++ imply EFI_PARTITION ++ imply IP_DYN ++ imply ISO_PARTITION ++ imply PHY_LIB ++ imply PHY_MSCC ++ imply SYSRESET ++ imply SYSRESET_GPIO ++ ++endif +diff --git a/board/sifive/hifive_unmatched_fu740/MAINTAINERS b/board/sifive/hifive_unmatched_fu740/MAINTAINERS +new file mode 100644 +index 0000000..2d3a89b +--- /dev/null ++++ b/board/sifive/hifive_unmatched_fu740/MAINTAINERS +@@ -0,0 +1,8 @@ ++SiFive HiFive Unmatched FU740 BOARD ++M: Paul Walmsley ++M: Pragnesh Patel ++S: Maintained ++F: board/sifive/hifive_unmatched_fu740/ ++F: doc/board/sifive/hifive-unmatched-fu740.rst ++F: include/configs/sifive-hifive-unmatched-fu740.h ++F: configs/sifive_hifive_unmatched_fu740_defconfig +diff --git a/board/sifive/hifive_unmatched_fu740/Makefile b/board/sifive/hifive_unmatched_fu740/Makefile +new file mode 100644 +index 0000000..8f65118 +--- /dev/null ++++ b/board/sifive/hifive_unmatched_fu740/Makefile +@@ -0,0 +1,5 @@ ++# SPDX-License-Identifier: GPL-2.0+ ++# ++# Copyright (c) 2020 SiFive, Inc ++ ++obj-y += hifive-unmatched-fu740.o +diff --git a/board/sifive/hifive_unmatched_fu740/hifive-unmatched-fu740.c b/board/sifive/hifive_unmatched_fu740/hifive-unmatched-fu740.c +new file mode 100644 +index 0000000..febfa51 +--- /dev/null ++++ b/board/sifive/hifive_unmatched_fu740/hifive-unmatched-fu740.c +@@ -0,0 +1,17 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (c) 2020, SiFive Inc ++ * ++ * Authors: ++ * Pragnesh Patel ++ */ ++ ++#include ++#include ++ ++int board_init(void) ++{ ++ /* For now nothing to do here. */ ++ ++ return 0; ++} +diff --git a/configs/sifive_hifive_unmatched_fu740_defconfig b/configs/sifive_hifive_unmatched_fu740_defconfig +new file mode 100644 +index 0000000..93ceeed +--- /dev/null ++++ b/configs/sifive_hifive_unmatched_fu740_defconfig +@@ -0,0 +1,12 @@ ++CONFIG_RISCV=y ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_DEFAULT_DEVICE_TREE="hifive-unmatched-a00" ++CONFIG_TARGET_SIFIVE_HIFIVE_UNMATCHED_FU740=y ++CONFIG_ARCH_RV64I=y ++CONFIG_RISCV_SMODE=y ++CONFIG_DISTRO_DEFAULTS=y ++CONFIG_FIT=y ++CONFIG_DISPLAY_CPUINFO=y ++CONFIG_DISPLAY_BOARDINFO=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_DM_RESET=y +diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig +index 8b40e9e..d51ccaa 100644 +--- a/drivers/reset/Kconfig ++++ b/drivers/reset/Kconfig +@@ -157,7 +157,7 @@ config RESET_IPQ419 + + config RESET_SIFIVE + bool "Reset Driver for SiFive SoC's" +- depends on DM_RESET && CLK_SIFIVE_PRCI && TARGET_SIFIVE_FU540 ++ depends on DM_RESET && CLK_SIFIVE_PRCI && (TARGET_SIFIVE_FU540 || TARGET_SIFIVE_HIFIVE_UNMATCHED_FU740) + default y + help + PRCI module within SiFive SoC's provides mechanism to reset +diff --git a/include/configs/sifive-hifive-unmatched-fu740.h b/include/configs/sifive-hifive-unmatched-fu740.h +new file mode 100644 +index 0000000..dc75d25 +--- /dev/null ++++ b/include/configs/sifive-hifive-unmatched-fu740.h +@@ -0,0 +1,47 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright (c) 2020 SiFive, Inc ++ * ++ * Authors: ++ * Pragnesh Patel ++ */ ++ ++#ifndef __SIFIVE_HIFIVE_UNMATCHED_FU740_H ++#define __SIFIVE_HIFIVE_UNMATCHED_FU740_H ++ ++#include ++ ++#define CONFIG_SYS_SDRAM_BASE 0x80000000 ++#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) ++ ++#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) ++ ++#define CONFIG_SYS_MALLOC_LEN SZ_8M ++ ++#define CONFIG_SYS_BOOTM_LEN SZ_64M ++ ++#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 ++ ++/* Environment options */ ++ ++#define BOOT_TARGET_DEVICES(func) \ ++ func(MMC, mmc, 0) \ ++ func(DHCP, dhcp, na) ++ ++#include ++ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ "fdt_high=0xffffffffffffffff\0" \ ++ "initrd_high=0xffffffffffffffff\0" \ ++ "kernel_addr_r=0x84000000\0" \ ++ "fdt_addr_r=0x88000000\0" \ ++ "scriptaddr=0x88100000\0" \ ++ "pxefile_addr_r=0x88200000\0" \ ++ "ramdisk_addr_r=0x88300000\0" \ ++ BOOTENV ++ ++#define CONFIG_PREBOOT \ ++ "setenv fdt_addr ${fdtcontroladdr};" \ ++ "fdt addr ${fdtcontroladdr};" ++ ++#endif /* __SIFIVE_HIFIVE_UNMATCHED_FU740_H */ +-- +2.7.4 + diff -Nru u-boot-2021.01+dfsg/debian/patches/riscv64/0011-riscv-sifive-dts-fu740-Add-board-u-boot.dtsi-files.patch u-boot-2021.01+dfsg/debian/patches/riscv64/0011-riscv-sifive-dts-fu740-Add-board-u-boot.dtsi-files.patch --- u-boot-2021.01+dfsg/debian/patches/riscv64/0011-riscv-sifive-dts-fu740-Add-board-u-boot.dtsi-files.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/riscv64/0011-riscv-sifive-dts-fu740-Add-board-u-boot.dtsi-files.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,150 @@ +From 61eb18411e58541899b98f922f1e56402e6166f7 Mon Sep 17 00:00:00 2001 +From: Pragnesh Patel +Date: Mon, 19 Oct 2020 18:03:37 +0530 +Subject: [PATCH 11/41] riscv: sifive: dts: fu740: Add board -u-boot.dtsi files + +Devicetree files in FU740 platform is synced from Linux, like other +platforms does. Apart from these U-Boot in FU740 would also require +some U-Boot specific node like clint. + +So, create board specific -u-boot.dtsi files. This would help of +maintain U-Boot specific changes separately without touching Linux +dts(i) files which indeed easy for syncing from Linux between +releases. + +Signed-off-by: Pragnesh Patel +--- + arch/riscv/dts/fu740-c000-u-boot.dtsi | 74 +++++++++++++++++++++++++ + arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi | 39 +++++++++++++ + 2 files changed, 113 insertions(+) + create mode 100644 arch/riscv/dts/fu740-c000-u-boot.dtsi + create mode 100644 arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi + +diff --git a/arch/riscv/dts/fu740-c000-u-boot.dtsi b/arch/riscv/dts/fu740-c000-u-boot.dtsi +new file mode 100644 +index 0000000..c7df15b +--- /dev/null ++++ b/arch/riscv/dts/fu740-c000-u-boot.dtsi +@@ -0,0 +1,74 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * (C) Copyright 2020 SiFive, Inc ++ */ ++ ++/ { ++ cpus { ++ assigned-clocks = <&prci PRCI_CLK_COREPLL>; ++ assigned-clock-rates = <1001000000>; ++ u-boot,dm-spl; ++ cpu0: cpu@0 { ++ clocks = <&prci PRCI_CLK_COREPLL>; ++ u-boot,dm-spl; ++ status = "okay"; ++ cpu0_intc: interrupt-controller { ++ u-boot,dm-spl; ++ }; ++ }; ++ cpu1: cpu@1 { ++ clocks = <&prci PRCI_CLK_COREPLL>; ++ u-boot,dm-spl; ++ cpu1_intc: interrupt-controller { ++ u-boot,dm-spl; ++ }; ++ }; ++ cpu2: cpu@2 { ++ clocks = <&prci PRCI_CLK_COREPLL>; ++ u-boot,dm-spl; ++ cpu2_intc: interrupt-controller { ++ u-boot,dm-spl; ++ }; ++ }; ++ cpu3: cpu@3 { ++ clocks = <&prci PRCI_CLK_COREPLL>; ++ u-boot,dm-spl; ++ cpu3_intc: interrupt-controller { ++ u-boot,dm-spl; ++ }; ++ }; ++ cpu4: cpu@4 { ++ clocks = <&prci PRCI_CLK_COREPLL>; ++ u-boot,dm-spl; ++ cpu4_intc: interrupt-controller { ++ u-boot,dm-spl; ++ }; ++ }; ++ }; ++ ++ soc { ++ u-boot,dm-spl; ++ clint: clint@2000000 { ++ compatible = "riscv,clint0"; ++ interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 ++ &cpu1_intc 3 &cpu1_intc 7 ++ &cpu2_intc 3 &cpu2_intc 7 ++ &cpu3_intc 3 &cpu3_intc 7 ++ &cpu4_intc 3 &cpu4_intc 7>; ++ reg = <0x0 0x2000000 0x0 0x10000>; ++ u-boot,dm-spl; ++ }; ++ }; ++}; ++ ++&prci { ++ u-boot,dm-spl; ++}; ++ ++&uart0 { ++ u-boot,dm-spl; ++}; ++ ++&spi0 { ++ u-boot,dm-spl; ++}; +diff --git a/arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi +new file mode 100644 +index 0000000..7171e25 +--- /dev/null ++++ b/arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi +@@ -0,0 +1,39 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (C) 2020 SiFive, Inc ++ */ ++ ++#include "fu740-c000-u-boot.dtsi" ++ ++/ { ++ aliases { ++ spi0 = &spi0; ++ }; ++ ++ memory@80000000 { ++ u-boot,dm-spl; ++ }; ++ ++ hfclk { ++ u-boot,dm-spl; ++ }; ++ ++ rtcclk { ++ u-boot,dm-spl; ++ }; ++ ++}; ++ ++&clint { ++ clocks = <&rtcclk>; ++}; ++ ++&spi0 { ++ mmc@0 { ++ u-boot,dm-spl; ++ }; ++}; ++ ++&gpio { ++ u-boot,dm-spl; ++}; +-- +2.7.4 + diff -Nru u-boot-2021.01+dfsg/debian/patches/riscv64/0012-dt-bindings-sifive-fu740-add-indexes-for-reset-signa.patch u-boot-2021.01+dfsg/debian/patches/riscv64/0012-dt-bindings-sifive-fu740-add-indexes-for-reset-signa.patch --- u-boot-2021.01+dfsg/debian/patches/riscv64/0012-dt-bindings-sifive-fu740-add-indexes-for-reset-signa.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/riscv64/0012-dt-bindings-sifive-fu740-add-indexes-for-reset-signa.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,43 @@ +From a8baf28b03f7c59fe839f2bd304e25cdc0d754b0 Mon Sep 17 00:00:00 2001 +From: Pragnesh Patel +Date: Sat, 31 Oct 2020 19:10:44 +0530 +Subject: [PATCH 12/41] dt-bindings: sifive: fu740: add indexes for reset + signals available in prci + +Add bit indexes for reset signals within the PRCI module +on FU740-C000 SoC. + +Signed-off-by: Pragnesh Patel +--- + include/dt-bindings/reset/sifive-fu740-prci.h | 19 +++++++++++++++++++ + 1 file changed, 19 insertions(+) + create mode 100644 include/dt-bindings/reset/sifive-fu740-prci.h + +diff --git a/include/dt-bindings/reset/sifive-fu740-prci.h b/include/dt-bindings/reset/sifive-fu740-prci.h +new file mode 100644 +index 0000000..a620865 +--- /dev/null ++++ b/include/dt-bindings/reset/sifive-fu740-prci.h +@@ -0,0 +1,19 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Copyright (C) 2020 Sifive, Inc. ++ * Author: Pragnesh Patel ++ */ ++ ++#ifndef __DT_BINDINGS_RESET_SIFIVE_FU740_PRCI_H ++#define __DT_BINDINGS_RESET_SIFIVE_FU740_PRCI_H ++ ++/* Reset indexes for use by device tree data and the PRCI driver */ ++#define PRCI_RST_DDR_CTRL_N 0 ++#define PRCI_RST_DDR_AXI_N 1 ++#define PRCI_RST_DDR_AHB_N 2 ++#define PRCI_RST_DDR_PHY_N 3 ++#define PRCI_RST_PCIE_POWER_UP_N 4 ++#define PRCI_RST_GEMGXL_N 5 ++#define PRCI_RST_CLTX_N 6 ++ ++#endif +-- +2.7.4 + diff -Nru u-boot-2021.01+dfsg/debian/patches/riscv64/0013-fu740-dtsi-add-reset-producer-and-consumer-entries.patch u-boot-2021.01+dfsg/debian/patches/riscv64/0013-fu740-dtsi-add-reset-producer-and-consumer-entries.patch --- u-boot-2021.01+dfsg/debian/patches/riscv64/0013-fu740-dtsi-add-reset-producer-and-consumer-entries.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/riscv64/0013-fu740-dtsi-add-reset-producer-and-consumer-entries.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,49 @@ +From d7a0143389875554621c27387537a1bd6a4e4e4f Mon Sep 17 00:00:00 2001 +From: Pragnesh Patel +Date: Sat, 31 Oct 2020 19:54:53 +0530 +Subject: [PATCH 13/41] fu740: dtsi: add reset producer and consumer entries + +The resets to DDR, ethernet and Chiplink sub-system are +connected to PRCI device reset control register, these reset +signals are active low and are held low at power-up. Add these +reset producer and consumer details needed by the reset driver. + +Signed-off-by: Pragnesh Patel +--- + arch/riscv/dts/fu740-c000-u-boot.dtsi | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +diff --git a/arch/riscv/dts/fu740-c000-u-boot.dtsi b/arch/riscv/dts/fu740-c000-u-boot.dtsi +index c7df15b..d38d573 100644 +--- a/arch/riscv/dts/fu740-c000-u-boot.dtsi ++++ b/arch/riscv/dts/fu740-c000-u-boot.dtsi +@@ -3,6 +3,8 @@ + * (C) Copyright 2020 SiFive, Inc + */ + ++#include ++ + / { + cpus { + assigned-clocks = <&prci PRCI_CLK_COREPLL>; +@@ -58,6 +60,17 @@ + reg = <0x0 0x2000000 0x0 0x10000>; + u-boot,dm-spl; + }; ++ prci: clock-controller@10000000 { ++ #reset-cells = <1>; ++ resets = <&prci PRCI_RST_DDR_CTRL_N>, ++ <&prci PRCI_RST_DDR_AXI_N>, ++ <&prci PRCI_RST_DDR_AHB_N>, ++ <&prci PRCI_RST_DDR_PHY_N>, ++ <&prci PRCI_RST_GEMGXL_N>, ++ <&prci PRCI_RST_CLTX_N>; ++ reset-names = "ddr_ctrl", "ddr_axi", "ddr_ahb", ++ "ddr_phy", "gemgxl_reset", "cltx_reset"; ++ }; + }; + }; + +-- +2.7.4 + diff -Nru u-boot-2021.01+dfsg/debian/patches/riscv64/0014-ram-sifive-Add-common-DDR-driver-for-sifive.patch u-boot-2021.01+dfsg/debian/patches/riscv64/0014-ram-sifive-Add-common-DDR-driver-for-sifive.patch --- u-boot-2021.01+dfsg/debian/patches/riscv64/0014-ram-sifive-Add-common-DDR-driver-for-sifive.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/riscv64/0014-ram-sifive-Add-common-DDR-driver-for-sifive.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,879 @@ +From 6dc2c6aadec593c9aad2d9e976d9585cfca29c92 Mon Sep 17 00:00:00 2001 +From: Pragnesh Patel +Date: Wed, 11 Nov 2020 18:49:20 +0530 +Subject: [PATCH 14/41] ram: sifive: Add common DDR driver for sifive + +Rename fu540_ddr.c to sifive_ddr.c, so that it can be used +by other SiFive SoCs + +Signed-off-by: Pragnesh Patel +--- + drivers/ram/sifive/Kconfig | 8 +- + drivers/ram/sifive/Makefile | 2 +- + drivers/ram/sifive/fu540_ddr.c | 409 ---------------------------------------- + drivers/ram/sifive/sifive_ddr.c | 409 ++++++++++++++++++++++++++++++++++++++++ + 4 files changed, 414 insertions(+), 414 deletions(-) + delete mode 100644 drivers/ram/sifive/fu540_ddr.c + create mode 100644 drivers/ram/sifive/sifive_ddr.c + +diff --git a/drivers/ram/sifive/Kconfig b/drivers/ram/sifive/Kconfig +index 6aca22a..b8ee6ce 100644 +--- a/drivers/ram/sifive/Kconfig ++++ b/drivers/ram/sifive/Kconfig +@@ -5,9 +5,9 @@ config RAM_SIFIVE + help + This enables support for ram drivers of SiFive SoCs. + +-config SIFIVE_FU540_DDR +- bool "SiFive FU540 DDR driver" ++config SIFIVE_DDR ++ bool "SiFive DDR driver" + depends on RAM_SIFIVE +- default y if TARGET_SIFIVE_FU540 ++ default y if TARGET_SIFIVE_FU540 || TARGET_SIFIVE_HIFIVE_UNMATCHED_FU740 + help +- This enables DDR support for the platforms based on SiFive FU540 SoC. ++ This enables DDR support for the platforms based on SiFive SoCs. +diff --git a/drivers/ram/sifive/Makefile b/drivers/ram/sifive/Makefile +index d66efec..4ef89f8 100644 +--- a/drivers/ram/sifive/Makefile ++++ b/drivers/ram/sifive/Makefile +@@ -3,4 +3,4 @@ + # Copyright (c) 2020 SiFive, Inc + # + +-obj-$(CONFIG_SIFIVE_FU540_DDR) += fu540_ddr.o ++obj-$(CONFIG_SIFIVE_DDR) += sifive_ddr.o +diff --git a/drivers/ram/sifive/fu540_ddr.c b/drivers/ram/sifive/fu540_ddr.c +deleted file mode 100644 +index 60d4945..0000000 +--- a/drivers/ram/sifive/fu540_ddr.c ++++ /dev/null +@@ -1,409 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +-/* +- * (C) Copyright 2020 SiFive, Inc. +- * +- * Authors: +- * Pragnesh Patel +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-#define DENALI_CTL_0 0 +-#define DENALI_CTL_21 21 +-#define DENALI_CTL_120 120 +-#define DENALI_CTL_132 132 +-#define DENALI_CTL_136 136 +-#define DENALI_CTL_170 170 +-#define DENALI_CTL_181 181 +-#define DENALI_CTL_182 182 +-#define DENALI_CTL_184 184 +-#define DENALI_CTL_208 208 +-#define DENALI_CTL_209 209 +-#define DENALI_CTL_210 210 +-#define DENALI_CTL_212 212 +-#define DENALI_CTL_214 214 +-#define DENALI_CTL_216 216 +-#define DENALI_CTL_224 224 +-#define DENALI_CTL_225 225 +-#define DENALI_CTL_260 260 +- +-#define DENALI_PHY_1152 1152 +-#define DENALI_PHY_1214 1214 +- +-#define DRAM_CLASS_OFFSET 8 +-#define DRAM_CLASS_DDR4 0xA +-#define OPTIMAL_RMODW_EN_OFFSET 0 +-#define DISABLE_RD_INTERLEAVE_OFFSET 16 +-#define OUT_OF_RANGE_OFFSET 1 +-#define MULTIPLE_OUT_OF_RANGE_OFFSET 2 +-#define PORT_COMMAND_CHANNEL_ERROR_OFFSET 7 +-#define MC_INIT_COMPLETE_OFFSET 8 +-#define LEVELING_OPERATION_COMPLETED_OFFSET 22 +-#define DFI_PHY_WRLELV_MODE_OFFSET 24 +-#define DFI_PHY_RDLVL_MODE_OFFSET 24 +-#define DFI_PHY_RDLVL_GATE_MODE_OFFSET 0 +-#define VREF_EN_OFFSET 24 +-#define PORT_ADDR_PROTECTION_EN_OFFSET 0 +-#define AXI0_ADDRESS_RANGE_ENABLE 8 +-#define AXI0_RANGE_PROT_BITS_0_OFFSET 24 +-#define RDLVL_EN_OFFSET 16 +-#define RDLVL_GATE_EN_OFFSET 24 +-#define WRLVL_EN_OFFSET 0 +- +-#define PHY_RX_CAL_DQ0_0_OFFSET 0 +-#define PHY_RX_CAL_DQ1_0_OFFSET 16 +- +-DECLARE_GLOBAL_DATA_PTR; +- +-struct fu540_ddrctl { +- volatile u32 denali_ctl[265]; +-}; +- +-struct fu540_ddrphy { +- volatile u32 denali_phy[1215]; +-}; +- +-/** +- * struct fu540_ddr_info +- * +- * @dev : pointer for the device +- * @info : UCLASS RAM information +- * @ctl : DDR controller base address +- * @phy : DDR PHY base address +- * @ctrl : DDR control base address +- * @physical_filter_ctrl : DDR physical filter control base address +- */ +-struct fu540_ddr_info { +- struct udevice *dev; +- struct ram_info info; +- struct fu540_ddrctl *ctl; +- struct fu540_ddrphy *phy; +- struct clk ddr_clk; +- u32 *physical_filter_ctrl; +-}; +- +-#if defined(CONFIG_SPL_BUILD) +-struct fu540_ddr_params { +- struct fu540_ddrctl pctl_regs; +- struct fu540_ddrphy phy_regs; +-}; +- +-struct sifive_dmc_plat { +- struct fu540_ddr_params ddr_params; +-}; +- +-/* +- * TODO : It can be possible to use common sdram_copy_to_reg() API +- * n: Unit bytes +- */ +-static void sdram_copy_to_reg(volatile u32 *dest, +- volatile u32 *src, u32 n) +-{ +- int i; +- +- for (i = 0; i < n / sizeof(u32); i++) { +- writel(*src, dest); +- src++; +- dest++; +- } +-} +- +-static void fu540_ddr_setup_range_protection(volatile u32 *ctl, u64 end_addr) +-{ +- u32 end_addr_16kblocks = ((end_addr >> 14) & 0x7FFFFF) - 1; +- +- writel(0x0, DENALI_CTL_209 + ctl); +- writel(end_addr_16kblocks, DENALI_CTL_210 + ctl); +- writel(0x0, DENALI_CTL_212 + ctl); +- writel(0x0, DENALI_CTL_214 + ctl); +- writel(0x0, DENALI_CTL_216 + ctl); +- setbits_le32(DENALI_CTL_224 + ctl, +- 0x3 << AXI0_RANGE_PROT_BITS_0_OFFSET); +- writel(0xFFFFFFFF, DENALI_CTL_225 + ctl); +- setbits_le32(DENALI_CTL_208 + ctl, 0x1 << AXI0_ADDRESS_RANGE_ENABLE); +- setbits_le32(DENALI_CTL_208 + ctl, +- 0x1 << PORT_ADDR_PROTECTION_EN_OFFSET); +-} +- +-static void fu540_ddr_start(volatile u32 *ctl, u32 *physical_filter_ctrl, +- u64 ddr_end) +-{ +- volatile u64 *filterreg = (volatile u64 *)physical_filter_ctrl; +- +- setbits_le32(DENALI_CTL_0 + ctl, 0x1); +- +- wait_for_bit_le32((void *)ctl + DENALI_CTL_132, +- BIT(MC_INIT_COMPLETE_OFFSET), false, 100, false); +- +- /* Disable the BusBlocker in front of the controller AXI slave ports */ +- filterreg[0] = 0x0f00000000000000UL | (ddr_end >> 2); +-} +- +-static void fu540_ddr_check_errata(u32 regbase, u32 updownreg) +-{ +- u64 fails = 0; +- u32 dq = 0; +- u32 down, up; +- u8 failc0, failc1; +- u32 phy_rx_cal_dqn_0_offset; +- +- for (u32 bit = 0; bit < 2; bit++) { +- if (bit == 0) { +- phy_rx_cal_dqn_0_offset = +- PHY_RX_CAL_DQ0_0_OFFSET; +- } else { +- phy_rx_cal_dqn_0_offset = +- PHY_RX_CAL_DQ1_0_OFFSET; +- } +- +- down = (updownreg >> +- phy_rx_cal_dqn_0_offset) & 0x3F; +- up = (updownreg >> +- (phy_rx_cal_dqn_0_offset + 6)) & +- 0x3F; +- +- failc0 = ((down == 0) && (up == 0x3F)); +- failc1 = ((up == 0) && (down == 0x3F)); +- +- /* print error message on failure */ +- if (failc0 || failc1) { +- if (fails == 0) +- printf("DDR error in fixing up\n"); +- +- fails |= (1 << dq); +- +- char slicelsc = '0'; +- char slicemsc = '0'; +- +- slicelsc += (dq % 10); +- slicemsc += (dq / 10); +- printf("S "); +- printf("%c", slicemsc); +- printf("%c", slicelsc); +- +- if (failc0) +- printf("U"); +- else +- printf("D"); +- +- printf("\n"); +- } +- dq++; +- } +-} +- +-static u64 fu540_ddr_phy_fixup(volatile u32 *ddrphyreg) +-{ +- u32 slicebase = 0; +- +- /* check errata condition */ +- for (u32 slice = 0; slice < 8; slice++) { +- u32 regbase = slicebase + 34; +- +- for (u32 reg = 0; reg < 4; reg++) { +- u32 updownreg = readl(regbase + reg + ddrphyreg); +- +- fu540_ddr_check_errata(regbase, updownreg); +- } +- slicebase += 128; +- } +- +- return(0); +-} +- +-static u32 fu540_ddr_get_dram_class(volatile u32 *ctl) +-{ +- u32 reg = readl(DENALI_CTL_0 + ctl); +- +- return ((reg >> DRAM_CLASS_OFFSET) & 0xF); +-} +- +-static int fu540_ddr_setup(struct udevice *dev) +-{ +- struct fu540_ddr_info *priv = dev_get_priv(dev); +- struct sifive_dmc_plat *plat = dev_get_platdata(dev); +- struct fu540_ddr_params *params = &plat->ddr_params; +- volatile u32 *denali_ctl = priv->ctl->denali_ctl; +- volatile u32 *denali_phy = priv->phy->denali_phy; +- const u64 ddr_size = priv->info.size; +- const u64 ddr_end = priv->info.base + ddr_size; +- int ret, i; +- u32 physet; +- +- ret = dev_read_u32_array(dev, "sifive,ddr-params", +- (u32 *)&plat->ddr_params, +- sizeof(plat->ddr_params) / sizeof(u32)); +- if (ret) { +- printf("%s: Cannot read sifive,ddr-params %d\n", +- __func__, ret); +- return ret; +- } +- +- sdram_copy_to_reg(priv->ctl->denali_ctl, +- params->pctl_regs.denali_ctl, +- sizeof(struct fu540_ddrctl)); +- +- /* phy reset */ +- for (i = DENALI_PHY_1152; i <= DENALI_PHY_1214; i++) { +- physet = params->phy_regs.denali_phy[i]; +- priv->phy->denali_phy[i] = physet; +- } +- +- for (i = 0; i < DENALI_PHY_1152; i++) { +- physet = params->phy_regs.denali_phy[i]; +- priv->phy->denali_phy[i] = physet; +- } +- +- /* Disable read interleave DENALI_CTL_120 */ +- setbits_le32(DENALI_CTL_120 + denali_ctl, +- 1 << DISABLE_RD_INTERLEAVE_OFFSET); +- +- /* Disable optimal read/modify/write logic DENALI_CTL_21 */ +- clrbits_le32(DENALI_CTL_21 + denali_ctl, 1 << OPTIMAL_RMODW_EN_OFFSET); +- +- /* Enable write Leveling DENALI_CTL_170 */ +- setbits_le32(DENALI_CTL_170 + denali_ctl, (1 << WRLVL_EN_OFFSET) +- | (1 << DFI_PHY_WRLELV_MODE_OFFSET)); +- +- /* Enable read leveling DENALI_CTL_181 and DENALI_CTL_260 */ +- setbits_le32(DENALI_CTL_181 + denali_ctl, +- 1 << DFI_PHY_RDLVL_MODE_OFFSET); +- setbits_le32(DENALI_CTL_260 + denali_ctl, 1 << RDLVL_EN_OFFSET); +- +- /* Enable read leveling gate DENALI_CTL_260 and DENALI_CTL_182 */ +- setbits_le32(DENALI_CTL_260 + denali_ctl, 1 << RDLVL_GATE_EN_OFFSET); +- setbits_le32(DENALI_CTL_182 + denali_ctl, +- 1 << DFI_PHY_RDLVL_GATE_MODE_OFFSET); +- +- if (fu540_ddr_get_dram_class(denali_ctl) == DRAM_CLASS_DDR4) { +- /* Enable vref training DENALI_CTL_184 */ +- setbits_le32(DENALI_CTL_184 + denali_ctl, 1 << VREF_EN_OFFSET); +- } +- +- /* Mask off leveling completion interrupt DENALI_CTL_136 */ +- setbits_le32(DENALI_CTL_136 + denali_ctl, +- 1 << LEVELING_OPERATION_COMPLETED_OFFSET); +- +- /* Mask off MC init complete interrupt DENALI_CTL_136 */ +- setbits_le32(DENALI_CTL_136 + denali_ctl, 1 << MC_INIT_COMPLETE_OFFSET); +- +- /* Mask off out of range interrupts DENALI_CTL_136 */ +- setbits_le32(DENALI_CTL_136 + denali_ctl, (1 << OUT_OF_RANGE_OFFSET) +- | (1 << MULTIPLE_OUT_OF_RANGE_OFFSET)); +- +- /* set up range protection */ +- fu540_ddr_setup_range_protection(denali_ctl, priv->info.size); +- +- /* Mask off port command error interrupt DENALI_CTL_136 */ +- setbits_le32(DENALI_CTL_136 + denali_ctl, +- 1 << PORT_COMMAND_CHANNEL_ERROR_OFFSET); +- +- fu540_ddr_start(denali_ctl, priv->physical_filter_ctrl, ddr_end); +- +- fu540_ddr_phy_fixup(denali_phy); +- +- /* check size */ +- priv->info.size = get_ram_size((long *)priv->info.base, +- ddr_size); +- +- debug("%s : %lx\n", __func__, (uintptr_t)priv->info.size); +- +- /* check memory access for all memory */ +- if (priv->info.size != ddr_size) { +- printf("DDR invalid size : 0x%lx, expected 0x%lx\n", +- (uintptr_t)priv->info.size, (uintptr_t)ddr_size); +- return -EINVAL; +- } +- +- return 0; +-} +-#endif +- +-static int fu540_ddr_probe(struct udevice *dev) +-{ +- struct fu540_ddr_info *priv = dev_get_priv(dev); +- +- /* Read memory base and size from DT */ +- fdtdec_setup_mem_size_base(); +- priv->info.base = gd->ram_base; +- priv->info.size = gd->ram_size; +- +-#if defined(CONFIG_SPL_BUILD) +- int ret; +- u32 clock = 0; +- +- debug("FU540 DDR probe\n"); +- priv->dev = dev; +- +- ret = clk_get_by_index(dev, 0, &priv->ddr_clk); +- if (ret) { +- debug("clk get failed %d\n", ret); +- return ret; +- } +- +- ret = dev_read_u32(dev, "clock-frequency", &clock); +- if (ret) { +- debug("clock-frequency not found in dt %d\n", ret); +- return ret; +- } else { +- ret = clk_set_rate(&priv->ddr_clk, clock); +- if (ret < 0) { +- debug("Could not set DDR clock\n"); +- return ret; +- } +- } +- +- ret = clk_enable(&priv->ddr_clk); +- if (ret < 0) { +- debug("Could not enable DDR clock\n"); +- return ret; +- } +- +- priv->ctl = (struct fu540_ddrctl *)dev_read_addr_index(dev, 0); +- priv->phy = (struct fu540_ddrphy *)dev_read_addr_index(dev, 1); +- priv->physical_filter_ctrl = (u32 *)dev_read_addr_index(dev, 2); +- +- return fu540_ddr_setup(dev); +-#endif +- +- return 0; +-} +- +-static int fu540_ddr_get_info(struct udevice *dev, struct ram_info *info) +-{ +- struct fu540_ddr_info *priv = dev_get_priv(dev); +- +- *info = priv->info; +- +- return 0; +-} +- +-static struct ram_ops fu540_ddr_ops = { +- .get_info = fu540_ddr_get_info, +-}; +- +-static const struct udevice_id fu540_ddr_ids[] = { +- { .compatible = "sifive,fu540-c000-ddr" }, +- { } +-}; +- +-U_BOOT_DRIVER(fu540_ddr) = { +- .name = "fu540_ddr", +- .id = UCLASS_RAM, +- .of_match = fu540_ddr_ids, +- .ops = &fu540_ddr_ops, +- .probe = fu540_ddr_probe, +- .priv_auto_alloc_size = sizeof(struct fu540_ddr_info), +-#if defined(CONFIG_SPL_BUILD) +- .platdata_auto_alloc_size = sizeof(struct sifive_dmc_plat), +-#endif +-}; +diff --git a/drivers/ram/sifive/sifive_ddr.c b/drivers/ram/sifive/sifive_ddr.c +new file mode 100644 +index 0000000..e74ac49 +--- /dev/null ++++ b/drivers/ram/sifive/sifive_ddr.c +@@ -0,0 +1,409 @@ ++// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause ++/* ++ * (C) Copyright 2020 SiFive, Inc. ++ * ++ * Authors: ++ * Pragnesh Patel ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define DENALI_CTL_0 0 ++#define DENALI_CTL_21 21 ++#define DENALI_CTL_120 120 ++#define DENALI_CTL_132 132 ++#define DENALI_CTL_136 136 ++#define DENALI_CTL_170 170 ++#define DENALI_CTL_181 181 ++#define DENALI_CTL_182 182 ++#define DENALI_CTL_184 184 ++#define DENALI_CTL_208 208 ++#define DENALI_CTL_209 209 ++#define DENALI_CTL_210 210 ++#define DENALI_CTL_212 212 ++#define DENALI_CTL_214 214 ++#define DENALI_CTL_216 216 ++#define DENALI_CTL_224 224 ++#define DENALI_CTL_225 225 ++#define DENALI_CTL_260 260 ++ ++#define DENALI_PHY_1152 1152 ++#define DENALI_PHY_1214 1214 ++ ++#define DRAM_CLASS_OFFSET 8 ++#define DRAM_CLASS_DDR4 0xA ++#define OPTIMAL_RMODW_EN_OFFSET 0 ++#define DISABLE_RD_INTERLEAVE_OFFSET 16 ++#define OUT_OF_RANGE_OFFSET 1 ++#define MULTIPLE_OUT_OF_RANGE_OFFSET 2 ++#define PORT_COMMAND_CHANNEL_ERROR_OFFSET 7 ++#define MC_INIT_COMPLETE_OFFSET 8 ++#define LEVELING_OPERATION_COMPLETED_OFFSET 22 ++#define DFI_PHY_WRLELV_MODE_OFFSET 24 ++#define DFI_PHY_RDLVL_MODE_OFFSET 24 ++#define DFI_PHY_RDLVL_GATE_MODE_OFFSET 0 ++#define VREF_EN_OFFSET 24 ++#define PORT_ADDR_PROTECTION_EN_OFFSET 0 ++#define AXI0_ADDRESS_RANGE_ENABLE 8 ++#define AXI0_RANGE_PROT_BITS_0_OFFSET 24 ++#define RDLVL_EN_OFFSET 16 ++#define RDLVL_GATE_EN_OFFSET 24 ++#define WRLVL_EN_OFFSET 0 ++ ++#define PHY_RX_CAL_DQ0_0_OFFSET 0 ++#define PHY_RX_CAL_DQ1_0_OFFSET 16 ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++struct sifive_ddrctl { ++ volatile u32 denali_ctl[265]; ++}; ++ ++struct sifive_ddrphy { ++ volatile u32 denali_phy[1215]; ++}; ++ ++/** ++ * struct sifive_ddr_info ++ * ++ * @dev : pointer for the device ++ * @info : UCLASS RAM information ++ * @ctl : DDR controller base address ++ * @phy : DDR PHY base address ++ * @ctrl : DDR control base address ++ * @physical_filter_ctrl : DDR physical filter control base address ++ */ ++struct sifive_ddr_info { ++ struct udevice *dev; ++ struct ram_info info; ++ struct sifive_ddrctl *ctl; ++ struct sifive_ddrphy *phy; ++ struct clk ddr_clk; ++ u32 *physical_filter_ctrl; ++}; ++ ++#if defined(CONFIG_SPL_BUILD) ++struct sifive_ddr_params { ++ struct sifive_ddrctl pctl_regs; ++ struct sifive_ddrphy phy_regs; ++}; ++ ++struct sifive_dmc_plat { ++ struct sifive_ddr_params ddr_params; ++}; ++ ++/* ++ * TODO : It can be possible to use common sdram_copy_to_reg() API ++ * n: Unit bytes ++ */ ++static void sdram_copy_to_reg(volatile u32 *dest, ++ volatile u32 *src, u32 n) ++{ ++ int i; ++ ++ for (i = 0; i < n / sizeof(u32); i++) { ++ writel(*src, dest); ++ src++; ++ dest++; ++ } ++} ++ ++static void sifive_ddr_setup_range_protection(volatile u32 *ctl, u64 end_addr) ++{ ++ u32 end_addr_16kblocks = ((end_addr >> 14) & 0x7FFFFF) - 1; ++ ++ writel(0x0, DENALI_CTL_209 + ctl); ++ writel(end_addr_16kblocks, DENALI_CTL_210 + ctl); ++ writel(0x0, DENALI_CTL_212 + ctl); ++ writel(0x0, DENALI_CTL_214 + ctl); ++ writel(0x0, DENALI_CTL_216 + ctl); ++ setbits_le32(DENALI_CTL_224 + ctl, ++ 0x3 << AXI0_RANGE_PROT_BITS_0_OFFSET); ++ writel(0xFFFFFFFF, DENALI_CTL_225 + ctl); ++ setbits_le32(DENALI_CTL_208 + ctl, 0x1 << AXI0_ADDRESS_RANGE_ENABLE); ++ setbits_le32(DENALI_CTL_208 + ctl, ++ 0x1 << PORT_ADDR_PROTECTION_EN_OFFSET); ++} ++ ++static void sifive_ddr_start(volatile u32 *ctl, u32 *physical_filter_ctrl, ++ u64 ddr_end) ++{ ++ volatile u64 *filterreg = (volatile u64 *)physical_filter_ctrl; ++ ++ setbits_le32(DENALI_CTL_0 + ctl, 0x1); ++ ++ wait_for_bit_le32((void *)ctl + DENALI_CTL_132, ++ BIT(MC_INIT_COMPLETE_OFFSET), false, 100, false); ++ ++ /* Disable the BusBlocker in front of the controller AXI slave ports */ ++ filterreg[0] = 0x0f00000000000000UL | (ddr_end >> 2); ++} ++ ++static void sifive_ddr_check_errata(u32 regbase, u32 updownreg) ++{ ++ u64 fails = 0; ++ u32 dq = 0; ++ u32 down, up; ++ u8 failc0, failc1; ++ u32 phy_rx_cal_dqn_0_offset; ++ ++ for (u32 bit = 0; bit < 2; bit++) { ++ if (bit == 0) { ++ phy_rx_cal_dqn_0_offset = ++ PHY_RX_CAL_DQ0_0_OFFSET; ++ } else { ++ phy_rx_cal_dqn_0_offset = ++ PHY_RX_CAL_DQ1_0_OFFSET; ++ } ++ ++ down = (updownreg >> ++ phy_rx_cal_dqn_0_offset) & 0x3F; ++ up = (updownreg >> ++ (phy_rx_cal_dqn_0_offset + 6)) & ++ 0x3F; ++ ++ failc0 = ((down == 0) && (up == 0x3F)); ++ failc1 = ((up == 0) && (down == 0x3F)); ++ ++ /* print error message on failure */ ++ if (failc0 || failc1) { ++ if (fails == 0) ++ printf("DDR error in fixing up\n"); ++ ++ fails |= (1 << dq); ++ ++ char slicelsc = '0'; ++ char slicemsc = '0'; ++ ++ slicelsc += (dq % 10); ++ slicemsc += (dq / 10); ++ printf("S "); ++ printf("%c", slicemsc); ++ printf("%c", slicelsc); ++ ++ if (failc0) ++ printf("U"); ++ else ++ printf("D"); ++ ++ printf("\n"); ++ } ++ dq++; ++ } ++} ++ ++static u64 sifive_ddr_phy_fixup(volatile u32 *ddrphyreg) ++{ ++ u32 slicebase = 0; ++ ++ /* check errata condition */ ++ for (u32 slice = 0; slice < 8; slice++) { ++ u32 regbase = slicebase + 34; ++ ++ for (u32 reg = 0; reg < 4; reg++) { ++ u32 updownreg = readl(regbase + reg + ddrphyreg); ++ ++ sifive_ddr_check_errata(regbase, updownreg); ++ } ++ slicebase += 128; ++ } ++ ++ return(0); ++} ++ ++static u32 sifive_ddr_get_dram_class(volatile u32 *ctl) ++{ ++ u32 reg = readl(DENALI_CTL_0 + ctl); ++ ++ return ((reg >> DRAM_CLASS_OFFSET) & 0xF); ++} ++ ++static int sifive_ddr_setup(struct udevice *dev) ++{ ++ struct sifive_ddr_info *priv = dev_get_priv(dev); ++ struct sifive_dmc_plat *plat = dev_get_platdata(dev); ++ struct sifive_ddr_params *params = &plat->ddr_params; ++ volatile u32 *denali_ctl = priv->ctl->denali_ctl; ++ volatile u32 *denali_phy = priv->phy->denali_phy; ++ const u64 ddr_size = priv->info.size; ++ const u64 ddr_end = priv->info.base + ddr_size; ++ int ret, i; ++ u32 physet; ++ ++ ret = dev_read_u32_array(dev, "sifive,ddr-params", ++ (u32 *)&plat->ddr_params, ++ sizeof(plat->ddr_params) / sizeof(u32)); ++ if (ret) { ++ printf("%s: Cannot read sifive,ddr-params %d\n", ++ __func__, ret); ++ return ret; ++ } ++ ++ sdram_copy_to_reg(priv->ctl->denali_ctl, ++ params->pctl_regs.denali_ctl, ++ sizeof(struct sifive_ddrctl)); ++ ++ /* phy reset */ ++ for (i = DENALI_PHY_1152; i <= DENALI_PHY_1214; i++) { ++ physet = params->phy_regs.denali_phy[i]; ++ priv->phy->denali_phy[i] = physet; ++ } ++ ++ for (i = 0; i < DENALI_PHY_1152; i++) { ++ physet = params->phy_regs.denali_phy[i]; ++ priv->phy->denali_phy[i] = physet; ++ } ++ ++ /* Disable read interleave DENALI_CTL_120 */ ++ setbits_le32(DENALI_CTL_120 + denali_ctl, ++ 1 << DISABLE_RD_INTERLEAVE_OFFSET); ++ ++ /* Disable optimal read/modify/write logic DENALI_CTL_21 */ ++ clrbits_le32(DENALI_CTL_21 + denali_ctl, 1 << OPTIMAL_RMODW_EN_OFFSET); ++ ++ /* Enable write Leveling DENALI_CTL_170 */ ++ setbits_le32(DENALI_CTL_170 + denali_ctl, (1 << WRLVL_EN_OFFSET) ++ | (1 << DFI_PHY_WRLELV_MODE_OFFSET)); ++ ++ /* Enable read leveling DENALI_CTL_181 and DENALI_CTL_260 */ ++ setbits_le32(DENALI_CTL_181 + denali_ctl, ++ 1 << DFI_PHY_RDLVL_MODE_OFFSET); ++ setbits_le32(DENALI_CTL_260 + denali_ctl, 1 << RDLVL_EN_OFFSET); ++ ++ /* Enable read leveling gate DENALI_CTL_260 and DENALI_CTL_182 */ ++ setbits_le32(DENALI_CTL_260 + denali_ctl, 1 << RDLVL_GATE_EN_OFFSET); ++ setbits_le32(DENALI_CTL_182 + denali_ctl, ++ 1 << DFI_PHY_RDLVL_GATE_MODE_OFFSET); ++ ++ if (sifive_ddr_get_dram_class(denali_ctl) == DRAM_CLASS_DDR4) { ++ /* Enable vref training DENALI_CTL_184 */ ++ setbits_le32(DENALI_CTL_184 + denali_ctl, 1 << VREF_EN_OFFSET); ++ } ++ ++ /* Mask off leveling completion interrupt DENALI_CTL_136 */ ++ setbits_le32(DENALI_CTL_136 + denali_ctl, ++ 1 << LEVELING_OPERATION_COMPLETED_OFFSET); ++ ++ /* Mask off MC init complete interrupt DENALI_CTL_136 */ ++ setbits_le32(DENALI_CTL_136 + denali_ctl, 1 << MC_INIT_COMPLETE_OFFSET); ++ ++ /* Mask off out of range interrupts DENALI_CTL_136 */ ++ setbits_le32(DENALI_CTL_136 + denali_ctl, (1 << OUT_OF_RANGE_OFFSET) ++ | (1 << MULTIPLE_OUT_OF_RANGE_OFFSET)); ++ ++ /* set up range protection */ ++ sifive_ddr_setup_range_protection(denali_ctl, priv->info.size); ++ ++ /* Mask off port command error interrupt DENALI_CTL_136 */ ++ setbits_le32(DENALI_CTL_136 + denali_ctl, ++ 1 << PORT_COMMAND_CHANNEL_ERROR_OFFSET); ++ ++ sifive_ddr_start(denali_ctl, priv->physical_filter_ctrl, ddr_end); ++ ++ sifive_ddr_phy_fixup(denali_phy); ++ ++ /* check size */ ++ priv->info.size = get_ram_size((long *)priv->info.base, ++ ddr_size); ++ ++ debug("%s : %lx\n", __func__, (uintptr_t)priv->info.size); ++ ++ /* check memory access for all memory */ ++ if (priv->info.size != ddr_size) { ++ printf("DDR invalid size : 0x%lx, expected 0x%lx\n", ++ (uintptr_t)priv->info.size, (uintptr_t)ddr_size); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++#endif ++ ++static int sifive_ddr_probe(struct udevice *dev) ++{ ++ struct sifive_ddr_info *priv = dev_get_priv(dev); ++ ++ /* Read memory base and size from DT */ ++ fdtdec_setup_mem_size_base(); ++ priv->info.base = gd->ram_base; ++ priv->info.size = gd->ram_size; ++ ++#if defined(CONFIG_SPL_BUILD) ++ int ret; ++ u32 clock = 0; ++ ++ debug("sifive DDR probe\n"); ++ priv->dev = dev; ++ ++ ret = clk_get_by_index(dev, 0, &priv->ddr_clk); ++ if (ret) { ++ debug("clk get failed %d\n", ret); ++ return ret; ++ } ++ ++ ret = dev_read_u32(dev, "clock-frequency", &clock); ++ if (ret) { ++ debug("clock-frequency not found in dt %d\n", ret); ++ return ret; ++ } else { ++ ret = clk_set_rate(&priv->ddr_clk, clock); ++ if (ret < 0) { ++ debug("Could not set DDR clock\n"); ++ return ret; ++ } ++ } ++ ++ ret = clk_enable(&priv->ddr_clk); ++ if (ret < 0) { ++ debug("Could not enable DDR clock\n"); ++ return ret; ++ } ++ ++ priv->ctl = (struct sifive_ddrctl *)dev_read_addr_index(dev, 0); ++ priv->phy = (struct sifive_ddrphy *)dev_read_addr_index(dev, 1); ++ priv->physical_filter_ctrl = (u32 *)dev_read_addr_index(dev, 2); ++ ++ return sifive_ddr_setup(dev); ++#endif ++ ++ return 0; ++} ++ ++static int sifive_ddr_get_info(struct udevice *dev, struct ram_info *info) ++{ ++ struct sifive_ddr_info *priv = dev_get_priv(dev); ++ ++ *info = priv->info; ++ ++ return 0; ++} ++ ++static struct ram_ops sifive_ddr_ops = { ++ .get_info = sifive_ddr_get_info, ++}; ++ ++static const struct udevice_id sifive_ddr_ids[] = { ++ { .compatible = "sifive,fu540-c000-ddr" }, ++ { } ++}; ++ ++U_BOOT_DRIVER(sifive_ddr) = { ++ .name = "sifive_ddr", ++ .id = UCLASS_RAM, ++ .of_match = sifive_ddr_ids, ++ .ops = &sifive_ddr_ops, ++ .probe = sifive_ddr_probe, ++ .priv_auto_alloc_size = sizeof(struct sifive_ddr_info), ++#if defined(CONFIG_SPL_BUILD) ++ .platdata_auto_alloc_size = sizeof(struct sifive_dmc_plat), ++#endif ++}; +-- +2.7.4 + diff -Nru u-boot-2021.01+dfsg/debian/patches/riscv64/0015-ram-sifive-Added-compatible-string-for-FU740-c000-dd.patch u-boot-2021.01+dfsg/debian/patches/riscv64/0015-ram-sifive-Added-compatible-string-for-FU740-c000-dd.patch --- u-boot-2021.01+dfsg/debian/patches/riscv64/0015-ram-sifive-Added-compatible-string-for-FU740-c000-dd.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/riscv64/0015-ram-sifive-Added-compatible-string-for-FU740-c000-dd.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,27 @@ +From e46d8dbd2952ea9daa057a40472e09d84d1c1641 Mon Sep 17 00:00:00 2001 +From: Pragnesh Patel +Date: Wed, 11 Nov 2020 18:50:19 +0530 +Subject: [PATCH 15/41] ram: sifive: Added compatible string for FU740-c000 ddr + +Added FU740-c000 ddr compatible string + +Signed-off-by: Pragnesh Patel +--- + drivers/ram/sifive/sifive_ddr.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/ram/sifive/sifive_ddr.c b/drivers/ram/sifive/sifive_ddr.c +index e74ac49..c464fea 100644 +--- a/drivers/ram/sifive/sifive_ddr.c ++++ b/drivers/ram/sifive/sifive_ddr.c +@@ -393,6 +393,7 @@ static struct ram_ops sifive_ddr_ops = { + + static const struct udevice_id sifive_ddr_ids[] = { + { .compatible = "sifive,fu540-c000-ddr" }, ++ { .compatible = "sifive,fu740-c000-ddr" }, + { } + }; + +-- +2.7.4 + diff -Nru u-boot-2021.01+dfsg/debian/patches/riscv64/0016-sifive-dts-fu740-Add-DDR-controller-and-phy-register.patch u-boot-2021.01+dfsg/debian/patches/riscv64/0016-sifive-dts-fu740-Add-DDR-controller-and-phy-register.patch --- u-boot-2021.01+dfsg/debian/patches/riscv64/0016-sifive-dts-fu740-Add-DDR-controller-and-phy-register.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/riscv64/0016-sifive-dts-fu740-Add-DDR-controller-and-phy-register.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,1526 @@ +From 43ddc5a21593c4b6a51cd0a47ce1193cf7a1b590 Mon Sep 17 00:00:00 2001 +From: Pragnesh Patel +Date: Tue, 10 Nov 2020 18:53:06 +0530 +Subject: [PATCH 16/41] sifive: dts: fu740: Add DDR controller and phy register + settings + +Add DDR controller and phy register settings for +SiFive hifive-unmatched board + +Signed-off-by: Pragnesh Patel +--- + arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi | 1489 ++++++++++++++++++++ + arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi | 1 + + 2 files changed, 1490 insertions(+) + create mode 100644 arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi + +diff --git a/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi b/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi +new file mode 100644 +index 0000000..0c4dedd +--- /dev/null ++++ b/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi +@@ -0,0 +1,1489 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * (C) Copyright 2020 SiFive, Inc ++ */ ++ ++&dmc { ++ sifive,ddr-params = < ++ 0x00000a00 /* DENALI_CTL_00_DATA */ ++ 0x00000000 /* DENALI_CTL_01_DATA */ ++ 0x00000000 /* DENALI_CTL_02_DATA */ ++ 0x00000000 /* DENALI_CTL_03_DATA */ ++ 0x00000000 /* DENALI_CTL_04_DATA */ ++ 0x00000000 /* DENALI_CTL_05_DATA */ ++ 0x0000000b /* DENALI_CTL_06_DATA */ ++ 0x00033f1e /* DENALI_CTL_07_DATA */ ++ 0x00081dcb /* DENALI_CTL_08_DATA */ ++ 0x0b200300 /* DENALI_CTL_09_DATA */ ++ 0x1c1c0400 /* DENALI_CTL_10_DATA */ ++ 0x04049a0d /* DENALI_CTL_11_DATA */ ++ 0x32060406 /* DENALI_CTL_12_DATA */ ++ 0x100d0823 /* DENALI_CTL_13_DATA */ ++ 0x080a0a17 /* DENALI_CTL_14_DATA */ ++ 0x0123b818 /* DENALI_CTL_15_DATA */ ++ 0x00180b06 /* DENALI_CTL_16_DATA */ ++ 0x00a01510 /* DENALI_CTL_17_DATA */ ++ 0x01000118 /* DENALI_CTL_18_DATA */ ++ 0x10032501 /* DENALI_CTL_19_DATA */ ++ 0x00000000 /* DENALI_CTL_20_DATA */ ++ 0x00000101 /* DENALI_CTL_21_DATA */ ++ 0x00000000 /* DENALI_CTL_22_DATA */ ++ 0x0a000000 /* DENALI_CTL_23_DATA */ ++ 0x00000000 /* DENALI_CTL_24_DATA */ ++ 0x01750100 /* DENALI_CTL_25_DATA */ ++ 0x00002069 /* DENALI_CTL_26_DATA */ ++ 0x00000005 /* DENALI_CTL_27_DATA */ ++ 0x001a0007 /* DENALI_CTL_28_DATA */ ++ 0x017f0300 /* DENALI_CTL_29_DATA */ ++ 0x03010000 /* DENALI_CTL_30_DATA */ ++ 0x000b0f00 /* DENALI_CTL_31_DATA */ ++ 0x04030200 /* DENALI_CTL_32_DATA */ ++ 0x0000031f /* DENALI_CTL_33_DATA */ ++ 0x00070004 /* DENALI_CTL_34_DATA */ ++ 0x00000000 /* DENALI_CTL_35_DATA */ ++ 0x00000000 /* DENALI_CTL_36_DATA */ ++ 0x00000000 /* DENALI_CTL_37_DATA */ ++ 0x00000000 /* DENALI_CTL_38_DATA */ ++ 0x00000000 /* DENALI_CTL_39_DATA */ ++ 0x00000000 /* DENALI_CTL_40_DATA */ ++ 0x00000000 /* DENALI_CTL_41_DATA */ ++ 0x00000000 /* DENALI_CTL_42_DATA */ ++ 0x00000000 /* DENALI_CTL_43_DATA */ ++ 0x00000000 /* DENALI_CTL_44_DATA */ ++ 0x00000000 /* DENALI_CTL_45_DATA */ ++ 0x00000000 /* DENALI_CTL_46_DATA */ ++ 0x00000000 /* DENALI_CTL_47_DATA */ ++ 0x00000000 /* DENALI_CTL_48_DATA */ ++ 0x00000000 /* DENALI_CTL_49_DATA */ ++ 0x00000000 /* DENALI_CTL_50_DATA */ ++ 0x00000000 /* DENALI_CTL_51_DATA */ ++ 0x00000000 /* DENALI_CTL_52_DATA */ ++ 0x00000000 /* DENALI_CTL_53_DATA */ ++ 0x00000000 /* DENALI_CTL_54_DATA */ ++ 0x00000000 /* DENALI_CTL_55_DATA */ ++ 0x00000000 /* DENALI_CTL_56_DATA */ ++ 0x00000000 /* DENALI_CTL_57_DATA */ ++ 0x00000000 /* DENALI_CTL_58_DATA */ ++ 0x00000000 /* DENALI_CTL_59_DATA */ ++ 0x00000634 /* DENALI_CTL_60_DATA */ ++ 0x00000201 /* DENALI_CTL_61_DATA */ ++ 0x00001010 /* DENALI_CTL_62_DATA */ ++ 0x00000000 /* DENALI_CTL_63_DATA */ ++ 0x00000200 /* DENALI_CTL_64_DATA */ ++ 0x00000000 /* DENALI_CTL_65_DATA */ ++ 0x00000481 /* DENALI_CTL_66_DATA */ ++ 0x00000800 /* DENALI_CTL_67_DATA */ ++ 0x00000634 /* DENALI_CTL_68_DATA */ ++ 0x00000201 /* DENALI_CTL_69_DATA */ ++ 0x00001010 /* DENALI_CTL_70_DATA */ ++ 0x00000000 /* DENALI_CTL_71_DATA */ ++ 0x00000200 /* DENALI_CTL_72_DATA */ ++ 0x00000000 /* DENALI_CTL_73_DATA */ ++ 0x00000481 /* DENALI_CTL_74_DATA */ ++ 0x00000800 /* DENALI_CTL_75_DATA */ ++ 0x01010000 /* DENALI_CTL_76_DATA */ ++ 0x00000000 /* DENALI_CTL_77_DATA */ ++ 0x00000000 /* DENALI_CTL_78_DATA */ ++ 0x00000000 /* DENALI_CTL_79_DATA */ ++ 0x00000000 /* DENALI_CTL_80_DATA */ ++ 0x00000000 /* DENALI_CTL_81_DATA */ ++ 0x00000000 /* DENALI_CTL_82_DATA */ ++ 0x00000000 /* DENALI_CTL_83_DATA */ ++ 0x00000000 /* DENALI_CTL_84_DATA */ ++ 0x00000000 /* DENALI_CTL_85_DATA */ ++ 0x00000000 /* DENALI_CTL_86_DATA */ ++ 0x00000000 /* DENALI_CTL_87_DATA */ ++ 0x00000000 /* DENALI_CTL_88_DATA */ ++ 0x00000000 /* DENALI_CTL_89_DATA */ ++ 0x00000000 /* DENALI_CTL_90_DATA */ ++ 0x00000000 /* DENALI_CTL_91_DATA */ ++ 0x00000000 /* DENALI_CTL_92_DATA */ ++ 0x00000000 /* DENALI_CTL_93_DATA */ ++ 0x00000000 /* DENALI_CTL_94_DATA */ ++ 0x00000000 /* DENALI_CTL_95_DATA */ ++ 0x00000000 /* DENALI_CTL_96_DATA */ ++ 0x00000000 /* DENALI_CTL_97_DATA */ ++ 0x00000000 /* DENALI_CTL_98_DATA */ ++ 0x00000000 /* DENALI_CTL_99_DATA */ ++ 0x00000000 /* DENALI_CTL_100_DATA */ ++ 0x00000000 /* DENALI_CTL_101_DATA */ ++ 0x00000000 /* DENALI_CTL_102_DATA */ ++ 0x00000000 /* DENALI_CTL_103_DATA */ ++ 0x00000000 /* DENALI_CTL_104_DATA */ ++ 0x00000003 /* DENALI_CTL_105_DATA */ ++ 0x00000000 /* DENALI_CTL_106_DATA */ ++ 0x00000000 /* DENALI_CTL_107_DATA */ ++ 0x00000000 /* DENALI_CTL_108_DATA */ ++ 0x00000000 /* DENALI_CTL_109_DATA */ ++ 0x01000000 /* DENALI_CTL_110_DATA */ ++ 0x00040000 /* DENALI_CTL_111_DATA */ ++ 0x00800200 /* DENALI_CTL_112_DATA */ ++ 0x00000200 /* DENALI_CTL_113_DATA */ ++ 0x00000040 /* DENALI_CTL_114_DATA */ ++ 0x01000100 /* DENALI_CTL_115_DATA */ ++ 0x0a000002 /* DENALI_CTL_116_DATA */ ++ 0x0101ffff /* DENALI_CTL_117_DATA */ ++ 0x01010101 /* DENALI_CTL_118_DATA */ ++ 0x01010101 /* DENALI_CTL_119_DATA */ ++ 0x0000010b /* DENALI_CTL_120_DATA */ ++ 0x00000c01 /* DENALI_CTL_121_DATA */ ++ 0x00000000 /* DENALI_CTL_122_DATA */ ++ 0x00000000 /* DENALI_CTL_123_DATA */ ++ 0x00000000 /* DENALI_CTL_124_DATA */ ++ 0x00000000 /* DENALI_CTL_125_DATA */ ++ 0x00030300 /* DENALI_CTL_126_DATA */ ++ 0x00000000 /* DENALI_CTL_127_DATA */ ++ 0x00010001 /* DENALI_CTL_128_DATA */ ++ 0x00000000 /* DENALI_CTL_129_DATA */ ++ 0x00000000 /* DENALI_CTL_130_DATA */ ++ 0x00000000 /* DENALI_CTL_131_DATA */ ++ 0x00000000 /* DENALI_CTL_132_DATA */ ++ 0x00000000 /* DENALI_CTL_133_DATA */ ++ 0x00000000 /* DENALI_CTL_134_DATA */ ++ 0x00000000 /* DENALI_CTL_135_DATA */ ++ 0x00000000 /* DENALI_CTL_136_DATA */ ++ 0x00000000 /* DENALI_CTL_137_DATA */ ++ 0x00000000 /* DENALI_CTL_138_DATA */ ++ 0x00000000 /* DENALI_CTL_139_DATA */ ++ 0x00000000 /* DENALI_CTL_140_DATA */ ++ 0x00000000 /* DENALI_CTL_141_DATA */ ++ 0x00000000 /* DENALI_CTL_142_DATA */ ++ 0x00000000 /* DENALI_CTL_143_DATA */ ++ 0x00000000 /* DENALI_CTL_144_DATA */ ++ 0x00000000 /* DENALI_CTL_145_DATA */ ++ 0x00000000 /* DENALI_CTL_146_DATA */ ++ 0x00000000 /* DENALI_CTL_147_DATA */ ++ 0x00000000 /* DENALI_CTL_148_DATA */ ++ 0x00000000 /* DENALI_CTL_149_DATA */ ++ 0x00000000 /* DENALI_CTL_150_DATA */ ++ 0x00000000 /* DENALI_CTL_151_DATA */ ++ 0x00000000 /* DENALI_CTL_152_DATA */ ++ 0x00000000 /* DENALI_CTL_153_DATA */ ++ 0x00000000 /* DENALI_CTL_154_DATA */ ++ 0x00000000 /* DENALI_CTL_155_DATA */ ++ 0x00000000 /* DENALI_CTL_156_DATA */ ++ 0x00000000 /* DENALI_CTL_157_DATA */ ++ 0x00000000 /* DENALI_CTL_158_DATA */ ++ 0x00000000 /* DENALI_CTL_159_DATA */ ++ 0x00000000 /* DENALI_CTL_160_DATA */ ++ 0x02010102 /* DENALI_CTL_161_DATA */ ++ 0x0107070e /* DENALI_CTL_162_DATA */ ++ 0x04040500 /* DENALI_CTL_163_DATA */ ++ 0x03000502 /* DENALI_CTL_164_DATA */ ++ 0x00000000 /* DENALI_CTL_165_DATA */ ++ 0x00000000 /* DENALI_CTL_166_DATA */ ++ 0x00000000 /* DENALI_CTL_167_DATA */ ++ 0x00000000 /* DENALI_CTL_168_DATA */ ++ 0x280d0000 /* DENALI_CTL_169_DATA */ ++ 0x01000000 /* DENALI_CTL_170_DATA */ ++ 0x00000000 /* DENALI_CTL_171_DATA */ ++ 0x00010001 /* DENALI_CTL_172_DATA */ ++ 0x00000000 /* DENALI_CTL_173_DATA */ ++ 0x00000000 /* DENALI_CTL_174_DATA */ ++ 0x00000000 /* DENALI_CTL_175_DATA */ ++ 0x00000000 /* DENALI_CTL_176_DATA */ ++ 0x00000000 /* DENALI_CTL_177_DATA */ ++ 0x00000000 /* DENALI_CTL_178_DATA */ ++ 0x00000000 /* DENALI_CTL_179_DATA */ ++ 0x00000000 /* DENALI_CTL_180_DATA */ ++ 0x01000000 /* DENALI_CTL_181_DATA */ ++ 0x00000001 /* DENALI_CTL_182_DATA */ ++ 0x00000100 /* DENALI_CTL_183_DATA */ ++ 0x00010101 /* DENALI_CTL_184_DATA */ ++ 0x67676701 /* DENALI_CTL_185_DATA */ ++ 0x67676767 /* DENALI_CTL_186_DATA */ ++ 0x67676767 /* DENALI_CTL_187_DATA */ ++ 0x67676767 /* DENALI_CTL_188_DATA */ ++ 0x67676767 /* DENALI_CTL_189_DATA */ ++ 0x67676767 /* DENALI_CTL_190_DATA */ ++ 0x67676767 /* DENALI_CTL_191_DATA */ ++ 0x67676767 /* DENALI_CTL_192_DATA */ ++ 0x67676767 /* DENALI_CTL_193_DATA */ ++ 0x01000067 /* DENALI_CTL_194_DATA */ ++ 0x00000001 /* DENALI_CTL_195_DATA */ ++ 0x00000101 /* DENALI_CTL_196_DATA */ ++ 0x00000000 /* DENALI_CTL_197_DATA */ ++ 0x00000000 /* DENALI_CTL_198_DATA */ ++ 0x00000000 /* DENALI_CTL_199_DATA */ ++ 0x00000000 /* DENALI_CTL_200_DATA */ ++ 0x00000000 /* DENALI_CTL_201_DATA */ ++ 0x00000000 /* DENALI_CTL_202_DATA */ ++ 0x00000000 /* DENALI_CTL_203_DATA */ ++ 0x00000000 /* DENALI_CTL_204_DATA */ ++ 0x00000000 /* DENALI_CTL_205_DATA */ ++ 0x00000000 /* DENALI_CTL_206_DATA */ ++ 0x00000000 /* DENALI_CTL_207_DATA */ ++ 0x00000001 /* DENALI_CTL_208_DATA */ ++ 0x00000000 /* DENALI_CTL_209_DATA */ ++ 0x007fffff /* DENALI_CTL_210_DATA */ ++ 0x00000000 /* DENALI_CTL_211_DATA */ ++ 0x007fffff /* DENALI_CTL_212_DATA */ ++ 0x00000000 /* DENALI_CTL_213_DATA */ ++ 0x007fffff /* DENALI_CTL_214_DATA */ ++ 0x00000000 /* DENALI_CTL_215_DATA */ ++ 0x007fffff /* DENALI_CTL_216_DATA */ ++ 0x00000000 /* DENALI_CTL_217_DATA */ ++ 0x007fffff /* DENALI_CTL_218_DATA */ ++ 0x00000000 /* DENALI_CTL_219_DATA */ ++ 0x007fffff /* DENALI_CTL_220_DATA */ ++ 0x00000000 /* DENALI_CTL_221_DATA */ ++ 0x007fffff /* DENALI_CTL_222_DATA */ ++ 0x00000000 /* DENALI_CTL_223_DATA */ ++ 0x037fffff /* DENALI_CTL_224_DATA */ ++ 0xffffffff /* DENALI_CTL_225_DATA */ ++ 0x000f000f /* DENALI_CTL_226_DATA */ ++ 0x00ffff03 /* DENALI_CTL_227_DATA */ ++ 0x000fffff /* DENALI_CTL_228_DATA */ ++ 0x0003000f /* DENALI_CTL_229_DATA */ ++ 0xffffffff /* DENALI_CTL_230_DATA */ ++ 0x000f000f /* DENALI_CTL_231_DATA */ ++ 0x00ffff03 /* DENALI_CTL_232_DATA */ ++ 0x000fffff /* DENALI_CTL_233_DATA */ ++ 0x0003000f /* DENALI_CTL_234_DATA */ ++ 0xffffffff /* DENALI_CTL_235_DATA */ ++ 0x000f000f /* DENALI_CTL_236_DATA */ ++ 0x00ffff03 /* DENALI_CTL_237_DATA */ ++ 0x000fffff /* DENALI_CTL_238_DATA */ ++ 0x0003000f /* DENALI_CTL_239_DATA */ ++ 0xffffffff /* DENALI_CTL_240_DATA */ ++ 0x000f000f /* DENALI_CTL_241_DATA */ ++ 0x00ffff03 /* DENALI_CTL_242_DATA */ ++ 0x000fffff /* DENALI_CTL_243_DATA */ ++ 0x6407000f /* DENALI_CTL_244_DATA */ ++ 0x01640001 /* DENALI_CTL_245_DATA */ ++ 0x00000000 /* DENALI_CTL_246_DATA */ ++ 0x00000000 /* DENALI_CTL_247_DATA */ ++ 0x00001900 /* DENALI_CTL_248_DATA */ ++ 0x0040d205 /* DENALI_CTL_249_DATA */ ++ 0x02000200 /* DENALI_CTL_250_DATA */ ++ 0x02000200 /* DENALI_CTL_251_DATA */ ++ 0x000040d2 /* DENALI_CTL_252_DATA */ ++ 0x00028834 /* DENALI_CTL_253_DATA */ ++ 0x02020e11 /* DENALI_CTL_254_DATA */ ++ 0x00140303 /* DENALI_CTL_255_DATA */ ++ 0x00000000 /* DENALI_CTL_256_DATA */ ++ 0x00000000 /* DENALI_CTL_257_DATA */ ++ 0x00001403 /* DENALI_CTL_258_DATA */ ++ 0x00000000 /* DENALI_CTL_259_DATA */ ++ 0x00000000 /* DENALI_CTL_260_DATA */ ++ 0x00000000 /* DENALI_CTL_261_DATA */ ++ 0x00000000 /* DENALI_CTL_262_DATA */ ++ 0x0f010000 /* DENALI_CTL_263_DATA */ ++ 0x00000009 /* DENALI_CTL_264_DATA */ ++ 0x01375642 /* DENALI_PHY_00_DATA */ ++ 0x0004c008 /* DENALI_PHY_01_DATA */ ++ 0x00000120 /* DENALI_PHY_02_DATA */ ++ 0x00000000 /* DENALI_PHY_03_DATA */ ++ 0x00000000 /* DENALI_PHY_04_DATA */ ++ 0x00010000 /* DENALI_PHY_05_DATA */ ++ 0x01DDDD90 /* DENALI_PHY_06_DATA */ ++ 0x01DDDD90 /* DENALI_PHY_07_DATA */ ++ 0x01030000 /* DENALI_PHY_08_DATA */ ++ 0x01000000 /* DENALI_PHY_09_DATA */ ++ 0x00c00000 /* DENALI_PHY_10_DATA */ ++ 0x00000007 /* DENALI_PHY_11_DATA */ ++ 0x00000000 /* DENALI_PHY_12_DATA */ ++ 0x00000000 /* DENALI_PHY_13_DATA */ ++ 0x04000408 /* DENALI_PHY_14_DATA */ ++ 0x00000408 /* DENALI_PHY_15_DATA */ ++ 0x00e4e400 /* DENALI_PHY_16_DATA */ ++ 0x00000000 /* DENALI_PHY_17_DATA */ ++ 0x00000000 /* DENALI_PHY_18_DATA */ ++ 0x00000000 /* DENALI_PHY_19_DATA */ ++ 0x00000000 /* DENALI_PHY_20_DATA */ ++ 0x00000000 /* DENALI_PHY_21_DATA */ ++ 0x00000000 /* DENALI_PHY_22_DATA */ ++ 0x00000000 /* DENALI_PHY_23_DATA */ ++ 0x00000000 /* DENALI_PHY_24_DATA */ ++ 0x00000000 /* DENALI_PHY_25_DATA */ ++ 0x00000000 /* DENALI_PHY_26_DATA */ ++ 0x00000000 /* DENALI_PHY_27_DATA */ ++ 0x00000000 /* DENALI_PHY_28_DATA */ ++ 0x00000000 /* DENALI_PHY_29_DATA */ ++ 0x00000000 /* DENALI_PHY_30_DATA */ ++ 0x00000000 /* DENALI_PHY_31_DATA */ ++ 0x00000000 /* DENALI_PHY_32_DATA */ ++ 0x00200000 /* DENALI_PHY_33_DATA */ ++ 0x00000000 /* DENALI_PHY_34_DATA */ ++ 0x00000000 /* DENALI_PHY_35_DATA */ ++ 0x00000000 /* DENALI_PHY_36_DATA */ ++ 0x00000000 /* DENALI_PHY_37_DATA */ ++ 0x00000000 /* DENALI_PHY_38_DATA */ ++ 0x00000000 /* DENALI_PHY_39_DATA */ ++ 0x02800280 /* DENALI_PHY_40_DATA */ ++ 0x02800280 /* DENALI_PHY_41_DATA */ ++ 0x02800280 /* DENALI_PHY_42_DATA */ ++ 0x02800280 /* DENALI_PHY_43_DATA */ ++ 0x00000280 /* DENALI_PHY_44_DATA */ ++ 0x00000000 /* DENALI_PHY_45_DATA */ ++ 0x00000000 /* DENALI_PHY_46_DATA */ ++ 0x00000000 /* DENALI_PHY_47_DATA */ ++ 0x00000000 /* DENALI_PHY_48_DATA */ ++ 0x00000000 /* DENALI_PHY_49_DATA */ ++ 0x00800080 /* DENALI_PHY_50_DATA */ ++ 0x00800080 /* DENALI_PHY_51_DATA */ ++ 0x00800080 /* DENALI_PHY_52_DATA */ ++ 0x00800080 /* DENALI_PHY_53_DATA */ ++ 0x00800080 /* DENALI_PHY_54_DATA */ ++ 0x00800080 /* DENALI_PHY_55_DATA */ ++ 0x00800080 /* DENALI_PHY_56_DATA */ ++ 0x00800080 /* DENALI_PHY_57_DATA */ ++ 0x00800080 /* DENALI_PHY_58_DATA */ ++ 0x00010120 /* DENALI_PHY_59_DATA */ ++ 0x000001d0 /* DENALI_PHY_60_DATA */ ++ 0x01000000 /* DENALI_PHY_61_DATA */ ++ 0x00000000 /* DENALI_PHY_62_DATA */ ++ 0x00000002 /* DENALI_PHY_63_DATA */ ++ 0x51313152 /* DENALI_PHY_64_DATA */ ++ 0x80013130 /* DENALI_PHY_65_DATA */ ++ 0x03000080 /* DENALI_PHY_66_DATA */ ++ 0x00100002 /* DENALI_PHY_67_DATA */ ++ 0x0c064208 /* DENALI_PHY_68_DATA */ ++ 0x000f0c0f /* DENALI_PHY_69_DATA */ ++ 0x01000140 /* DENALI_PHY_70_DATA */ ++ 0x0000000c /* DENALI_PHY_71_DATA */ ++ 0x00000000 /* DENALI_PHY_72_DATA */ ++ 0x00000000 /* DENALI_PHY_73_DATA */ ++ 0x00000000 /* DENALI_PHY_74_DATA */ ++ 0x00000000 /* DENALI_PHY_75_DATA */ ++ 0x00000000 /* DENALI_PHY_76_DATA */ ++ 0x00000000 /* DENALI_PHY_77_DATA */ ++ 0x00000000 /* DENALI_PHY_78_DATA */ ++ 0x00000000 /* DENALI_PHY_79_DATA */ ++ 0x00000000 /* DENALI_PHY_80_DATA */ ++ 0x00000000 /* DENALI_PHY_81_DATA */ ++ 0x00000000 /* DENALI_PHY_82_DATA */ ++ 0x00000000 /* DENALI_PHY_83_DATA */ ++ 0x00000000 /* DENALI_PHY_84_DATA */ ++ 0x00000000 /* DENALI_PHY_85_DATA */ ++ 0x00000000 /* DENALI_PHY_86_DATA */ ++ 0x00000000 /* DENALI_PHY_87_DATA */ ++ 0x00000000 /* DENALI_PHY_88_DATA */ ++ 0x00000000 /* DENALI_PHY_89_DATA */ ++ 0x00000000 /* DENALI_PHY_90_DATA */ ++ 0x00000000 /* DENALI_PHY_91_DATA */ ++ 0x00000000 /* DENALI_PHY_92_DATA */ ++ 0x00000000 /* DENALI_PHY_93_DATA */ ++ 0x00000000 /* DENALI_PHY_94_DATA */ ++ 0x00000000 /* DENALI_PHY_95_DATA */ ++ 0x00000000 /* DENALI_PHY_96_DATA */ ++ 0x00000000 /* DENALI_PHY_97_DATA */ ++ 0x00000000 /* DENALI_PHY_98_DATA */ ++ 0x00000000 /* DENALI_PHY_99_DATA */ ++ 0x00000000 /* DENALI_PHY_100_DATA */ ++ 0x00000000 /* DENALI_PHY_101_DATA */ ++ 0x00000000 /* DENALI_PHY_102_DATA */ ++ 0x00000000 /* DENALI_PHY_103_DATA */ ++ 0x00000000 /* DENALI_PHY_104_DATA */ ++ 0x00000000 /* DENALI_PHY_105_DATA */ ++ 0x00000000 /* DENALI_PHY_106_DATA */ ++ 0x00000000 /* DENALI_PHY_107_DATA */ ++ 0x00000000 /* DENALI_PHY_108_DATA */ ++ 0x00000000 /* DENALI_PHY_109_DATA */ ++ 0x00000000 /* DENALI_PHY_110_DATA */ ++ 0x00000000 /* DENALI_PHY_111_DATA */ ++ 0x00000000 /* DENALI_PHY_112_DATA */ ++ 0x00000000 /* DENALI_PHY_113_DATA */ ++ 0x00000000 /* DENALI_PHY_114_DATA */ ++ 0x00000000 /* DENALI_PHY_115_DATA */ ++ 0x00000000 /* DENALI_PHY_116_DATA */ ++ 0x00000000 /* DENALI_PHY_117_DATA */ ++ 0x00000000 /* DENALI_PHY_118_DATA */ ++ 0x00000000 /* DENALI_PHY_119_DATA */ ++ 0x00000000 /* DENALI_PHY_120_DATA */ ++ 0x00000000 /* DENALI_PHY_121_DATA */ ++ 0x00000000 /* DENALI_PHY_122_DATA */ ++ 0x00000000 /* DENALI_PHY_123_DATA */ ++ 0x00000000 /* DENALI_PHY_124_DATA */ ++ 0x00000000 /* DENALI_PHY_125_DATA */ ++ 0x00000000 /* DENALI_PHY_126_DATA */ ++ 0x00000000 /* DENALI_PHY_127_DATA */ ++ 0x40263571 /* DENALI_PHY_128_DATA */ ++ 0x0004c008 /* DENALI_PHY_129_DATA */ ++ 0x00000120 /* DENALI_PHY_130_DATA */ ++ 0x00000000 /* DENALI_PHY_131_DATA */ ++ 0x00000000 /* DENALI_PHY_132_DATA */ ++ 0x00010000 /* DENALI_PHY_133_DATA */ ++ 0x01DDDD90 /* DENALI_PHY_134_DATA */ ++ 0x01DDDD90 /* DENALI_PHY_135_DATA */ ++ 0x01030000 /* DENALI_PHY_136_DATA */ ++ 0x01000000 /* DENALI_PHY_137_DATA */ ++ 0x00c00000 /* DENALI_PHY_138_DATA */ ++ 0x00000007 /* DENALI_PHY_139_DATA */ ++ 0x00000000 /* DENALI_PHY_140_DATA */ ++ 0x00000000 /* DENALI_PHY_141_DATA */ ++ 0x04000408 /* DENALI_PHY_142_DATA */ ++ 0x00000408 /* DENALI_PHY_143_DATA */ ++ 0x00e4e400 /* DENALI_PHY_144_DATA */ ++ 0x00000000 /* DENALI_PHY_145_DATA */ ++ 0x00000000 /* DENALI_PHY_146_DATA */ ++ 0x00000000 /* DENALI_PHY_147_DATA */ ++ 0x00000000 /* DENALI_PHY_148_DATA */ ++ 0x00000000 /* DENALI_PHY_149_DATA */ ++ 0x00000000 /* DENALI_PHY_150_DATA */ ++ 0x00000000 /* DENALI_PHY_151_DATA */ ++ 0x00000000 /* DENALI_PHY_152_DATA */ ++ 0x00000000 /* DENALI_PHY_153_DATA */ ++ 0x00000000 /* DENALI_PHY_154_DATA */ ++ 0x00000000 /* DENALI_PHY_155_DATA */ ++ 0x00000000 /* DENALI_PHY_156_DATA */ ++ 0x00000000 /* DENALI_PHY_157_DATA */ ++ 0x00000000 /* DENALI_PHY_158_DATA */ ++ 0x00000000 /* DENALI_PHY_159_DATA */ ++ 0x00000000 /* DENALI_PHY_160_DATA */ ++ 0x00200000 /* DENALI_PHY_161_DATA */ ++ 0x00000000 /* DENALI_PHY_162_DATA */ ++ 0x00000000 /* DENALI_PHY_163_DATA */ ++ 0x00000000 /* DENALI_PHY_164_DATA */ ++ 0x00000000 /* DENALI_PHY_165_DATA */ ++ 0x00000000 /* DENALI_PHY_166_DATA */ ++ 0x00000000 /* DENALI_PHY_167_DATA */ ++ 0x02800280 /* DENALI_PHY_168_DATA */ ++ 0x02800280 /* DENALI_PHY_169_DATA */ ++ 0x02800280 /* DENALI_PHY_170_DATA */ ++ 0x02800280 /* DENALI_PHY_171_DATA */ ++ 0x00000280 /* DENALI_PHY_172_DATA */ ++ 0x00000000 /* DENALI_PHY_173_DATA */ ++ 0x00000000 /* DENALI_PHY_174_DATA */ ++ 0x00000000 /* DENALI_PHY_175_DATA */ ++ 0x00000000 /* DENALI_PHY_176_DATA */ ++ 0x00000000 /* DENALI_PHY_177_DATA */ ++ 0x00800080 /* DENALI_PHY_178_DATA */ ++ 0x00800080 /* DENALI_PHY_179_DATA */ ++ 0x00800080 /* DENALI_PHY_180_DATA */ ++ 0x00800080 /* DENALI_PHY_181_DATA */ ++ 0x00800080 /* DENALI_PHY_182_DATA */ ++ 0x00800080 /* DENALI_PHY_183_DATA */ ++ 0x00800080 /* DENALI_PHY_184_DATA */ ++ 0x00800080 /* DENALI_PHY_185_DATA */ ++ 0x00800080 /* DENALI_PHY_186_DATA */ ++ 0x00010120 /* DENALI_PHY_187_DATA */ ++ 0x000001d0 /* DENALI_PHY_188_DATA */ ++ 0x01000000 /* DENALI_PHY_189_DATA */ ++ 0x00000000 /* DENALI_PHY_190_DATA */ ++ 0x00000002 /* DENALI_PHY_191_DATA */ ++ 0x51313152 /* DENALI_PHY_192_DATA */ ++ 0x80013130 /* DENALI_PHY_193_DATA */ ++ 0x03000080 /* DENALI_PHY_194_DATA */ ++ 0x00100002 /* DENALI_PHY_195_DATA */ ++ 0x0c064208 /* DENALI_PHY_196_DATA */ ++ 0x000f0c0f /* DENALI_PHY_197_DATA */ ++ 0x01000140 /* DENALI_PHY_198_DATA */ ++ 0x0000000c /* DENALI_PHY_199_DATA */ ++ 0x00000000 /* DENALI_PHY_200_DATA */ ++ 0x00000000 /* DENALI_PHY_201_DATA */ ++ 0x00000000 /* DENALI_PHY_202_DATA */ ++ 0x00000000 /* DENALI_PHY_203_DATA */ ++ 0x00000000 /* DENALI_PHY_204_DATA */ ++ 0x00000000 /* DENALI_PHY_205_DATA */ ++ 0x00000000 /* DENALI_PHY_206_DATA */ ++ 0x00000000 /* DENALI_PHY_207_DATA */ ++ 0x00000000 /* DENALI_PHY_208_DATA */ ++ 0x00000000 /* DENALI_PHY_209_DATA */ ++ 0x00000000 /* DENALI_PHY_210_DATA */ ++ 0x00000000 /* DENALI_PHY_211_DATA */ ++ 0x00000000 /* DENALI_PHY_212_DATA */ ++ 0x00000000 /* DENALI_PHY_213_DATA */ ++ 0x00000000 /* DENALI_PHY_214_DATA */ ++ 0x00000000 /* DENALI_PHY_215_DATA */ ++ 0x00000000 /* DENALI_PHY_216_DATA */ ++ 0x00000000 /* DENALI_PHY_217_DATA */ ++ 0x00000000 /* DENALI_PHY_218_DATA */ ++ 0x00000000 /* DENALI_PHY_219_DATA */ ++ 0x00000000 /* DENALI_PHY_220_DATA */ ++ 0x00000000 /* DENALI_PHY_221_DATA */ ++ 0x00000000 /* DENALI_PHY_222_DATA */ ++ 0x00000000 /* DENALI_PHY_223_DATA */ ++ 0x00000000 /* DENALI_PHY_224_DATA */ ++ 0x00000000 /* DENALI_PHY_225_DATA */ ++ 0x00000000 /* DENALI_PHY_226_DATA */ ++ 0x00000000 /* DENALI_PHY_227_DATA */ ++ 0x00000000 /* DENALI_PHY_228_DATA */ ++ 0x00000000 /* DENALI_PHY_229_DATA */ ++ 0x00000000 /* DENALI_PHY_230_DATA */ ++ 0x00000000 /* DENALI_PHY_231_DATA */ ++ 0x00000000 /* DENALI_PHY_232_DATA */ ++ 0x00000000 /* DENALI_PHY_233_DATA */ ++ 0x00000000 /* DENALI_PHY_234_DATA */ ++ 0x00000000 /* DENALI_PHY_235_DATA */ ++ 0x00000000 /* DENALI_PHY_236_DATA */ ++ 0x00000000 /* DENALI_PHY_237_DATA */ ++ 0x00000000 /* DENALI_PHY_238_DATA */ ++ 0x00000000 /* DENALI_PHY_239_DATA */ ++ 0x00000000 /* DENALI_PHY_240_DATA */ ++ 0x00000000 /* DENALI_PHY_241_DATA */ ++ 0x00000000 /* DENALI_PHY_242_DATA */ ++ 0x00000000 /* DENALI_PHY_243_DATA */ ++ 0x00000000 /* DENALI_PHY_244_DATA */ ++ 0x00000000 /* DENALI_PHY_245_DATA */ ++ 0x00000000 /* DENALI_PHY_246_DATA */ ++ 0x00000000 /* DENALI_PHY_247_DATA */ ++ 0x00000000 /* DENALI_PHY_248_DATA */ ++ 0x00000000 /* DENALI_PHY_249_DATA */ ++ 0x00000000 /* DENALI_PHY_250_DATA */ ++ 0x00000000 /* DENALI_PHY_251_DATA */ ++ 0x00000000 /* DENALI_PHY_252_DATA */ ++ 0x00000000 /* DENALI_PHY_253_DATA */ ++ 0x00000000 /* DENALI_PHY_254_DATA */ ++ 0x00000000 /* DENALI_PHY_255_DATA */ ++ 0x46052371 /* DENALI_PHY_256_DATA */ ++ 0x0004c008 /* DENALI_PHY_257_DATA */ ++ 0x00000120 /* DENALI_PHY_258_DATA */ ++ 0x00000000 /* DENALI_PHY_259_DATA */ ++ 0x00000000 /* DENALI_PHY_260_DATA */ ++ 0x00010000 /* DENALI_PHY_261_DATA */ ++ 0x01DDDD90 /* DENALI_PHY_262_DATA */ ++ 0x01DDDD90 /* DENALI_PHY_263_DATA */ ++ 0x01030000 /* DENALI_PHY_264_DATA */ ++ 0x01000000 /* DENALI_PHY_265_DATA */ ++ 0x00c00000 /* DENALI_PHY_266_DATA */ ++ 0x00000007 /* DENALI_PHY_267_DATA */ ++ 0x00000000 /* DENALI_PHY_268_DATA */ ++ 0x00000000 /* DENALI_PHY_269_DATA */ ++ 0x04000408 /* DENALI_PHY_270_DATA */ ++ 0x00000408 /* DENALI_PHY_271_DATA */ ++ 0x00e4e400 /* DENALI_PHY_272_DATA */ ++ 0x00000000 /* DENALI_PHY_273_DATA */ ++ 0x00000000 /* DENALI_PHY_274_DATA */ ++ 0x00000000 /* DENALI_PHY_275_DATA */ ++ 0x00000000 /* DENALI_PHY_276_DATA */ ++ 0x00000000 /* DENALI_PHY_277_DATA */ ++ 0x00000000 /* DENALI_PHY_278_DATA */ ++ 0x00000000 /* DENALI_PHY_279_DATA */ ++ 0x00000000 /* DENALI_PHY_280_DATA */ ++ 0x00000000 /* DENALI_PHY_281_DATA */ ++ 0x00000000 /* DENALI_PHY_282_DATA */ ++ 0x00000000 /* DENALI_PHY_283_DATA */ ++ 0x00000000 /* DENALI_PHY_284_DATA */ ++ 0x00000000 /* DENALI_PHY_285_DATA */ ++ 0x00000000 /* DENALI_PHY_286_DATA */ ++ 0x00000000 /* DENALI_PHY_287_DATA */ ++ 0x00000000 /* DENALI_PHY_288_DATA */ ++ 0x00200000 /* DENALI_PHY_289_DATA */ ++ 0x00000000 /* DENALI_PHY_290_DATA */ ++ 0x00000000 /* DENALI_PHY_291_DATA */ ++ 0x00000000 /* DENALI_PHY_292_DATA */ ++ 0x00000000 /* DENALI_PHY_293_DATA */ ++ 0x00000000 /* DENALI_PHY_294_DATA */ ++ 0x00000000 /* DENALI_PHY_295_DATA */ ++ 0x02800280 /* DENALI_PHY_296_DATA */ ++ 0x02800280 /* DENALI_PHY_297_DATA */ ++ 0x02800280 /* DENALI_PHY_298_DATA */ ++ 0x02800280 /* DENALI_PHY_299_DATA */ ++ 0x00000280 /* DENALI_PHY_300_DATA */ ++ 0x00000000 /* DENALI_PHY_301_DATA */ ++ 0x00000000 /* DENALI_PHY_302_DATA */ ++ 0x00000000 /* DENALI_PHY_303_DATA */ ++ 0x00000000 /* DENALI_PHY_304_DATA */ ++ 0x00000000 /* DENALI_PHY_305_DATA */ ++ 0x00800080 /* DENALI_PHY_306_DATA */ ++ 0x00800080 /* DENALI_PHY_307_DATA */ ++ 0x00800080 /* DENALI_PHY_308_DATA */ ++ 0x00800080 /* DENALI_PHY_309_DATA */ ++ 0x00800080 /* DENALI_PHY_310_DATA */ ++ 0x00800080 /* DENALI_PHY_311_DATA */ ++ 0x00800080 /* DENALI_PHY_312_DATA */ ++ 0x00800080 /* DENALI_PHY_313_DATA */ ++ 0x00800080 /* DENALI_PHY_314_DATA */ ++ 0x00010120 /* DENALI_PHY_315_DATA */ ++ 0x000001d0 /* DENALI_PHY_316_DATA */ ++ 0x01000000 /* DENALI_PHY_317_DATA */ ++ 0x00000000 /* DENALI_PHY_318_DATA */ ++ 0x00000002 /* DENALI_PHY_319_DATA */ ++ 0x51313152 /* DENALI_PHY_320_DATA */ ++ 0x80013130 /* DENALI_PHY_321_DATA */ ++ 0x03000080 /* DENALI_PHY_322_DATA */ ++ 0x00100002 /* DENALI_PHY_323_DATA */ ++ 0x0c064208 /* DENALI_PHY_324_DATA */ ++ 0x000f0c0f /* DENALI_PHY_325_DATA */ ++ 0x01000140 /* DENALI_PHY_326_DATA */ ++ 0x0000000c /* DENALI_PHY_327_DATA */ ++ 0x00000000 /* DENALI_PHY_328_DATA */ ++ 0x00000000 /* DENALI_PHY_329_DATA */ ++ 0x00000000 /* DENALI_PHY_330_DATA */ ++ 0x00000000 /* DENALI_PHY_331_DATA */ ++ 0x00000000 /* DENALI_PHY_332_DATA */ ++ 0x00000000 /* DENALI_PHY_333_DATA */ ++ 0x00000000 /* DENALI_PHY_334_DATA */ ++ 0x00000000 /* DENALI_PHY_335_DATA */ ++ 0x00000000 /* DENALI_PHY_336_DATA */ ++ 0x00000000 /* DENALI_PHY_337_DATA */ ++ 0x00000000 /* DENALI_PHY_338_DATA */ ++ 0x00000000 /* DENALI_PHY_339_DATA */ ++ 0x00000000 /* DENALI_PHY_340_DATA */ ++ 0x00000000 /* DENALI_PHY_341_DATA */ ++ 0x00000000 /* DENALI_PHY_342_DATA */ ++ 0x00000000 /* DENALI_PHY_343_DATA */ ++ 0x00000000 /* DENALI_PHY_344_DATA */ ++ 0x00000000 /* DENALI_PHY_345_DATA */ ++ 0x00000000 /* DENALI_PHY_346_DATA */ ++ 0x00000000 /* DENALI_PHY_347_DATA */ ++ 0x00000000 /* DENALI_PHY_348_DATA */ ++ 0x00000000 /* DENALI_PHY_349_DATA */ ++ 0x00000000 /* DENALI_PHY_350_DATA */ ++ 0x00000000 /* DENALI_PHY_351_DATA */ ++ 0x00000000 /* DENALI_PHY_352_DATA */ ++ 0x00000000 /* DENALI_PHY_353_DATA */ ++ 0x00000000 /* DENALI_PHY_354_DATA */ ++ 0x00000000 /* DENALI_PHY_355_DATA */ ++ 0x00000000 /* DENALI_PHY_356_DATA */ ++ 0x00000000 /* DENALI_PHY_357_DATA */ ++ 0x00000000 /* DENALI_PHY_358_DATA */ ++ 0x00000000 /* DENALI_PHY_359_DATA */ ++ 0x00000000 /* DENALI_PHY_360_DATA */ ++ 0x00000000 /* DENALI_PHY_361_DATA */ ++ 0x00000000 /* DENALI_PHY_362_DATA */ ++ 0x00000000 /* DENALI_PHY_363_DATA */ ++ 0x00000000 /* DENALI_PHY_364_DATA */ ++ 0x00000000 /* DENALI_PHY_365_DATA */ ++ 0x00000000 /* DENALI_PHY_366_DATA */ ++ 0x00000000 /* DENALI_PHY_367_DATA */ ++ 0x00000000 /* DENALI_PHY_368_DATA */ ++ 0x00000000 /* DENALI_PHY_369_DATA */ ++ 0x00000000 /* DENALI_PHY_370_DATA */ ++ 0x00000000 /* DENALI_PHY_371_DATA */ ++ 0x00000000 /* DENALI_PHY_372_DATA */ ++ 0x00000000 /* DENALI_PHY_373_DATA */ ++ 0x00000000 /* DENALI_PHY_374_DATA */ ++ 0x00000000 /* DENALI_PHY_375_DATA */ ++ 0x00000000 /* DENALI_PHY_376_DATA */ ++ 0x00000000 /* DENALI_PHY_377_DATA */ ++ 0x00000000 /* DENALI_PHY_378_DATA */ ++ 0x00000000 /* DENALI_PHY_379_DATA */ ++ 0x00000000 /* DENALI_PHY_380_DATA */ ++ 0x00000000 /* DENALI_PHY_381_DATA */ ++ 0x00000000 /* DENALI_PHY_382_DATA */ ++ 0x00000000 /* DENALI_PHY_383_DATA */ ++ 0x37651240 /* DENALI_PHY_384_DATA */ ++ 0x0004c008 /* DENALI_PHY_385_DATA */ ++ 0x00000120 /* DENALI_PHY_386_DATA */ ++ 0x00000000 /* DENALI_PHY_387_DATA */ ++ 0x00000000 /* DENALI_PHY_388_DATA */ ++ 0x00010000 /* DENALI_PHY_389_DATA */ ++ 0x01DDDD90 /* DENALI_PHY_390_DATA */ ++ 0x01DDDD90 /* DENALI_PHY_391_DATA */ ++ 0x01030000 /* DENALI_PHY_392_DATA */ ++ 0x01000000 /* DENALI_PHY_393_DATA */ ++ 0x00c00000 /* DENALI_PHY_394_DATA */ ++ 0x00000007 /* DENALI_PHY_395_DATA */ ++ 0x00000000 /* DENALI_PHY_396_DATA */ ++ 0x00000000 /* DENALI_PHY_397_DATA */ ++ 0x04000408 /* DENALI_PHY_398_DATA */ ++ 0x00000408 /* DENALI_PHY_399_DATA */ ++ 0x00e4e400 /* DENALI_PHY_400_DATA */ ++ 0x00000000 /* DENALI_PHY_401_DATA */ ++ 0x00000000 /* DENALI_PHY_402_DATA */ ++ 0x00000000 /* DENALI_PHY_403_DATA */ ++ 0x00000000 /* DENALI_PHY_404_DATA */ ++ 0x00000000 /* DENALI_PHY_405_DATA */ ++ 0x00000000 /* DENALI_PHY_406_DATA */ ++ 0x00000000 /* DENALI_PHY_407_DATA */ ++ 0x00000000 /* DENALI_PHY_408_DATA */ ++ 0x00000000 /* DENALI_PHY_409_DATA */ ++ 0x00000000 /* DENALI_PHY_410_DATA */ ++ 0x00000000 /* DENALI_PHY_411_DATA */ ++ 0x00000000 /* DENALI_PHY_412_DATA */ ++ 0x00000000 /* DENALI_PHY_413_DATA */ ++ 0x00000000 /* DENALI_PHY_414_DATA */ ++ 0x00000000 /* DENALI_PHY_415_DATA */ ++ 0x00000000 /* DENALI_PHY_416_DATA */ ++ 0x00200000 /* DENALI_PHY_417_DATA */ ++ 0x00000000 /* DENALI_PHY_418_DATA */ ++ 0x00000000 /* DENALI_PHY_419_DATA */ ++ 0x00000000 /* DENALI_PHY_420_DATA */ ++ 0x00000000 /* DENALI_PHY_421_DATA */ ++ 0x00000000 /* DENALI_PHY_422_DATA */ ++ 0x00000000 /* DENALI_PHY_423_DATA */ ++ 0x02800280 /* DENALI_PHY_424_DATA */ ++ 0x02800280 /* DENALI_PHY_425_DATA */ ++ 0x02800280 /* DENALI_PHY_426_DATA */ ++ 0x02800280 /* DENALI_PHY_427_DATA */ ++ 0x00000280 /* DENALI_PHY_428_DATA */ ++ 0x00000000 /* DENALI_PHY_429_DATA */ ++ 0x00000000 /* DENALI_PHY_430_DATA */ ++ 0x00000000 /* DENALI_PHY_431_DATA */ ++ 0x00000000 /* DENALI_PHY_432_DATA */ ++ 0x00000000 /* DENALI_PHY_433_DATA */ ++ 0x00800080 /* DENALI_PHY_434_DATA */ ++ 0x00800080 /* DENALI_PHY_435_DATA */ ++ 0x00800080 /* DENALI_PHY_436_DATA */ ++ 0x00800080 /* DENALI_PHY_437_DATA */ ++ 0x00800080 /* DENALI_PHY_438_DATA */ ++ 0x00800080 /* DENALI_PHY_439_DATA */ ++ 0x00800080 /* DENALI_PHY_440_DATA */ ++ 0x00800080 /* DENALI_PHY_441_DATA */ ++ 0x00800080 /* DENALI_PHY_442_DATA */ ++ 0x00010120 /* DENALI_PHY_443_DATA */ ++ 0x000001d0 /* DENALI_PHY_444_DATA */ ++ 0x01000000 /* DENALI_PHY_445_DATA */ ++ 0x00000000 /* DENALI_PHY_446_DATA */ ++ 0x00000002 /* DENALI_PHY_447_DATA */ ++ 0x51313152 /* DENALI_PHY_448_DATA */ ++ 0x80013130 /* DENALI_PHY_449_DATA */ ++ 0x03000080 /* DENALI_PHY_450_DATA */ ++ 0x00100002 /* DENALI_PHY_451_DATA */ ++ 0x0c064208 /* DENALI_PHY_452_DATA */ ++ 0x000f0c0f /* DENALI_PHY_453_DATA */ ++ 0x01000140 /* DENALI_PHY_454_DATA */ ++ 0x0000000c /* DENALI_PHY_455_DATA */ ++ 0x00000000 /* DENALI_PHY_456_DATA */ ++ 0x00000000 /* DENALI_PHY_457_DATA */ ++ 0x00000000 /* DENALI_PHY_458_DATA */ ++ 0x00000000 /* DENALI_PHY_459_DATA */ ++ 0x00000000 /* DENALI_PHY_460_DATA */ ++ 0x00000000 /* DENALI_PHY_461_DATA */ ++ 0x00000000 /* DENALI_PHY_462_DATA */ ++ 0x00000000 /* DENALI_PHY_463_DATA */ ++ 0x00000000 /* DENALI_PHY_464_DATA */ ++ 0x00000000 /* DENALI_PHY_465_DATA */ ++ 0x00000000 /* DENALI_PHY_466_DATA */ ++ 0x00000000 /* DENALI_PHY_467_DATA */ ++ 0x00000000 /* DENALI_PHY_468_DATA */ ++ 0x00000000 /* DENALI_PHY_469_DATA */ ++ 0x00000000 /* DENALI_PHY_470_DATA */ ++ 0x00000000 /* DENALI_PHY_471_DATA */ ++ 0x00000000 /* DENALI_PHY_472_DATA */ ++ 0x00000000 /* DENALI_PHY_473_DATA */ ++ 0x00000000 /* DENALI_PHY_474_DATA */ ++ 0x00000000 /* DENALI_PHY_475_DATA */ ++ 0x00000000 /* DENALI_PHY_476_DATA */ ++ 0x00000000 /* DENALI_PHY_477_DATA */ ++ 0x00000000 /* DENALI_PHY_478_DATA */ ++ 0x00000000 /* DENALI_PHY_479_DATA */ ++ 0x00000000 /* DENALI_PHY_480_DATA */ ++ 0x00000000 /* DENALI_PHY_481_DATA */ ++ 0x00000000 /* DENALI_PHY_482_DATA */ ++ 0x00000000 /* DENALI_PHY_483_DATA */ ++ 0x00000000 /* DENALI_PHY_484_DATA */ ++ 0x00000000 /* DENALI_PHY_485_DATA */ ++ 0x00000000 /* DENALI_PHY_486_DATA */ ++ 0x00000000 /* DENALI_PHY_487_DATA */ ++ 0x00000000 /* DENALI_PHY_488_DATA */ ++ 0x00000000 /* DENALI_PHY_489_DATA */ ++ 0x00000000 /* DENALI_PHY_490_DATA */ ++ 0x00000000 /* DENALI_PHY_491_DATA */ ++ 0x00000000 /* DENALI_PHY_492_DATA */ ++ 0x00000000 /* DENALI_PHY_493_DATA */ ++ 0x00000000 /* DENALI_PHY_494_DATA */ ++ 0x00000000 /* DENALI_PHY_495_DATA */ ++ 0x00000000 /* DENALI_PHY_496_DATA */ ++ 0x00000000 /* DENALI_PHY_497_DATA */ ++ 0x00000000 /* DENALI_PHY_498_DATA */ ++ 0x00000000 /* DENALI_PHY_499_DATA */ ++ 0x00000000 /* DENALI_PHY_500_DATA */ ++ 0x00000000 /* DENALI_PHY_501_DATA */ ++ 0x00000000 /* DENALI_PHY_502_DATA */ ++ 0x00000000 /* DENALI_PHY_503_DATA */ ++ 0x00000000 /* DENALI_PHY_504_DATA */ ++ 0x00000000 /* DENALI_PHY_505_DATA */ ++ 0x00000000 /* DENALI_PHY_506_DATA */ ++ 0x00000000 /* DENALI_PHY_507_DATA */ ++ 0x00000000 /* DENALI_PHY_508_DATA */ ++ 0x00000000 /* DENALI_PHY_509_DATA */ ++ 0x00000000 /* DENALI_PHY_510_DATA */ ++ 0x00000000 /* DENALI_PHY_511_DATA */ ++ 0x34216750 /* DENALI_PHY_512_DATA */ ++ 0x0004c008 /* DENALI_PHY_513_DATA */ ++ 0x00000120 /* DENALI_PHY_514_DATA */ ++ 0x00000000 /* DENALI_PHY_515_DATA */ ++ 0x00000000 /* DENALI_PHY_516_DATA */ ++ 0x00010000 /* DENALI_PHY_517_DATA */ ++ 0x01DDDD90 /* DENALI_PHY_518_DATA */ ++ 0x01DDDD90 /* DENALI_PHY_519_DATA */ ++ 0x01030000 /* DENALI_PHY_520_DATA */ ++ 0x01000000 /* DENALI_PHY_521_DATA */ ++ 0x00c00000 /* DENALI_PHY_522_DATA */ ++ 0x00000007 /* DENALI_PHY_523_DATA */ ++ 0x00000000 /* DENALI_PHY_524_DATA */ ++ 0x00000000 /* DENALI_PHY_525_DATA */ ++ 0x04000408 /* DENALI_PHY_526_DATA */ ++ 0x00000408 /* DENALI_PHY_527_DATA */ ++ 0x00e4e400 /* DENALI_PHY_528_DATA */ ++ 0x00000000 /* DENALI_PHY_529_DATA */ ++ 0x00000000 /* DENALI_PHY_530_DATA */ ++ 0x00000000 /* DENALI_PHY_531_DATA */ ++ 0x00000000 /* DENALI_PHY_532_DATA */ ++ 0x00000000 /* DENALI_PHY_533_DATA */ ++ 0x00000000 /* DENALI_PHY_534_DATA */ ++ 0x00000000 /* DENALI_PHY_535_DATA */ ++ 0x00000000 /* DENALI_PHY_536_DATA */ ++ 0x00000000 /* DENALI_PHY_537_DATA */ ++ 0x00000000 /* DENALI_PHY_538_DATA */ ++ 0x00000000 /* DENALI_PHY_539_DATA */ ++ 0x00000000 /* DENALI_PHY_540_DATA */ ++ 0x00000000 /* DENALI_PHY_541_DATA */ ++ 0x00000000 /* DENALI_PHY_542_DATA */ ++ 0x00000000 /* DENALI_PHY_543_DATA */ ++ 0x00000000 /* DENALI_PHY_544_DATA */ ++ 0x00200000 /* DENALI_PHY_545_DATA */ ++ 0x00000000 /* DENALI_PHY_546_DATA */ ++ 0x00000000 /* DENALI_PHY_547_DATA */ ++ 0x00000000 /* DENALI_PHY_548_DATA */ ++ 0x00000000 /* DENALI_PHY_549_DATA */ ++ 0x00000000 /* DENALI_PHY_550_DATA */ ++ 0x00000000 /* DENALI_PHY_551_DATA */ ++ 0x02800280 /* DENALI_PHY_552_DATA */ ++ 0x02800280 /* DENALI_PHY_553_DATA */ ++ 0x02800280 /* DENALI_PHY_554_DATA */ ++ 0x02800280 /* DENALI_PHY_555_DATA */ ++ 0x00000280 /* DENALI_PHY_556_DATA */ ++ 0x00000000 /* DENALI_PHY_557_DATA */ ++ 0x00000000 /* DENALI_PHY_558_DATA */ ++ 0x00000000 /* DENALI_PHY_559_DATA */ ++ 0x00000000 /* DENALI_PHY_560_DATA */ ++ 0x00000000 /* DENALI_PHY_561_DATA */ ++ 0x00800080 /* DENALI_PHY_562_DATA */ ++ 0x00800080 /* DENALI_PHY_563_DATA */ ++ 0x00800080 /* DENALI_PHY_564_DATA */ ++ 0x00800080 /* DENALI_PHY_565_DATA */ ++ 0x00800080 /* DENALI_PHY_566_DATA */ ++ 0x00800080 /* DENALI_PHY_567_DATA */ ++ 0x00800080 /* DENALI_PHY_568_DATA */ ++ 0x00800080 /* DENALI_PHY_569_DATA */ ++ 0x00800080 /* DENALI_PHY_570_DATA */ ++ 0x00010120 /* DENALI_PHY_571_DATA */ ++ 0x000001d0 /* DENALI_PHY_572_DATA */ ++ 0x01000000 /* DENALI_PHY_573_DATA */ ++ 0x00000000 /* DENALI_PHY_574_DATA */ ++ 0x00000002 /* DENALI_PHY_575_DATA */ ++ 0x51313152 /* DENALI_PHY_576_DATA */ ++ 0x80013130 /* DENALI_PHY_577_DATA */ ++ 0x03000080 /* DENALI_PHY_578_DATA */ ++ 0x00100002 /* DENALI_PHY_579_DATA */ ++ 0x0c064208 /* DENALI_PHY_580_DATA */ ++ 0x000f0c0f /* DENALI_PHY_581_DATA */ ++ 0x01000140 /* DENALI_PHY_582_DATA */ ++ 0x0000000c /* DENALI_PHY_583_DATA */ ++ 0x00000000 /* DENALI_PHY_584_DATA */ ++ 0x00000000 /* DENALI_PHY_585_DATA */ ++ 0x00000000 /* DENALI_PHY_586_DATA */ ++ 0x00000000 /* DENALI_PHY_587_DATA */ ++ 0x00000000 /* DENALI_PHY_588_DATA */ ++ 0x00000000 /* DENALI_PHY_589_DATA */ ++ 0x00000000 /* DENALI_PHY_590_DATA */ ++ 0x00000000 /* DENALI_PHY_591_DATA */ ++ 0x00000000 /* DENALI_PHY_592_DATA */ ++ 0x00000000 /* DENALI_PHY_593_DATA */ ++ 0x00000000 /* DENALI_PHY_594_DATA */ ++ 0x00000000 /* DENALI_PHY_595_DATA */ ++ 0x00000000 /* DENALI_PHY_596_DATA */ ++ 0x00000000 /* DENALI_PHY_597_DATA */ ++ 0x00000000 /* DENALI_PHY_598_DATA */ ++ 0x00000000 /* DENALI_PHY_599_DATA */ ++ 0x00000000 /* DENALI_PHY_600_DATA */ ++ 0x00000000 /* DENALI_PHY_601_DATA */ ++ 0x00000000 /* DENALI_PHY_602_DATA */ ++ 0x00000000 /* DENALI_PHY_603_DATA */ ++ 0x00000000 /* DENALI_PHY_604_DATA */ ++ 0x00000000 /* DENALI_PHY_605_DATA */ ++ 0x00000000 /* DENALI_PHY_606_DATA */ ++ 0x00000000 /* DENALI_PHY_607_DATA */ ++ 0x00000000 /* DENALI_PHY_608_DATA */ ++ 0x00000000 /* DENALI_PHY_609_DATA */ ++ 0x00000000 /* DENALI_PHY_610_DATA */ ++ 0x00000000 /* DENALI_PHY_611_DATA */ ++ 0x00000000 /* DENALI_PHY_612_DATA */ ++ 0x00000000 /* DENALI_PHY_613_DATA */ ++ 0x00000000 /* DENALI_PHY_614_DATA */ ++ 0x00000000 /* DENALI_PHY_615_DATA */ ++ 0x00000000 /* DENALI_PHY_616_DATA */ ++ 0x00000000 /* DENALI_PHY_617_DATA */ ++ 0x00000000 /* DENALI_PHY_618_DATA */ ++ 0x00000000 /* DENALI_PHY_619_DATA */ ++ 0x00000000 /* DENALI_PHY_620_DATA */ ++ 0x00000000 /* DENALI_PHY_621_DATA */ ++ 0x00000000 /* DENALI_PHY_622_DATA */ ++ 0x00000000 /* DENALI_PHY_623_DATA */ ++ 0x00000000 /* DENALI_PHY_624_DATA */ ++ 0x00000000 /* DENALI_PHY_625_DATA */ ++ 0x00000000 /* DENALI_PHY_626_DATA */ ++ 0x00000000 /* DENALI_PHY_627_DATA */ ++ 0x00000000 /* DENALI_PHY_628_DATA */ ++ 0x00000000 /* DENALI_PHY_629_DATA */ ++ 0x00000000 /* DENALI_PHY_630_DATA */ ++ 0x00000000 /* DENALI_PHY_631_DATA */ ++ 0x00000000 /* DENALI_PHY_632_DATA */ ++ 0x00000000 /* DENALI_PHY_633_DATA */ ++ 0x00000000 /* DENALI_PHY_634_DATA */ ++ 0x00000000 /* DENALI_PHY_635_DATA */ ++ 0x00000000 /* DENALI_PHY_636_DATA */ ++ 0x00000000 /* DENALI_PHY_637_DATA */ ++ 0x00000000 /* DENALI_PHY_638_DATA */ ++ 0x00000000 /* DENALI_PHY_639_DATA */ ++ 0x35176402 /* DENALI_PHY_640_DATA */ ++ 0x0004c008 /* DENALI_PHY_641_DATA */ ++ 0x00000120 /* DENALI_PHY_642_DATA */ ++ 0x00000000 /* DENALI_PHY_643_DATA */ ++ 0x00000000 /* DENALI_PHY_644_DATA */ ++ 0x00010000 /* DENALI_PHY_645_DATA */ ++ 0x01DDDD90 /* DENALI_PHY_646_DATA */ ++ 0x01DDDD90 /* DENALI_PHY_647_DATA */ ++ 0x01030000 /* DENALI_PHY_648_DATA */ ++ 0x01000000 /* DENALI_PHY_649_DATA */ ++ 0x00c00000 /* DENALI_PHY_650_DATA */ ++ 0x00000007 /* DENALI_PHY_651_DATA */ ++ 0x00000000 /* DENALI_PHY_652_DATA */ ++ 0x00000000 /* DENALI_PHY_653_DATA */ ++ 0x04000408 /* DENALI_PHY_654_DATA */ ++ 0x00000408 /* DENALI_PHY_655_DATA */ ++ 0x00e4e400 /* DENALI_PHY_656_DATA */ ++ 0x00000000 /* DENALI_PHY_657_DATA */ ++ 0x00000000 /* DENALI_PHY_658_DATA */ ++ 0x00000000 /* DENALI_PHY_659_DATA */ ++ 0x00000000 /* DENALI_PHY_660_DATA */ ++ 0x00000000 /* DENALI_PHY_661_DATA */ ++ 0x00000000 /* DENALI_PHY_662_DATA */ ++ 0x00000000 /* DENALI_PHY_663_DATA */ ++ 0x00000000 /* DENALI_PHY_664_DATA */ ++ 0x00000000 /* DENALI_PHY_665_DATA */ ++ 0x00000000 /* DENALI_PHY_666_DATA */ ++ 0x00000000 /* DENALI_PHY_667_DATA */ ++ 0x00000000 /* DENALI_PHY_668_DATA */ ++ 0x00000000 /* DENALI_PHY_669_DATA */ ++ 0x00000000 /* DENALI_PHY_670_DATA */ ++ 0x00000000 /* DENALI_PHY_671_DATA */ ++ 0x00000000 /* DENALI_PHY_672_DATA */ ++ 0x00200000 /* DENALI_PHY_673_DATA */ ++ 0x00000000 /* DENALI_PHY_674_DATA */ ++ 0x00000000 /* DENALI_PHY_675_DATA */ ++ 0x00000000 /* DENALI_PHY_676_DATA */ ++ 0x00000000 /* DENALI_PHY_677_DATA */ ++ 0x00000000 /* DENALI_PHY_678_DATA */ ++ 0x00000000 /* DENALI_PHY_679_DATA */ ++ 0x02800280 /* DENALI_PHY_680_DATA */ ++ 0x02800280 /* DENALI_PHY_681_DATA */ ++ 0x02800280 /* DENALI_PHY_682_DATA */ ++ 0x02800280 /* DENALI_PHY_683_DATA */ ++ 0x00000280 /* DENALI_PHY_684_DATA */ ++ 0x00000000 /* DENALI_PHY_685_DATA */ ++ 0x00000000 /* DENALI_PHY_686_DATA */ ++ 0x00000000 /* DENALI_PHY_687_DATA */ ++ 0x00000000 /* DENALI_PHY_688_DATA */ ++ 0x00000000 /* DENALI_PHY_689_DATA */ ++ 0x00800080 /* DENALI_PHY_690_DATA */ ++ 0x00800080 /* DENALI_PHY_691_DATA */ ++ 0x00800080 /* DENALI_PHY_692_DATA */ ++ 0x00800080 /* DENALI_PHY_693_DATA */ ++ 0x00800080 /* DENALI_PHY_694_DATA */ ++ 0x00800080 /* DENALI_PHY_695_DATA */ ++ 0x00800080 /* DENALI_PHY_696_DATA */ ++ 0x00800080 /* DENALI_PHY_697_DATA */ ++ 0x00800080 /* DENALI_PHY_698_DATA */ ++ 0x00010120 /* DENALI_PHY_699_DATA */ ++ 0x000001d0 /* DENALI_PHY_700_DATA */ ++ 0x01000000 /* DENALI_PHY_701_DATA */ ++ 0x00000000 /* DENALI_PHY_702_DATA */ ++ 0x00000002 /* DENALI_PHY_703_DATA */ ++ 0x51313152 /* DENALI_PHY_704_DATA */ ++ 0x80013130 /* DENALI_PHY_705_DATA */ ++ 0x03000080 /* DENALI_PHY_706_DATA */ ++ 0x00100002 /* DENALI_PHY_707_DATA */ ++ 0x0c064208 /* DENALI_PHY_708_DATA */ ++ 0x000f0c0f /* DENALI_PHY_709_DATA */ ++ 0x01000140 /* DENALI_PHY_710_DATA */ ++ 0x0000000c /* DENALI_PHY_711_DATA */ ++ 0x00000000 /* DENALI_PHY_712_DATA */ ++ 0x00000000 /* DENALI_PHY_713_DATA */ ++ 0x00000000 /* DENALI_PHY_714_DATA */ ++ 0x00000000 /* DENALI_PHY_715_DATA */ ++ 0x00000000 /* DENALI_PHY_716_DATA */ ++ 0x00000000 /* DENALI_PHY_717_DATA */ ++ 0x00000000 /* DENALI_PHY_718_DATA */ ++ 0x00000000 /* DENALI_PHY_719_DATA */ ++ 0x00000000 /* DENALI_PHY_720_DATA */ ++ 0x00000000 /* DENALI_PHY_721_DATA */ ++ 0x00000000 /* DENALI_PHY_722_DATA */ ++ 0x00000000 /* DENALI_PHY_723_DATA */ ++ 0x00000000 /* DENALI_PHY_724_DATA */ ++ 0x00000000 /* DENALI_PHY_725_DATA */ ++ 0x00000000 /* DENALI_PHY_726_DATA */ ++ 0x00000000 /* DENALI_PHY_727_DATA */ ++ 0x00000000 /* DENALI_PHY_728_DATA */ ++ 0x00000000 /* DENALI_PHY_729_DATA */ ++ 0x00000000 /* DENALI_PHY_730_DATA */ ++ 0x00000000 /* DENALI_PHY_731_DATA */ ++ 0x00000000 /* DENALI_PHY_732_DATA */ ++ 0x00000000 /* DENALI_PHY_733_DATA */ ++ 0x00000000 /* DENALI_PHY_734_DATA */ ++ 0x00000000 /* DENALI_PHY_735_DATA */ ++ 0x00000000 /* DENALI_PHY_736_DATA */ ++ 0x00000000 /* DENALI_PHY_737_DATA */ ++ 0x00000000 /* DENALI_PHY_738_DATA */ ++ 0x00000000 /* DENALI_PHY_739_DATA */ ++ 0x00000000 /* DENALI_PHY_740_DATA */ ++ 0x00000000 /* DENALI_PHY_741_DATA */ ++ 0x00000000 /* DENALI_PHY_742_DATA */ ++ 0x00000000 /* DENALI_PHY_743_DATA */ ++ 0x00000000 /* DENALI_PHY_744_DATA */ ++ 0x00000000 /* DENALI_PHY_745_DATA */ ++ 0x00000000 /* DENALI_PHY_746_DATA */ ++ 0x00000000 /* DENALI_PHY_747_DATA */ ++ 0x00000000 /* DENALI_PHY_748_DATA */ ++ 0x00000000 /* DENALI_PHY_749_DATA */ ++ 0x00000000 /* DENALI_PHY_750_DATA */ ++ 0x00000000 /* DENALI_PHY_751_DATA */ ++ 0x00000000 /* DENALI_PHY_752_DATA */ ++ 0x00000000 /* DENALI_PHY_753_DATA */ ++ 0x00000000 /* DENALI_PHY_754_DATA */ ++ 0x00000000 /* DENALI_PHY_755_DATA */ ++ 0x00000000 /* DENALI_PHY_756_DATA */ ++ 0x00000000 /* DENALI_PHY_757_DATA */ ++ 0x00000000 /* DENALI_PHY_758_DATA */ ++ 0x00000000 /* DENALI_PHY_759_DATA */ ++ 0x00000000 /* DENALI_PHY_760_DATA */ ++ 0x00000000 /* DENALI_PHY_761_DATA */ ++ 0x00000000 /* DENALI_PHY_762_DATA */ ++ 0x00000000 /* DENALI_PHY_763_DATA */ ++ 0x00000000 /* DENALI_PHY_764_DATA */ ++ 0x00000000 /* DENALI_PHY_765_DATA */ ++ 0x00000000 /* DENALI_PHY_766_DATA */ ++ 0x00000000 /* DENALI_PHY_767_DATA */ ++ 0x10526347 /* DENALI_PHY_768_DATA */ ++ 0x0004c008 /* DENALI_PHY_769_DATA */ ++ 0x00000120 /* DENALI_PHY_770_DATA */ ++ 0x00000000 /* DENALI_PHY_771_DATA */ ++ 0x00000000 /* DENALI_PHY_772_DATA */ ++ 0x00010000 /* DENALI_PHY_773_DATA */ ++ 0x01DDDD90 /* DENALI_PHY_774_DATA */ ++ 0x01DDDD90 /* DENALI_PHY_775_DATA */ ++ 0x01030000 /* DENALI_PHY_776_DATA */ ++ 0x01000000 /* DENALI_PHY_777_DATA */ ++ 0x00c00000 /* DENALI_PHY_778_DATA */ ++ 0x00000007 /* DENALI_PHY_779_DATA */ ++ 0x00000000 /* DENALI_PHY_780_DATA */ ++ 0x00000000 /* DENALI_PHY_781_DATA */ ++ 0x04000408 /* DENALI_PHY_782_DATA */ ++ 0x00000408 /* DENALI_PHY_783_DATA */ ++ 0x00e4e400 /* DENALI_PHY_784_DATA */ ++ 0x00000000 /* DENALI_PHY_785_DATA */ ++ 0x00000000 /* DENALI_PHY_786_DATA */ ++ 0x00000000 /* DENALI_PHY_787_DATA */ ++ 0x00000000 /* DENALI_PHY_788_DATA */ ++ 0x00000000 /* DENALI_PHY_789_DATA */ ++ 0x00000000 /* DENALI_PHY_790_DATA */ ++ 0x00000000 /* DENALI_PHY_791_DATA */ ++ 0x00000000 /* DENALI_PHY_792_DATA */ ++ 0x00000000 /* DENALI_PHY_793_DATA */ ++ 0x00000000 /* DENALI_PHY_794_DATA */ ++ 0x00000000 /* DENALI_PHY_795_DATA */ ++ 0x00000000 /* DENALI_PHY_796_DATA */ ++ 0x00000000 /* DENALI_PHY_797_DATA */ ++ 0x00000000 /* DENALI_PHY_798_DATA */ ++ 0x00000000 /* DENALI_PHY_799_DATA */ ++ 0x00000000 /* DENALI_PHY_800_DATA */ ++ 0x00200000 /* DENALI_PHY_801_DATA */ ++ 0x00000000 /* DENALI_PHY_802_DATA */ ++ 0x00000000 /* DENALI_PHY_803_DATA */ ++ 0x00000000 /* DENALI_PHY_804_DATA */ ++ 0x00000000 /* DENALI_PHY_805_DATA */ ++ 0x00000000 /* DENALI_PHY_806_DATA */ ++ 0x00000000 /* DENALI_PHY_807_DATA */ ++ 0x02800280 /* DENALI_PHY_808_DATA */ ++ 0x02800280 /* DENALI_PHY_809_DATA */ ++ 0x02800280 /* DENALI_PHY_810_DATA */ ++ 0x02800280 /* DENALI_PHY_811_DATA */ ++ 0x00000280 /* DENALI_PHY_812_DATA */ ++ 0x00000000 /* DENALI_PHY_813_DATA */ ++ 0x00000000 /* DENALI_PHY_814_DATA */ ++ 0x00000000 /* DENALI_PHY_815_DATA */ ++ 0x00000000 /* DENALI_PHY_816_DATA */ ++ 0x00000000 /* DENALI_PHY_817_DATA */ ++ 0x00800080 /* DENALI_PHY_818_DATA */ ++ 0x00800080 /* DENALI_PHY_819_DATA */ ++ 0x00800080 /* DENALI_PHY_820_DATA */ ++ 0x00800080 /* DENALI_PHY_821_DATA */ ++ 0x00800080 /* DENALI_PHY_822_DATA */ ++ 0x00800080 /* DENALI_PHY_823_DATA */ ++ 0x00800080 /* DENALI_PHY_824_DATA */ ++ 0x00800080 /* DENALI_PHY_825_DATA */ ++ 0x00800080 /* DENALI_PHY_826_DATA */ ++ 0x00010120 /* DENALI_PHY_827_DATA */ ++ 0x000001d0 /* DENALI_PHY_828_DATA */ ++ 0x01000000 /* DENALI_PHY_829_DATA */ ++ 0x00000000 /* DENALI_PHY_830_DATA */ ++ 0x00000002 /* DENALI_PHY_831_DATA */ ++ 0x51313152 /* DENALI_PHY_832_DATA */ ++ 0x80013130 /* DENALI_PHY_833_DATA */ ++ 0x03000080 /* DENALI_PHY_834_DATA */ ++ 0x00100002 /* DENALI_PHY_835_DATA */ ++ 0x0c064208 /* DENALI_PHY_836_DATA */ ++ 0x000f0c0f /* DENALI_PHY_837_DATA */ ++ 0x01000140 /* DENALI_PHY_838_DATA */ ++ 0x0000000c /* DENALI_PHY_839_DATA */ ++ 0x00000000 /* DENALI_PHY_840_DATA */ ++ 0x00000000 /* DENALI_PHY_841_DATA */ ++ 0x00000000 /* DENALI_PHY_842_DATA */ ++ 0x00000000 /* DENALI_PHY_843_DATA */ ++ 0x00000000 /* DENALI_PHY_844_DATA */ ++ 0x00000000 /* DENALI_PHY_845_DATA */ ++ 0x00000000 /* DENALI_PHY_846_DATA */ ++ 0x00000000 /* DENALI_PHY_847_DATA */ ++ 0x00000000 /* DENALI_PHY_848_DATA */ ++ 0x00000000 /* DENALI_PHY_849_DATA */ ++ 0x00000000 /* DENALI_PHY_850_DATA */ ++ 0x00000000 /* DENALI_PHY_851_DATA */ ++ 0x00000000 /* DENALI_PHY_852_DATA */ ++ 0x00000000 /* DENALI_PHY_853_DATA */ ++ 0x00000000 /* DENALI_PHY_854_DATA */ ++ 0x00000000 /* DENALI_PHY_855_DATA */ ++ 0x00000000 /* DENALI_PHY_856_DATA */ ++ 0x00000000 /* DENALI_PHY_857_DATA */ ++ 0x00000000 /* DENALI_PHY_858_DATA */ ++ 0x00000000 /* DENALI_PHY_859_DATA */ ++ 0x00000000 /* DENALI_PHY_860_DATA */ ++ 0x00000000 /* DENALI_PHY_861_DATA */ ++ 0x00000000 /* DENALI_PHY_862_DATA */ ++ 0x00000000 /* DENALI_PHY_863_DATA */ ++ 0x00000000 /* DENALI_PHY_864_DATA */ ++ 0x00000000 /* DENALI_PHY_865_DATA */ ++ 0x00000000 /* DENALI_PHY_866_DATA */ ++ 0x00000000 /* DENALI_PHY_867_DATA */ ++ 0x00000000 /* DENALI_PHY_868_DATA */ ++ 0x00000000 /* DENALI_PHY_869_DATA */ ++ 0x00000000 /* DENALI_PHY_870_DATA */ ++ 0x00000000 /* DENALI_PHY_871_DATA */ ++ 0x00000000 /* DENALI_PHY_872_DATA */ ++ 0x00000000 /* DENALI_PHY_873_DATA */ ++ 0x00000000 /* DENALI_PHY_874_DATA */ ++ 0x00000000 /* DENALI_PHY_875_DATA */ ++ 0x00000000 /* DENALI_PHY_876_DATA */ ++ 0x00000000 /* DENALI_PHY_877_DATA */ ++ 0x00000000 /* DENALI_PHY_878_DATA */ ++ 0x00000000 /* DENALI_PHY_879_DATA */ ++ 0x00000000 /* DENALI_PHY_880_DATA */ ++ 0x00000000 /* DENALI_PHY_881_DATA */ ++ 0x00000000 /* DENALI_PHY_882_DATA */ ++ 0x00000000 /* DENALI_PHY_883_DATA */ ++ 0x00000000 /* DENALI_PHY_884_DATA */ ++ 0x00000000 /* DENALI_PHY_885_DATA */ ++ 0x00000000 /* DENALI_PHY_886_DATA */ ++ 0x00000000 /* DENALI_PHY_887_DATA */ ++ 0x00000000 /* DENALI_PHY_888_DATA */ ++ 0x00000000 /* DENALI_PHY_889_DATA */ ++ 0x00000000 /* DENALI_PHY_890_DATA */ ++ 0x00000000 /* DENALI_PHY_891_DATA */ ++ 0x00000000 /* DENALI_PHY_892_DATA */ ++ 0x00000000 /* DENALI_PHY_893_DATA */ ++ 0x00000000 /* DENALI_PHY_894_DATA */ ++ 0x00000000 /* DENALI_PHY_895_DATA */ ++ 0x41753260 /* DENALI_PHY_896_DATA */ ++ 0x0004c008 /* DENALI_PHY_897_DATA */ ++ 0x00000120 /* DENALI_PHY_898_DATA */ ++ 0x00000000 /* DENALI_PHY_899_DATA */ ++ 0x00000000 /* DENALI_PHY_900_DATA */ ++ 0x00010000 /* DENALI_PHY_901_DATA */ ++ 0x01DDDD90 /* DENALI_PHY_902_DATA */ ++ 0x01DDDD90 /* DENALI_PHY_903_DATA */ ++ 0x01030000 /* DENALI_PHY_904_DATA */ ++ 0x01000000 /* DENALI_PHY_905_DATA */ ++ 0x00c00000 /* DENALI_PHY_906_DATA */ ++ 0x00000007 /* DENALI_PHY_907_DATA */ ++ 0x00000000 /* DENALI_PHY_908_DATA */ ++ 0x00000000 /* DENALI_PHY_909_DATA */ ++ 0x04000408 /* DENALI_PHY_910_DATA */ ++ 0x00000408 /* DENALI_PHY_911_DATA */ ++ 0x00e4e400 /* DENALI_PHY_912_DATA */ ++ 0x00000000 /* DENALI_PHY_913_DATA */ ++ 0x00000000 /* DENALI_PHY_914_DATA */ ++ 0x00000000 /* DENALI_PHY_915_DATA */ ++ 0x00000000 /* DENALI_PHY_916_DATA */ ++ 0x00000000 /* DENALI_PHY_917_DATA */ ++ 0x00000000 /* DENALI_PHY_918_DATA */ ++ 0x00000000 /* DENALI_PHY_919_DATA */ ++ 0x00000000 /* DENALI_PHY_920_DATA */ ++ 0x00000000 /* DENALI_PHY_921_DATA */ ++ 0x00000000 /* DENALI_PHY_922_DATA */ ++ 0x00000000 /* DENALI_PHY_923_DATA */ ++ 0x00000000 /* DENALI_PHY_924_DATA */ ++ 0x00000000 /* DENALI_PHY_925_DATA */ ++ 0x00000000 /* DENALI_PHY_926_DATA */ ++ 0x00000000 /* DENALI_PHY_927_DATA */ ++ 0x00000000 /* DENALI_PHY_928_DATA */ ++ 0x00200000 /* DENALI_PHY_929_DATA */ ++ 0x00000000 /* DENALI_PHY_930_DATA */ ++ 0x00000000 /* DENALI_PHY_931_DATA */ ++ 0x00000000 /* DENALI_PHY_932_DATA */ ++ 0x00000000 /* DENALI_PHY_933_DATA */ ++ 0x00000000 /* DENALI_PHY_934_DATA */ ++ 0x00000000 /* DENALI_PHY_935_DATA */ ++ 0x02800280 /* DENALI_PHY_936_DATA */ ++ 0x02800280 /* DENALI_PHY_937_DATA */ ++ 0x02800280 /* DENALI_PHY_938_DATA */ ++ 0x02800280 /* DENALI_PHY_939_DATA */ ++ 0x00000280 /* DENALI_PHY_940_DATA */ ++ 0x00000000 /* DENALI_PHY_941_DATA */ ++ 0x00000000 /* DENALI_PHY_942_DATA */ ++ 0x00000000 /* DENALI_PHY_943_DATA */ ++ 0x00000000 /* DENALI_PHY_944_DATA */ ++ 0x00000000 /* DENALI_PHY_945_DATA */ ++ 0x00800080 /* DENALI_PHY_946_DATA */ ++ 0x00800080 /* DENALI_PHY_947_DATA */ ++ 0x00800080 /* DENALI_PHY_948_DATA */ ++ 0x00800080 /* DENALI_PHY_949_DATA */ ++ 0x00800080 /* DENALI_PHY_950_DATA */ ++ 0x00800080 /* DENALI_PHY_951_DATA */ ++ 0x00800080 /* DENALI_PHY_952_DATA */ ++ 0x00800080 /* DENALI_PHY_953_DATA */ ++ 0x00800080 /* DENALI_PHY_954_DATA */ ++ 0x00010120 /* DENALI_PHY_955_DATA */ ++ 0x000001d0 /* DENALI_PHY_956_DATA */ ++ 0x01000000 /* DENALI_PHY_957_DATA */ ++ 0x00000000 /* DENALI_PHY_958_DATA */ ++ 0x00000002 /* DENALI_PHY_959_DATA */ ++ 0x51313152 /* DENALI_PHY_960_DATA */ ++ 0x80013130 /* DENALI_PHY_961_DATA */ ++ 0x03000080 /* DENALI_PHY_962_DATA */ ++ 0x00100002 /* DENALI_PHY_963_DATA */ ++ 0x0c064208 /* DENALI_PHY_964_DATA */ ++ 0x000f0c0f /* DENALI_PHY_965_DATA */ ++ 0x01000140 /* DENALI_PHY_966_DATA */ ++ 0x0000000c /* DENALI_PHY_967_DATA */ ++ 0x00000000 /* DENALI_PHY_968_DATA */ ++ 0x00000000 /* DENALI_PHY_969_DATA */ ++ 0x00000000 /* DENALI_PHY_970_DATA */ ++ 0x00000000 /* DENALI_PHY_971_DATA */ ++ 0x00000000 /* DENALI_PHY_972_DATA */ ++ 0x00000000 /* DENALI_PHY_973_DATA */ ++ 0x00000000 /* DENALI_PHY_974_DATA */ ++ 0x00000000 /* DENALI_PHY_975_DATA */ ++ 0x00000000 /* DENALI_PHY_976_DATA */ ++ 0x00000000 /* DENALI_PHY_977_DATA */ ++ 0x00000000 /* DENALI_PHY_978_DATA */ ++ 0x00000000 /* DENALI_PHY_979_DATA */ ++ 0x00000000 /* DENALI_PHY_980_DATA */ ++ 0x00000000 /* DENALI_PHY_981_DATA */ ++ 0x00000000 /* DENALI_PHY_982_DATA */ ++ 0x00000000 /* DENALI_PHY_983_DATA */ ++ 0x00000000 /* DENALI_PHY_984_DATA */ ++ 0x00000000 /* DENALI_PHY_985_DATA */ ++ 0x00000000 /* DENALI_PHY_986_DATA */ ++ 0x00000000 /* DENALI_PHY_987_DATA */ ++ 0x00000000 /* DENALI_PHY_988_DATA */ ++ 0x00000000 /* DENALI_PHY_989_DATA */ ++ 0x00000000 /* DENALI_PHY_990_DATA */ ++ 0x00000000 /* DENALI_PHY_991_DATA */ ++ 0x00000000 /* DENALI_PHY_992_DATA */ ++ 0x00000000 /* DENALI_PHY_993_DATA */ ++ 0x00000000 /* DENALI_PHY_994_DATA */ ++ 0x00000000 /* DENALI_PHY_995_DATA */ ++ 0x00000000 /* DENALI_PHY_996_DATA */ ++ 0x00000000 /* DENALI_PHY_997_DATA */ ++ 0x00000000 /* DENALI_PHY_998_DATA */ ++ 0x00000000 /* DENALI_PHY_999_DATA */ ++ 0x00000000 /* DENALI_PHY_1000_DATA */ ++ 0x00000000 /* DENALI_PHY_1001_DATA */ ++ 0x00000000 /* DENALI_PHY_1002_DATA */ ++ 0x00000000 /* DENALI_PHY_1003_DATA */ ++ 0x00000000 /* DENALI_PHY_1004_DATA */ ++ 0x00000000 /* DENALI_PHY_1005_DATA */ ++ 0x00000000 /* DENALI_PHY_1006_DATA */ ++ 0x00000000 /* DENALI_PHY_1007_DATA */ ++ 0x00000000 /* DENALI_PHY_1008_DATA */ ++ 0x00000000 /* DENALI_PHY_1009_DATA */ ++ 0x00000000 /* DENALI_PHY_1010_DATA */ ++ 0x00000000 /* DENALI_PHY_1011_DATA */ ++ 0x00000000 /* DENALI_PHY_1012_DATA */ ++ 0x00000000 /* DENALI_PHY_1013_DATA */ ++ 0x00000000 /* DENALI_PHY_1014_DATA */ ++ 0x00000000 /* DENALI_PHY_1015_DATA */ ++ 0x00000000 /* DENALI_PHY_1016_DATA */ ++ 0x00000000 /* DENALI_PHY_1017_DATA */ ++ 0x00000000 /* DENALI_PHY_1018_DATA */ ++ 0x00000000 /* DENALI_PHY_1019_DATA */ ++ 0x00000000 /* DENALI_PHY_1020_DATA */ ++ 0x00000000 /* DENALI_PHY_1021_DATA */ ++ 0x00000000 /* DENALI_PHY_1022_DATA */ ++ 0x00000000 /* DENALI_PHY_1023_DATA */ ++ 0x76543210 /* DENALI_PHY_1024_DATA */ ++ 0x0004c008 /* DENALI_PHY_1025_DATA */ ++ 0x00000120 /* DENALI_PHY_1026_DATA */ ++ 0x00000000 /* DENALI_PHY_1027_DATA */ ++ 0x00000000 /* DENALI_PHY_1028_DATA */ ++ 0x00010000 /* DENALI_PHY_1029_DATA */ ++ 0x01DDDD90 /* DENALI_PHY_1030_DATA */ ++ 0x01DDDD90 /* DENALI_PHY_1031_DATA */ ++ 0x01030000 /* DENALI_PHY_1032_DATA */ ++ 0x01000000 /* DENALI_PHY_1033_DATA */ ++ 0x00c00000 /* DENALI_PHY_1034_DATA */ ++ 0x00000007 /* DENALI_PHY_1035_DATA */ ++ 0x00000000 /* DENALI_PHY_1036_DATA */ ++ 0x00000000 /* DENALI_PHY_1037_DATA */ ++ 0x04000408 /* DENALI_PHY_1038_DATA */ ++ 0x00000408 /* DENALI_PHY_1039_DATA */ ++ 0x00e4e400 /* DENALI_PHY_1040_DATA */ ++ 0x00000000 /* DENALI_PHY_1041_DATA */ ++ 0x00000000 /* DENALI_PHY_1042_DATA */ ++ 0x00000000 /* DENALI_PHY_1043_DATA */ ++ 0x00000000 /* DENALI_PHY_1044_DATA */ ++ 0x00000000 /* DENALI_PHY_1045_DATA */ ++ 0x00000000 /* DENALI_PHY_1046_DATA */ ++ 0x00000000 /* DENALI_PHY_1047_DATA */ ++ 0x00000000 /* DENALI_PHY_1048_DATA */ ++ 0x00000000 /* DENALI_PHY_1049_DATA */ ++ 0x00000000 /* DENALI_PHY_1050_DATA */ ++ 0x00000000 /* DENALI_PHY_1051_DATA */ ++ 0x00000000 /* DENALI_PHY_1052_DATA */ ++ 0x00000000 /* DENALI_PHY_1053_DATA */ ++ 0x00000000 /* DENALI_PHY_1054_DATA */ ++ 0x00000000 /* DENALI_PHY_1055_DATA */ ++ 0x00000000 /* DENALI_PHY_1056_DATA */ ++ 0x00200000 /* DENALI_PHY_1057_DATA */ ++ 0x00000000 /* DENALI_PHY_1058_DATA */ ++ 0x00000000 /* DENALI_PHY_1059_DATA */ ++ 0x00000000 /* DENALI_PHY_1060_DATA */ ++ 0x00000000 /* DENALI_PHY_1061_DATA */ ++ 0x00000000 /* DENALI_PHY_1062_DATA */ ++ 0x00000000 /* DENALI_PHY_1063_DATA */ ++ 0x02800280 /* DENALI_PHY_1064_DATA */ ++ 0x02800280 /* DENALI_PHY_1065_DATA */ ++ 0x02800280 /* DENALI_PHY_1066_DATA */ ++ 0x02800280 /* DENALI_PHY_1067_DATA */ ++ 0x00000280 /* DENALI_PHY_1068_DATA */ ++ 0x00000000 /* DENALI_PHY_1069_DATA */ ++ 0x00000000 /* DENALI_PHY_1070_DATA */ ++ 0x00000000 /* DENALI_PHY_1071_DATA */ ++ 0x00000000 /* DENALI_PHY_1072_DATA */ ++ 0x00000000 /* DENALI_PHY_1073_DATA */ ++ 0x00800080 /* DENALI_PHY_1074_DATA */ ++ 0x00800080 /* DENALI_PHY_1075_DATA */ ++ 0x00800080 /* DENALI_PHY_1076_DATA */ ++ 0x00800080 /* DENALI_PHY_1077_DATA */ ++ 0x00800080 /* DENALI_PHY_1078_DATA */ ++ 0x00800080 /* DENALI_PHY_1079_DATA */ ++ 0x00800080 /* DENALI_PHY_1080_DATA */ ++ 0x00800080 /* DENALI_PHY_1081_DATA */ ++ 0x00800080 /* DENALI_PHY_1082_DATA */ ++ 0x00010120 /* DENALI_PHY_1083_DATA */ ++ 0x000001d0 /* DENALI_PHY_1084_DATA */ ++ 0x01000000 /* DENALI_PHY_1085_DATA */ ++ 0x00000000 /* DENALI_PHY_1086_DATA */ ++ 0x00000002 /* DENALI_PHY_1087_DATA */ ++ 0x51313152 /* DENALI_PHY_1088_DATA */ ++ 0x80013130 /* DENALI_PHY_1089_DATA */ ++ 0x03000080 /* DENALI_PHY_1090_DATA */ ++ 0x00100002 /* DENALI_PHY_1091_DATA */ ++ 0x0c064208 /* DENALI_PHY_1092_DATA */ ++ 0x000f0c0f /* DENALI_PHY_1093_DATA */ ++ 0x01000140 /* DENALI_PHY_1094_DATA */ ++ 0x0000000c /* DENALI_PHY_1095_DATA */ ++ 0x00000000 /* DENALI_PHY_1096_DATA */ ++ 0x00000000 /* DENALI_PHY_1097_DATA */ ++ 0x00000000 /* DENALI_PHY_1098_DATA */ ++ 0x00000000 /* DENALI_PHY_1099_DATA */ ++ 0x00000000 /* DENALI_PHY_1100_DATA */ ++ 0x00000000 /* DENALI_PHY_1101_DATA */ ++ 0x00000000 /* DENALI_PHY_1102_DATA */ ++ 0x00000000 /* DENALI_PHY_1103_DATA */ ++ 0x00000000 /* DENALI_PHY_1104_DATA */ ++ 0x00000000 /* DENALI_PHY_1105_DATA */ ++ 0x00000000 /* DENALI_PHY_1106_DATA */ ++ 0x00000000 /* DENALI_PHY_1107_DATA */ ++ 0x00000000 /* DENALI_PHY_1108_DATA */ ++ 0x00000000 /* DENALI_PHY_1109_DATA */ ++ 0x00000000 /* DENALI_PHY_1110_DATA */ ++ 0x00000000 /* DENALI_PHY_1111_DATA */ ++ 0x00000000 /* DENALI_PHY_1112_DATA */ ++ 0x00000000 /* DENALI_PHY_1113_DATA */ ++ 0x00000000 /* DENALI_PHY_1114_DATA */ ++ 0x00000000 /* DENALI_PHY_1115_DATA */ ++ 0x00000000 /* DENALI_PHY_1116_DATA */ ++ 0x00000000 /* DENALI_PHY_1117_DATA */ ++ 0x00000000 /* DENALI_PHY_1118_DATA */ ++ 0x00000000 /* DENALI_PHY_1119_DATA */ ++ 0x00000000 /* DENALI_PHY_1120_DATA */ ++ 0x00000000 /* DENALI_PHY_1121_DATA */ ++ 0x00000000 /* DENALI_PHY_1122_DATA */ ++ 0x00000000 /* DENALI_PHY_1123_DATA */ ++ 0x00000000 /* DENALI_PHY_1124_DATA */ ++ 0x00000000 /* DENALI_PHY_1125_DATA */ ++ 0x00000000 /* DENALI_PHY_1126_DATA */ ++ 0x00000000 /* DENALI_PHY_1127_DATA */ ++ 0x00000000 /* DENALI_PHY_1128_DATA */ ++ 0x00000000 /* DENALI_PHY_1129_DATA */ ++ 0x00000000 /* DENALI_PHY_1130_DATA */ ++ 0x00000000 /* DENALI_PHY_1131_DATA */ ++ 0x00000000 /* DENALI_PHY_1132_DATA */ ++ 0x00000000 /* DENALI_PHY_1133_DATA */ ++ 0x00000000 /* DENALI_PHY_1134_DATA */ ++ 0x00000000 /* DENALI_PHY_1135_DATA */ ++ 0x00000000 /* DENALI_PHY_1136_DATA */ ++ 0x00000000 /* DENALI_PHY_1137_DATA */ ++ 0x00000000 /* DENALI_PHY_1138_DATA */ ++ 0x00000000 /* DENALI_PHY_1139_DATA */ ++ 0x00000000 /* DENALI_PHY_1140_DATA */ ++ 0x00000000 /* DENALI_PHY_1141_DATA */ ++ 0x00000000 /* DENALI_PHY_1142_DATA */ ++ 0x00000000 /* DENALI_PHY_1143_DATA */ ++ 0x00000000 /* DENALI_PHY_1144_DATA */ ++ 0x00000000 /* DENALI_PHY_1145_DATA */ ++ 0x00000000 /* DENALI_PHY_1146_DATA */ ++ 0x00000000 /* DENALI_PHY_1147_DATA */ ++ 0x00000000 /* DENALI_PHY_1148_DATA */ ++ 0x00000000 /* DENALI_PHY_1149_DATA */ ++ 0x00000000 /* DENALI_PHY_1150_DATA */ ++ 0x00000000 /* DENALI_PHY_1151_DATA */ ++ 0x00000000 /* DENALI_PHY_1152_DATA */ ++ 0x00000000 /* DENALI_PHY_1153_DATA */ ++ 0x00050000 /* DENALI_PHY_1154_DATA */ ++ 0x00000000 /* DENALI_PHY_1155_DATA */ ++ 0x00000000 /* DENALI_PHY_1156_DATA */ ++ 0x00000000 /* DENALI_PHY_1157_DATA */ ++ 0x00000100 /* DENALI_PHY_1158_DATA */ ++ 0x00000000 /* DENALI_PHY_1159_DATA */ ++ 0x00000000 /* DENALI_PHY_1160_DATA */ ++ 0x00506401 /* DENALI_PHY_1161_DATA */ ++ 0x01221102 /* DENALI_PHY_1162_DATA */ ++ 0x00000122 /* DENALI_PHY_1163_DATA */ ++ 0x00000000 /* DENALI_PHY_1164_DATA */ ++ 0x000B1F00 /* DENALI_PHY_1165_DATA */ ++ 0x0B1F0B1F /* DENALI_PHY_1166_DATA */ ++ 0x0B1F0B1F /* DENALI_PHY_1167_DATA */ ++ 0x0B1F0B1F /* DENALI_PHY_1168_DATA */ ++ 0x0B1F0B1F /* DENALI_PHY_1169_DATA */ ++ 0x00000B00 /* DENALI_PHY_1170_DATA */ ++ 0x42080010 /* DENALI_PHY_1171_DATA */ ++ 0x01000100 /* DENALI_PHY_1172_DATA */ ++ 0x01000100 /* DENALI_PHY_1173_DATA */ ++ 0x01000100 /* DENALI_PHY_1174_DATA */ ++ 0x01000100 /* DENALI_PHY_1175_DATA */ ++ 0x00000000 /* DENALI_PHY_1176_DATA */ ++ 0x00000000 /* DENALI_PHY_1177_DATA */ ++ 0x00000000 /* DENALI_PHY_1178_DATA */ ++ 0x00000000 /* DENALI_PHY_1179_DATA */ ++ 0x00000000 /* DENALI_PHY_1180_DATA */ ++ 0x00000903 /* DENALI_PHY_1181_DATA */ ++ 0x223FFF00 /* DENALI_PHY_1182_DATA */ ++ 0x000008FF /* DENALI_PHY_1183_DATA */ ++ 0x0000057F /* DENALI_PHY_1184_DATA */ ++ 0x0000057F /* DENALI_PHY_1185_DATA */ ++ 0x00037FFF /* DENALI_PHY_1186_DATA */ ++ 0x00037FFF /* DENALI_PHY_1187_DATA */ ++ 0x00004410 /* DENALI_PHY_1188_DATA */ ++ 0x00004410 /* DENALI_PHY_1189_DATA */ ++ 0x00004410 /* DENALI_PHY_1190_DATA */ ++ 0x00004410 /* DENALI_PHY_1191_DATA */ ++ 0x00004410 /* DENALI_PHY_1192_DATA */ ++ 0x00000111 /* DENALI_PHY_1193_DATA */ ++ 0x00000111 /* DENALI_PHY_1194_DATA */ ++ 0x00000000 /* DENALI_PHY_1195_DATA */ ++ 0x00000000 /* DENALI_PHY_1196_DATA */ ++ 0x00000000 /* DENALI_PHY_1197_DATA */ ++ 0x04000000 /* DENALI_PHY_1198_DATA */ ++ 0x00000000 /* DENALI_PHY_1199_DATA */ ++ 0x00000000 /* DENALI_PHY_1200_DATA */ ++ 0x00000108 /* DENALI_PHY_1201_DATA */ ++ 0x00000000 /* DENALI_PHY_1202_DATA */ ++ 0x00000000 /* DENALI_PHY_1203_DATA */ ++ 0x00000000 /* DENALI_PHY_1204_DATA */ ++ 0x00000001 /* DENALI_PHY_1205_DATA */ ++ 0x00000000 /* DENALI_PHY_1206_DATA */ ++ 0x00000000 /* DENALI_PHY_1207_DATA */ ++ 0x00000000 /* DENALI_PHY_1208_DATA */ ++ 0x00000000 /* DENALI_PHY_1209_DATA */ ++ 0x00000000 /* DENALI_PHY_1210_DATA */ ++ 0x00000000 /* DENALI_PHY_1211_DATA */ ++ 0x00020100 /* DENALI_PHY_1212_DATA */ ++ 0x00000000 /* DENALI_PHY_1213_DATA */ ++ 0x00000000 /* DENALI_PHY_1214_DATA */ ++ >; ++}; +diff --git a/arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi +index 7171e25..ee0e010 100644 +--- a/arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi ++++ b/arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi +@@ -4,6 +4,7 @@ + */ + + #include "fu740-c000-u-boot.dtsi" ++#include "fu740-hifive-unmatched-a00-ddr.dtsi" + + / { + aliases { +-- +2.7.4 + diff -Nru u-boot-2021.01+dfsg/debian/patches/riscv64/0017-riscv-sifive-dts-fu740-add-U-Boot-dmc-node.patch u-boot-2021.01+dfsg/debian/patches/riscv64/0017-riscv-sifive-dts-fu740-add-U-Boot-dmc-node.patch --- u-boot-2021.01+dfsg/debian/patches/riscv64/0017-riscv-sifive-dts-fu740-add-U-Boot-dmc-node.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/riscv64/0017-riscv-sifive-dts-fu740-add-U-Boot-dmc-node.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,36 @@ +From 47f6cf8d33518b925b6fa36333e6c5e92b762c00 Mon Sep 17 00:00:00 2001 +From: Pragnesh Patel +Date: Sat, 31 Oct 2020 19:57:12 +0530 +Subject: [PATCH 17/41] riscv: sifive: dts: fu740: add U-Boot dmc node + +Add dmc node to enable ddr driver. dmc is used to +initialize the memory controller. + +Signed-off-by: Pragnesh Patel +--- + arch/riscv/dts/fu740-c000-u-boot.dtsi | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/arch/riscv/dts/fu740-c000-u-boot.dtsi b/arch/riscv/dts/fu740-c000-u-boot.dtsi +index d38d573..1cc8cd4 100644 +--- a/arch/riscv/dts/fu740-c000-u-boot.dtsi ++++ b/arch/riscv/dts/fu740-c000-u-boot.dtsi +@@ -71,6 +71,15 @@ + reset-names = "ddr_ctrl", "ddr_axi", "ddr_ahb", + "ddr_phy", "gemgxl_reset", "cltx_reset"; + }; ++ dmc: dmc@100b0000 { ++ compatible = "sifive,fu740-c000-ddr"; ++ reg = <0x0 0x100b0000 0x0 0x0800 ++ 0x0 0x100b2000 0x0 0x2000 ++ 0x0 0x100b8000 0x0 0x1000>; ++ clocks = <&prci PRCI_CLK_DDRPLL>; ++ clock-frequency = <1066000000>; ++ u-boot,dm-spl; ++ }; + }; + }; + +-- +2.7.4 + diff -Nru u-boot-2021.01+dfsg/debian/patches/riscv64/0018-riscv-sifive-hifive_unmatched_fu740-add-SPL-configur.patch u-boot-2021.01+dfsg/debian/patches/riscv64/0018-riscv-sifive-hifive_unmatched_fu740-add-SPL-configur.patch --- u-boot-2021.01+dfsg/debian/patches/riscv64/0018-riscv-sifive-hifive_unmatched_fu740-add-SPL-configur.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/riscv64/0018-riscv-sifive-hifive_unmatched_fu740-add-SPL-configur.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,258 @@ +From 043af2665d5cea99a98137edff659fd1a144ef95 Mon Sep 17 00:00:00 2001 +From: Pragnesh Patel +Date: Wed, 21 Oct 2020 17:14:03 +0530 +Subject: [PATCH 18/41] riscv: sifive: hifive_unmatched_fu740: add SPL + configuration + +Add a support for SPL which will boot from L2 LIM (0x0800_0000) and +then SPL will boot U-Boot FIT image (OpenSBI FW_DYNAMIC + u-boot.bin) +from MMC boot devices. + +Signed-off-by: Pragnesh Patel +--- + arch/riscv/cpu/fu740/Makefile | 4 ++ + arch/riscv/cpu/fu740/spl.c | 23 +++++++ + arch/riscv/include/asm/arch-fu740/spl.h | 14 ++++ + board/sifive/hifive_unmatched_fu740/Kconfig | 8 +++ + board/sifive/hifive_unmatched_fu740/Makefile | 4 ++ + board/sifive/hifive_unmatched_fu740/spl.c | 85 +++++++++++++++++++++++++ + include/configs/sifive-hifive-unmatched-fu740.h | 16 +++++ + 7 files changed, 154 insertions(+) + create mode 100644 arch/riscv/cpu/fu740/spl.c + create mode 100644 arch/riscv/include/asm/arch-fu740/spl.h + create mode 100644 board/sifive/hifive_unmatched_fu740/spl.c + +diff --git a/arch/riscv/cpu/fu740/Makefile b/arch/riscv/cpu/fu740/Makefile +index 44700d9..043fb96 100644 +--- a/arch/riscv/cpu/fu740/Makefile ++++ b/arch/riscv/cpu/fu740/Makefile +@@ -3,5 +3,9 @@ + # Copyright (C) 2020 SiFive, Inc + # Pragnesh Patel + ++ifeq ($(CONFIG_SPL_BUILD),y) ++obj-y += spl.o ++else + obj-y += dram.o + obj-y += cpu.o ++endif +diff --git a/arch/riscv/cpu/fu740/spl.c b/arch/riscv/cpu/fu740/spl.c +new file mode 100644 +index 0000000..45657b7 +--- /dev/null ++++ b/arch/riscv/cpu/fu740/spl.c +@@ -0,0 +1,23 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) 2020 SiFive, Inc ++ * Pragnesh Patel ++ */ ++ ++#include ++#include ++ ++int spl_soc_init(void) ++{ ++ int ret; ++ struct udevice *dev; ++ ++ /* DDR init */ ++ ret = uclass_get_device(UCLASS_RAM, 0, &dev); ++ if (ret) { ++ debug("DRAM init failed: %d\n", ret); ++ return ret; ++ } ++ ++ return 0; ++} +diff --git a/arch/riscv/include/asm/arch-fu740/spl.h b/arch/riscv/include/asm/arch-fu740/spl.h +new file mode 100644 +index 0000000..4697279 +--- /dev/null ++++ b/arch/riscv/include/asm/arch-fu740/spl.h +@@ -0,0 +1,14 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright (C) 2020 SiFive, Inc. ++ * ++ * Authors: ++ * Pragnesh Patel ++ */ ++ ++#ifndef _SPL_SIFIVE_H ++#define _SPL_SIFIVE_H ++ ++int spl_soc_init(void); ++ ++#endif /* _SPL_SIFIVE_H */ +diff --git a/board/sifive/hifive_unmatched_fu740/Kconfig b/board/sifive/hifive_unmatched_fu740/Kconfig +index 3b9b0ae..9857330 100644 +--- a/board/sifive/hifive_unmatched_fu740/Kconfig ++++ b/board/sifive/hifive_unmatched_fu740/Kconfig +@@ -13,12 +13,20 @@ config SYS_CONFIG_NAME + default "sifive-hifive-unmatched-fu740" + + config SYS_TEXT_BASE ++ default 0x80200000 if SPL + default 0x80000000 if !RISCV_SMODE + default 0x80200000 if RISCV_SMODE + ++config SPL_TEXT_BASE ++ default 0x08000000 ++ ++config SPL_OPENSBI_LOAD_ADDR ++ default 0x80000000 ++ + config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select SIFIVE_FU740 ++ select SUPPORT_SPL + imply CMD_DHCP + imply CMD_EXT2 + imply CMD_EXT4 +diff --git a/board/sifive/hifive_unmatched_fu740/Makefile b/board/sifive/hifive_unmatched_fu740/Makefile +index 8f65118..aeab025 100644 +--- a/board/sifive/hifive_unmatched_fu740/Makefile ++++ b/board/sifive/hifive_unmatched_fu740/Makefile +@@ -3,3 +3,7 @@ + # Copyright (c) 2020 SiFive, Inc + + obj-y += hifive-unmatched-fu740.o ++ ++ifdef CONFIG_SPL_BUILD ++obj-y += spl.o ++endif +diff --git a/board/sifive/hifive_unmatched_fu740/spl.c b/board/sifive/hifive_unmatched_fu740/spl.c +new file mode 100644 +index 0000000..d8ee934 +--- /dev/null ++++ b/board/sifive/hifive_unmatched_fu740/spl.c +@@ -0,0 +1,85 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (c) 2020 SiFive, Inc ++ * ++ * Authors: ++ * Pragnesh Patel ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define GEM_PHY_RESET SIFIVE_GENERIC_GPIO_NR(0, 12) ++ ++#define MODE_SELECT_REG 0x1000 ++#define MODE_SELECT_SD 0xb ++#define MODE_SELECT_MASK GENMASK(3, 0) ++ ++int spl_board_init_f(void) ++{ ++ int ret; ++ ++ ret = spl_soc_init(); ++ if (ret) { ++ debug("HiFive Unmatched FU740 SPL init failed: %d\n", ret); ++ return ret; ++ } ++ ++ /* ++ * GEMGXL init VSC8541 PHY reset sequence; ++ * leave pull-down active for 2ms ++ */ ++ udelay(2000); ++ ret = gpio_request(GEM_PHY_RESET, "gem_phy_reset"); ++ if (ret) { ++ debug("gem_phy_reset gpio request failed: %d\n", ret); ++ return ret; ++ } ++ ++ /* Set GPIO 12 (PHY NRESET) */ ++ ret = gpio_direction_output(GEM_PHY_RESET, 1); ++ if (ret) { ++ debug("gem_phy_reset gpio direction set failed: %d\n", ret); ++ return ret; ++ } ++ ++ udelay(1); ++ ++ /* Reset PHY again to enter unmanaged mode */ ++ gpio_set_value(GEM_PHY_RESET, 0); ++ udelay(1); ++ gpio_set_value(GEM_PHY_RESET, 1); ++ mdelay(15); ++ ++ return 0; ++} ++ ++u32 spl_boot_device(void) ++{ ++ u32 mode_select = readl((void *)MODE_SELECT_REG); ++ u32 boot_device = mode_select & MODE_SELECT_MASK; ++ ++ switch (boot_device) { ++ case MODE_SELECT_SD: ++ return BOOT_DEVICE_MMC1; ++ default: ++ debug("Unsupported boot device 0x%x but trying MMC1\n", ++ boot_device); ++ return BOOT_DEVICE_MMC1; ++ } ++} ++ ++#ifdef CONFIG_SPL_LOAD_FIT ++int board_fit_config_name_match(const char *name) ++{ ++ /* boot using first FIT config */ ++ return 0; ++} ++#endif +diff --git a/include/configs/sifive-hifive-unmatched-fu740.h b/include/configs/sifive-hifive-unmatched-fu740.h +index dc75d25..59088a0 100644 +--- a/include/configs/sifive-hifive-unmatched-fu740.h ++++ b/include/configs/sifive-hifive-unmatched-fu740.h +@@ -11,6 +11,20 @@ + + #include + ++#ifdef CONFIG_SPL ++ ++#define CONFIG_SPL_MAX_SIZE 0x00100000 ++#define CONFIG_SPL_BSS_START_ADDR 0x85000000 ++#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 ++#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ ++ CONFIG_SPL_BSS_MAX_SIZE) ++#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 ++ ++#define CONFIG_SPL_STACK (0x08000000 + 0x001D0000 - \ ++ GENERATED_GBL_DATA_SIZE) ++ ++#endif ++ + #define CONFIG_SYS_SDRAM_BASE 0x80000000 + #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) + +@@ -24,6 +38,7 @@ + + /* Environment options */ + ++#ifndef CONFIG_SPL_BUILD + #define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(DHCP, dhcp, na) +@@ -43,5 +58,6 @@ + #define CONFIG_PREBOOT \ + "setenv fdt_addr ${fdtcontroladdr};" \ + "fdt addr ${fdtcontroladdr};" ++#endif /* CONFIG_SPL_BUILD */ + + #endif /* __SIFIVE_HIFIVE_UNMATCHED_FU740_H */ +-- +2.7.4 + diff -Nru u-boot-2021.01+dfsg/debian/patches/riscv64/0019-sifive-hifive_unmatched_fu740-Add-sample-SD-gpt-part.patch u-boot-2021.01+dfsg/debian/patches/riscv64/0019-sifive-hifive_unmatched_fu740-Add-sample-SD-gpt-part.patch --- u-boot-2021.01+dfsg/debian/patches/riscv64/0019-sifive-hifive_unmatched_fu740-Add-sample-SD-gpt-part.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/riscv64/0019-sifive-hifive_unmatched_fu740-Add-sample-SD-gpt-part.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,87 @@ +From 313410edaf2dcd7f2aa327c310ff50729d449333 Mon Sep 17 00:00:00 2001 +From: Pragnesh Patel +Date: Wed, 21 Oct 2020 17:22:32 +0530 +Subject: [PATCH 19/41] sifive: hifive_unmatched_fu740: Add sample SD gpt + partition layout + +This is a sample GPT partition layout for SD card, +right now three important partitions are added to +make the system bootable. + +partition layout: + +Part Start LBA End LBA Name + Attributes + Type GUID + Partition GUID + 1 0x00000022 0x00000821 "loader1" + attrs: 0x0000000000000000 + type: 5b193300-fc78-40cd-8002-e86c45580b47 + guid: cbcbef44-e627-42bc-b134-93b6f3784b8c + 2 0x00000822 0x00002821 "loader2" + attrs: 0x0000000000000000 + type: 2e54b353-1271-4842-806f-e436d6af6985 + guid: f54eba28-d8de-4852-978d-1a673777e2ae + 3 0x00002822 0x00020821 "rootfs" + attrs: 0x0000000000000004 + type: 0fc63daf-8483-4772-8e79-3d69d8477de4 + type: linux + guid: 9561df46-8d55-4799-a83b-cfee9ef6ff93 + +Note: +- loader1 would be spl +- loader2 would be U-Boot or U-Boot proper + +Signed-off-by: Pragnesh Patel +--- + board/sifive/hifive_unmatched_fu740/Kconfig | 2 ++ + include/configs/sifive-hifive-unmatched-fu740.h | 13 +++++++++++++ + 2 files changed, 15 insertions(+) + +diff --git a/board/sifive/hifive_unmatched_fu740/Kconfig b/board/sifive/hifive_unmatched_fu740/Kconfig +index 9857330..19b6413 100644 +--- a/board/sifive/hifive_unmatched_fu740/Kconfig ++++ b/board/sifive/hifive_unmatched_fu740/Kconfig +@@ -32,6 +32,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy + imply CMD_EXT4 + imply CMD_FAT + imply CMD_FS_GENERIC ++ imply CMD_GPT ++ imply PARTITION_TYPE_GUID + imply CMD_NET + imply CMD_PING + imply CMD_SF +diff --git a/include/configs/sifive-hifive-unmatched-fu740.h b/include/configs/sifive-hifive-unmatched-fu740.h +index 59088a0..d3fc373 100644 +--- a/include/configs/sifive-hifive-unmatched-fu740.h ++++ b/include/configs/sifive-hifive-unmatched-fu740.h +@@ -45,6 +45,15 @@ + + #include + ++#define TYPE_GUID_LOADER1 "5B193300-FC78-40CD-8002-E86C45580B47" ++#define TYPE_GUID_LOADER2 "2E54B353-1271-4842-806F-E436D6AF6985" ++#define TYPE_GUID_SYSTEM "0FC63DAF-8483-4772-8E79-3D69D8477DE4" ++ ++#define PARTS_DEFAULT \ ++ "name=loader1,start=17K,size=1M,type=${type_guid_gpt_loader1};" \ ++ "name=loader2,size=4MB,type=${type_guid_gpt_loader2};" \ ++ "name=system,size=-,bootable,type=${type_guid_gpt_system};" ++ + #define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ +@@ -53,6 +62,10 @@ + "scriptaddr=0x88100000\0" \ + "pxefile_addr_r=0x88200000\0" \ + "ramdisk_addr_r=0x88300000\0" \ ++ "type_guid_gpt_loader1=" TYPE_GUID_LOADER1 "\0" \ ++ "type_guid_gpt_loader2=" TYPE_GUID_LOADER2 "\0" \ ++ "type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \ ++ "partitions=" PARTS_DEFAULT "\0" \ + BOOTENV + + #define CONFIG_PREBOOT \ +-- +2.7.4 + diff -Nru u-boot-2021.01+dfsg/debian/patches/riscv64/0020-sifive-fu740-Add-U-Boot-proper-sector-start.patch u-boot-2021.01+dfsg/debian/patches/riscv64/0020-sifive-fu740-Add-U-Boot-proper-sector-start.patch --- u-boot-2021.01+dfsg/debian/patches/riscv64/0020-sifive-fu740-Add-U-Boot-proper-sector-start.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/riscv64/0020-sifive-fu740-Add-U-Boot-proper-sector-start.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,43 @@ +From 38aad675ad72d46faf4d4fc5af65b6a96fd81c4b Mon Sep 17 00:00:00 2001 +From: Pragnesh Patel +Date: Wed, 21 Oct 2020 17:26:24 +0530 +Subject: [PATCH 20/41] sifive: fu740: Add U-Boot proper sector start + +Add U-Boot proper sector start offset for SiFive FU740. +This value is based on the partition layout supported +by SiFive FU740. + +u-boot.itb need to write on this specific offset so-that +the SPL will retrieve it from here and load. + +Signed-off-by: Pragnesh Patel +--- + common/spl/Kconfig | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +diff --git a/common/spl/Kconfig b/common/spl/Kconfig +index d8086bd..e78c1f5 100644 +--- a/common/spl/Kconfig ++++ b/common/spl/Kconfig +@@ -308,7 +308,8 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR + ARCH_MX6 || ARCH_MX7 || \ + ARCH_ROCKCHIP || ARCH_MVEBU || ARCH_SOCFPGA || \ + ARCH_AT91 || ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || \ +- OMAP44XX || OMAP54XX || AM33XX || AM43XX || TARGET_SIFIVE_FU540 ++ OMAP44XX || OMAP54XX || AM33XX || AM43XX || TARGET_SIFIVE_FU540 || \ ++ TARGET_SIFIVE_HIFIVE_UNMATCHED_FU740 + help + Use sector number for specifying U-Boot location on MMC/SD in + raw mode. +@@ -325,7 +326,7 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR + default 0x300 if ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || OMAP44XX || \ + OMAP54XX || AM33XX || AM43XX || ARCH_K3 + default 0x4000 if ARCH_ROCKCHIP +- default 0x822 if TARGET_SIFIVE_FU540 ++ default 0x822 if TARGET_SIFIVE_FU540 || TARGET_SIFIVE_HIFIVE_UNMATCHED_FU740 + help + Address on the MMC to load U-Boot from, when the MMC is being used + in raw mode. Units: MMC sectors (1 sector = 512 bytes). +-- +2.7.4 + diff -Nru u-boot-2021.01+dfsg/debian/patches/riscv64/0021-configs-hifive_unmatched_fu740-Add-config-options-fo.patch u-boot-2021.01+dfsg/debian/patches/riscv64/0021-configs-hifive_unmatched_fu740-Add-config-options-fo.patch --- u-boot-2021.01+dfsg/debian/patches/riscv64/0021-configs-hifive_unmatched_fu740-Add-config-options-fo.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/riscv64/0021-configs-hifive_unmatched_fu740-Add-config-options-fo.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,52 @@ +From 5f116fff54e6c11a3e6b0462056019c353cce742 Mon Sep 17 00:00:00 2001 +From: Pragnesh Patel +Date: Wed, 21 Oct 2020 17:41:18 +0530 +Subject: [PATCH 21/41] configs: hifive_unmatched_fu740: Add config options for + U-Boot SPL + +With u-boot-spl.bin, +u-boot-spl.bin->FIT image (opensbi + U-Boot proper + dtb) + +U-Boot SPL will be loaded by ZSBL from SD card and runs in +L2 LIM in machine mode and then load FIT image u-boot.itb +from SD card into RAM. + +U-Boot SPL expects u-boot.itb FIT image at the starting of SD card sector +number (0x822) of GUID type "2E54B353-1271-4842-806F-E436D6AF6985" + +Signed-off-by: Pragnesh Patel +--- + configs/sifive_hifive_unmatched_fu740_defconfig | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +diff --git a/configs/sifive_hifive_unmatched_fu740_defconfig b/configs/sifive_hifive_unmatched_fu740_defconfig +index 93ceeed..17cc047 100644 +--- a/configs/sifive_hifive_unmatched_fu740_defconfig ++++ b/configs/sifive_hifive_unmatched_fu740_defconfig +@@ -1,12 +1,23 @@ + CONFIG_RISCV=y ++CONFIG_SPL_GPIO_SUPPORT=y ++CONFIG_SYS_MALLOC_F_LEN=0x3000 + CONFIG_NR_DRAM_BANKS=1 ++CONFIG_SPL_DM_SPI=y ++CONFIG_SPL_MMC_SUPPORT=y ++CONFIG_SPL=y ++CONFIG_SPL_SPI_SUPPORT=y + CONFIG_DEFAULT_DEVICE_TREE="hifive-unmatched-a00" + CONFIG_TARGET_SIFIVE_HIFIVE_UNMATCHED_FU740=y + CONFIG_ARCH_RV64I=y + CONFIG_RISCV_SMODE=y + CONFIG_DISTRO_DEFAULTS=y + CONFIG_FIT=y ++CONFIG_SPL_LOAD_FIT_ADDRESS=0x84000000 + CONFIG_DISPLAY_CPUINFO=y + CONFIG_DISPLAY_BOARDINFO=y ++CONFIG_SPL_SEPARATE_BSS=y ++CONFIG_SPL_DM_RESET=y ++CONFIG_SPL_YMODEM_SUPPORT=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_SPL_CLK=y + CONFIG_DM_RESET=y +-- +2.7.4 + diff -Nru u-boot-2021.01+dfsg/debian/patches/riscv64/0022-riscv-sifive-fu540-enable-all-cache-ways-from-U-Boot.patch u-boot-2021.01+dfsg/debian/patches/riscv64/0022-riscv-sifive-fu540-enable-all-cache-ways-from-U-Boot.patch --- u-boot-2021.01+dfsg/debian/patches/riscv64/0022-riscv-sifive-fu540-enable-all-cache-ways-from-U-Boot.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/riscv64/0022-riscv-sifive-fu540-enable-all-cache-ways-from-U-Boot.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,77 @@ +From 8c9f98720814046264c667a07865346cac650715 Mon Sep 17 00:00:00 2001 +From: Pragnesh Patel +Date: Wed, 21 Oct 2020 18:20:14 +0530 +Subject: [PATCH 22/41] riscv: sifive: fu540: enable all cache ways from U-Boot + proper + +Add L2 cache node to enable all cache ways from U-Boot proper. + +Signed-off-by: Pragnesh Patel +--- + arch/riscv/cpu/fu740/cache.c | 54 ++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 54 insertions(+) + create mode 100644 arch/riscv/cpu/fu740/cache.c + +diff --git a/arch/riscv/cpu/fu740/cache.c b/arch/riscv/cpu/fu740/cache.c +new file mode 100644 +index 0000000..347528a +--- /dev/null ++++ b/arch/riscv/cpu/fu740/cache.c +@@ -0,0 +1,54 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) 2020 SiFive, Inc ++ * ++ * Authors: ++ * Pragnesh Patel ++ */ ++ ++#include ++#include ++#include ++ ++/* Register offsets */ ++#define L2_CACHE_CONFIG 0x000 ++#define L2_CACHE_ENABLE 0x008 ++ ++#define MASK_NUM_WAYS GENMASK(15, 8) ++#define NUM_WAYS_SHIFT 8 ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++int cache_enable_ways(void) ++{ ++ const void *blob = gd->fdt_blob; ++ int node; ++ fdt_addr_t base; ++ u32 config; ++ u32 ways; ++ ++ volatile u32 *enable; ++ ++ node = fdt_node_offset_by_compatible(blob, -1, ++ "sifive,fu740-c000-ccache"); ++ ++ if (node < 0) ++ return node; ++ ++ base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0, ++ NULL, false); ++ if (base == FDT_ADDR_T_NONE) ++ return FDT_ADDR_T_NONE; ++ ++ config = readl((volatile u32 *)base + L2_CACHE_CONFIG); ++ ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT; ++ ++ enable = (volatile u32 *)(base + L2_CACHE_ENABLE); ++ ++ /* memory barrier */ ++ mb(); ++ (*enable) = ways - 1; ++ /* memory barrier */ ++ mb(); ++ return 0; ++} +-- +2.7.4 + diff -Nru u-boot-2021.01+dfsg/debian/patches/riscv64/0023-riscv-sifive-dts-fu740-set-ethernet-clock-rate.patch u-boot-2021.01+dfsg/debian/patches/riscv64/0023-riscv-sifive-dts-fu740-set-ethernet-clock-rate.patch --- u-boot-2021.01+dfsg/debian/patches/riscv64/0023-riscv-sifive-dts-fu740-set-ethernet-clock-rate.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/riscv64/0023-riscv-sifive-dts-fu740-set-ethernet-clock-rate.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,29 @@ +From f91820a22ab11bc44c462121994daa28f038d434 Mon Sep 17 00:00:00 2001 +From: Pragnesh Patel +Date: Sat, 31 Oct 2020 19:59:45 +0530 +Subject: [PATCH 23/41] riscv: sifive: dts: fu740: set ethernet clock rate + +Set ethernet clock rate to 125 Mhz so that it will work +with 1000Mbps. + +Signed-off-by: Pragnesh Patel +--- + arch/riscv/dts/fu740-c000-u-boot.dtsi | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/arch/riscv/dts/fu740-c000-u-boot.dtsi b/arch/riscv/dts/fu740-c000-u-boot.dtsi +index 1cc8cd4..88cbaaa 100644 +--- a/arch/riscv/dts/fu740-c000-u-boot.dtsi ++++ b/arch/riscv/dts/fu740-c000-u-boot.dtsi +@@ -94,3 +94,8 @@ + &spi0 { + u-boot,dm-spl; + }; ++ ++ð0 { ++ assigned-clocks = <&prci PRCI_CLK_GEMGXLPLL>; ++ assigned-clock-rates = <126750000>; ++}; +-- +2.7.4 + diff -Nru u-boot-2021.01+dfsg/debian/patches/riscv64/0024-sifive-fu740-set-kernel_comp_addr_r-and-kernel_comp_.patch u-boot-2021.01+dfsg/debian/patches/riscv64/0024-sifive-fu740-set-kernel_comp_addr_r-and-kernel_comp_.patch --- u-boot-2021.01+dfsg/debian/patches/riscv64/0024-sifive-fu740-set-kernel_comp_addr_r-and-kernel_comp_.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/riscv64/0024-sifive-fu740-set-kernel_comp_addr_r-and-kernel_comp_.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,30 @@ +From ef08f93f17b1a76037588bf642c7bd0af2a8df81 Mon Sep 17 00:00:00 2001 +From: David Abdurachmanov +Date: Tue, 12 Jan 2021 20:25:25 +0200 +Subject: [PATCH 24/41] sifive-fu740: set kernel_comp_addr_r and + kernel_comp_size + +These are required for compressed Image.{gz,xz,.} kernel images to work +with booti command. + +Signed-off-by: David Abdurachmanov +--- + include/configs/sifive-hifive-unmatched-fu740.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/include/configs/sifive-hifive-unmatched-fu740.h b/include/configs/sifive-hifive-unmatched-fu740.h +index d3fc373..34d2647 100644 +--- a/include/configs/sifive-hifive-unmatched-fu740.h ++++ b/include/configs/sifive-hifive-unmatched-fu740.h +@@ -62,6 +62,8 @@ + "scriptaddr=0x88100000\0" \ + "pxefile_addr_r=0x88200000\0" \ + "ramdisk_addr_r=0x88300000\0" \ ++ "kernel_comp_addr_r=0x90000000\0" \ ++ "kernel_comp_size=0x4000000\0" \ + "type_guid_gpt_loader1=" TYPE_GUID_LOADER1 "\0" \ + "type_guid_gpt_loader2=" TYPE_GUID_LOADER2 "\0" \ + "type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \ +-- +2.7.4 + diff -Nru u-boot-2021.01+dfsg/debian/patches/riscv64/0025-sifive-fu740-enable-full-L2-cache-ways-16-ways-total.patch u-boot-2021.01+dfsg/debian/patches/riscv64/0025-sifive-fu740-enable-full-L2-cache-ways-16-ways-total.patch --- u-boot-2021.01+dfsg/debian/patches/riscv64/0025-sifive-fu740-enable-full-L2-cache-ways-16-ways-total.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/riscv64/0025-sifive-fu740-enable-full-L2-cache-ways-16-ways-total.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,88 @@ +From 5ce70ea7495d0febaa3671d16add996b49ecc329 Mon Sep 17 00:00:00 2001 +From: David Abdurachmanov +Date: Tue, 12 Jan 2021 20:32:50 +0200 +Subject: [PATCH 25/41] sifive: fu740: enable full L2 cache ways (16 ways + total) + +Linux reports now: + +[..] +[ 2.593562] L2CACHE: Index of the largest way enabled: 15 +[..] + +Signed-off-by: David Abdurachmanov +--- + arch/riscv/cpu/fu740/Makefile | 1 + + arch/riscv/dts/fu740-c000-u-boot.dtsi | 3 +++ + arch/riscv/include/asm/arch-fu740/cache.h | 14 ++++++++++++++ + .../sifive/hifive_unmatched_fu740/hifive-unmatched-fu740.c | 9 ++++++++- + 4 files changed, 26 insertions(+), 1 deletion(-) + create mode 100644 arch/riscv/include/asm/arch-fu740/cache.h + +diff --git a/arch/riscv/cpu/fu740/Makefile b/arch/riscv/cpu/fu740/Makefile +index 043fb96..088205e 100644 +--- a/arch/riscv/cpu/fu740/Makefile ++++ b/arch/riscv/cpu/fu740/Makefile +@@ -8,4 +8,5 @@ obj-y += spl.o + else + obj-y += dram.o + obj-y += cpu.o ++obj-y += cache.o + endif +diff --git a/arch/riscv/dts/fu740-c000-u-boot.dtsi b/arch/riscv/dts/fu740-c000-u-boot.dtsi +index 88cbaaa..ae1d607 100644 +--- a/arch/riscv/dts/fu740-c000-u-boot.dtsi ++++ b/arch/riscv/dts/fu740-c000-u-boot.dtsi +@@ -99,3 +99,6 @@ + assigned-clocks = <&prci PRCI_CLK_GEMGXLPLL>; + assigned-clock-rates = <126750000>; + }; ++&ccache { ++ status = "okay"; ++}; +diff --git a/arch/riscv/include/asm/arch-fu740/cache.h b/arch/riscv/include/asm/arch-fu740/cache.h +new file mode 100644 +index 0000000..135a17c +--- /dev/null ++++ b/arch/riscv/include/asm/arch-fu740/cache.h +@@ -0,0 +1,14 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright (C) 2020 SiFive, Inc. ++ * ++ * Authors: ++ * Pragnesh Patel ++ */ ++ ++#ifndef _CACHE_SIFIVE_H ++#define _CACHE_SIFIVE_H ++ ++int cache_enable_ways(void); ++ ++#endif /* _CACHE_SIFIVE_H */ +diff --git a/board/sifive/hifive_unmatched_fu740/hifive-unmatched-fu740.c b/board/sifive/hifive_unmatched_fu740/hifive-unmatched-fu740.c +index febfa51..361bfbf 100644 +--- a/board/sifive/hifive_unmatched_fu740/hifive-unmatched-fu740.c ++++ b/board/sifive/hifive_unmatched_fu740/hifive-unmatched-fu740.c +@@ -8,10 +8,17 @@ + + #include + #include ++#include + + int board_init(void) + { +- /* For now nothing to do here. */ ++ int ret; + ++ /* enable all cache ways */ ++ ret = cache_enable_ways(); ++ if (ret) { ++ debug("%s: could not enable cache ways\n", __func__); ++ return ret; ++ } + return 0; + } +-- +2.7.4 + diff -Nru u-boot-2021.01+dfsg/debian/patches/riscv64/0026-sifive-fu740-fix-cache-controller-signals-order.patch u-boot-2021.01+dfsg/debian/patches/riscv64/0026-sifive-fu740-fix-cache-controller-signals-order.patch --- u-boot-2021.01+dfsg/debian/patches/riscv64/0026-sifive-fu740-fix-cache-controller-signals-order.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/riscv64/0026-sifive-fu740-fix-cache-controller-signals-order.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,30 @@ +From 1b4e3ab010b04dfe2142e03854b92dc55a2b5a09 Mon Sep 17 00:00:00 2001 +From: David Abdurachmanov +Date: Tue, 12 Jan 2021 20:36:24 +0200 +Subject: [PATCH 26/41] sifive: fu740: fix cache controller signals order + +Cache controller in FU740 compared to FU540 has 4 signals instead of 3. +DirFail is the last one. Signals are wired differently in FU740 thus +the change in the order is required. + +Signed-off-by: David Abdurachmanov +--- + arch/riscv/dts/fu740-c000.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/dts/fu740-c000.dtsi b/arch/riscv/dts/fu740-c000.dtsi +index ee0ab3f..72564c2 100644 +--- a/arch/riscv/dts/fu740-c000.dtsi ++++ b/arch/riscv/dts/fu740-c000.dtsi +@@ -271,7 +271,7 @@ + cache-size = <2097152>; + cache-unified; + interrupt-parent = <&plic0>; +- interrupts = <19 20 21 22>; ++ interrupts = <19 21 22 20>; + reg = <0x0 0x2010000 0x0 0x1000>; + }; + gpio: gpio@10060000 { +-- +2.7.4 + diff -Nru u-boot-2021.01+dfsg/debian/patches/riscv64/0027-sifive-fu740-change-eth0-assigned-clock-rates-to-125.patch u-boot-2021.01+dfsg/debian/patches/riscv64/0027-sifive-fu740-change-eth0-assigned-clock-rates-to-125.patch --- u-boot-2021.01+dfsg/debian/patches/riscv64/0027-sifive-fu740-change-eth0-assigned-clock-rates-to-125.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/riscv64/0027-sifive-fu740-change-eth0-assigned-clock-rates-to-125.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,73 @@ +From 1ae57dee4f5457f90911d0b98a0bfb5fa2ec1700 Mon Sep 17 00:00:00 2001 +From: David Abdurachmanov +Date: Tue, 23 Feb 2021 06:16:17 -0800 +Subject: [PATCH 27/41] sifive: fu740: change eth0 assigned-clock-rates to + 125125000 + +GEMGXL PLL cannot generate required 125 000 000 Hz clock precisely + +Signed-off-by: David Abdurachmanov +--- + arch/riscv/dts/fu740-c000-u-boot.dtsi | 2 +- + arch/riscv/dts/fu740-c000.dtsi | 2 +- + drivers/net/macb.c | 11 ++++++++--- + 3 files changed, 10 insertions(+), 5 deletions(-) + +diff --git a/arch/riscv/dts/fu740-c000-u-boot.dtsi b/arch/riscv/dts/fu740-c000-u-boot.dtsi +index ae1d607..2817b6d 100644 +--- a/arch/riscv/dts/fu740-c000-u-boot.dtsi ++++ b/arch/riscv/dts/fu740-c000-u-boot.dtsi +@@ -97,7 +97,7 @@ + + ð0 { + assigned-clocks = <&prci PRCI_CLK_GEMGXLPLL>; +- assigned-clock-rates = <126750000>; ++ assigned-clock-rates = <125125000>; + }; + &ccache { + status = "okay"; +diff --git a/arch/riscv/dts/fu740-c000.dtsi b/arch/riscv/dts/fu740-c000.dtsi +index 72564c2..c5964a6 100644 +--- a/arch/riscv/dts/fu740-c000.dtsi ++++ b/arch/riscv/dts/fu740-c000.dtsi +@@ -232,7 +232,7 @@ + status = "disabled"; + }; + eth0: ethernet@10090000 { +- compatible = "sifive,fu540-c000-gem"; ++ compatible = "sifive,fu740-c000-gem"; + interrupt-parent = <&plic0>; + interrupts = <55>; + reg = <0x0 0x10090000 0x0 0x2000 +diff --git a/drivers/net/macb.c b/drivers/net/macb.c +index b80a259..179477a 100644 +--- a/drivers/net/macb.c ++++ b/drivers/net/macb.c +@@ -515,7 +515,12 @@ static int macb_sifive_clk_init(struct udevice *dev, ulong rate) + * and output clock on GMII output signal GTX_CLK + * 1 = MII mode. Use MII input signal TX_CLK in TX logic + */ +- writel(rate != 125000000, gemgxl_regs); ++ if (device_is_compatible(dev, "sifive,fu540-c000-gem")) { ++ writel(rate != 125000000, gemgxl_regs); ++ } else if (device_is_compatible(dev, "sifive,fu740-c000-gem")) { ++ writel(rate != 125125000, gemgxl_regs); ++ } ++ + return 0; + } + +@@ -1322,8 +1327,8 @@ static const struct udevice_id macb_eth_ids[] = { + { .compatible = "atmel,sama5d3-gem" }, + { .compatible = "atmel,sama5d4-gem", .data = (ulong)&sama5d4_config }, + { .compatible = "cdns,zynq-gem" }, +- { .compatible = "sifive,fu540-c000-gem", +- .data = (ulong)&sifive_config }, ++ { .compatible = "sifive,fu540-c000-gem", .data = (ulong)&sifive_config }, ++ { .compatible = "sifive,fu740-c000-gem", .data = (ulong)&sifive_config }, + { } + }; + +-- +2.7.4 + diff -Nru u-boot-2021.01+dfsg/debian/patches/riscv64/0028-sifive-hifive_unmatched_fu740-Enable-64bit-PCI-resou.patch u-boot-2021.01+dfsg/debian/patches/riscv64/0028-sifive-hifive_unmatched_fu740-Enable-64bit-PCI-resou.patch --- u-boot-2021.01+dfsg/debian/patches/riscv64/0028-sifive-hifive_unmatched_fu740-Enable-64bit-PCI-resou.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/riscv64/0028-sifive-hifive_unmatched_fu740-Enable-64bit-PCI-resou.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,30 @@ +From 9ac67e3beb37730bf565c8fe6af32bcd791818b4 Mon Sep 17 00:00:00 2001 +From: Green Wan +Date: Mon, 18 Jan 2021 00:28:45 -0800 +Subject: [PATCH 28/41] sifive: hifive_unmatched_fu740: Enable 64bit PCI + resources + +Enable 64bit PCI resources support to avoid address is truncated in +new u-boot code. + +Signed-off-by: Green Wan +--- + include/configs/sifive-hifive-unmatched-fu740.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/include/configs/sifive-hifive-unmatched-fu740.h b/include/configs/sifive-hifive-unmatched-fu740.h +index 34d2647..30458d2 100644 +--- a/include/configs/sifive-hifive-unmatched-fu740.h ++++ b/include/configs/sifive-hifive-unmatched-fu740.h +@@ -36,6 +36,8 @@ + + #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 + ++#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit resources */ ++ + /* Environment options */ + + #ifndef CONFIG_SPL_BUILD +-- +2.7.4 + diff -Nru u-boot-2021.01+dfsg/debian/patches/riscv64/0029-clk-sifive-add-pciaux-clock.patch u-boot-2021.01+dfsg/debian/patches/riscv64/0029-clk-sifive-add-pciaux-clock.patch --- u-boot-2021.01+dfsg/debian/patches/riscv64/0029-clk-sifive-add-pciaux-clock.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/riscv64/0029-clk-sifive-add-pciaux-clock.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,120 @@ +From 9d0d30253299f61a96f9ed59dfd2ed3ddaacf7fd Mon Sep 17 00:00:00 2001 +From: Green Wan +Date: Fri, 15 Jan 2021 23:08:48 +0800 +Subject: [PATCH 29/41] clk: sifive: add pciaux clock + +pciaux clock has no parent and divider. Overwrite the default +clock enable function in sifive_prci.c + +Signed-off-by: Green Wan +--- + drivers/clk/sifive/fu740-prci.c | 31 +++++++++++++++++++++++++++ + drivers/clk/sifive/fu740-prci.h | 2 +- + drivers/clk/sifive/sifive-prci.h | 5 +++++ + include/dt-bindings/clock/sifive-fu740-prci.h | 1 + + 4 files changed, 38 insertions(+), 1 deletion(-) + +diff --git a/drivers/clk/sifive/fu740-prci.c b/drivers/clk/sifive/fu740-prci.c +index 218029b..32b0f40 100644 +--- a/drivers/clk/sifive/fu740-prci.c ++++ b/drivers/clk/sifive/fu740-prci.c +@@ -18,6 +18,23 @@ + + #include + #include "sifive-prci.h" ++#include ++ ++int sifive_prci_fu740_pciauxclk_enable(struct __prci_clock *pc, bool enable) ++{ ++ struct __prci_wrpll_data *pwd = pc->pwd; ++ struct __prci_data *pd = pc->pd; ++ u32 v; ++ ++ if (pwd->cfg1_offs != PRCI_PCIEAUXCFG1_OFFSET) ++ return -EINVAL; ++ ++ v = readl(pd->va + pwd->cfg1_offs); ++ v = enable ? (v | PRCI_PCIEAUXCFG1_MASK) : (v & ~PRCI_PCIEAUXCFG1_MASK); ++ writel(v, pd->va + pwd->cfg1_offs); ++ ++ return 0; ++} + + /* PRCI integration data for each WRPLL instance */ + static struct __prci_wrpll_data __prci_corepll_data = { +@@ -59,6 +76,10 @@ static struct __prci_wrpll_data __prci_cltxpll_data = { + .release_reset = sifive_prci_cltx_release_reset, + }; + ++static struct __prci_wrpll_data __prci_pcieaux_data = { ++ .cfg1_offs = PRCI_PCIEAUXCFG1_OFFSET, ++}; ++ + /* Linux clock framework integration */ + + static const struct __prci_clock_ops sifive_fu740_prci_wrpll_clk_ops = { +@@ -76,6 +97,10 @@ static const struct __prci_clock_ops sifive_fu740_prci_hfpclkplldiv_clk_ops = { + .recalc_rate = sifive_prci_hfpclkplldiv_recalc_rate, + }; + ++static const struct __prci_clock_ops sifive_fu740_prci_pcieaux_clk_ops = { ++ .enable_clk = sifive_prci_fu740_pciauxclk_enable, ++}; ++ + /* List of clock controls provided by the PRCI */ + struct __prci_clock __prci_init_clocks_fu740[] = { + [PRCI_CLK_COREPLL] = { +@@ -124,4 +149,10 @@ struct __prci_clock __prci_init_clocks_fu740[] = { + .parent_name = "hfpclkpll", + .ops = &sifive_fu740_prci_hfpclkplldiv_clk_ops, + }, ++ [PRCI_CLK_PCIEAUX] { ++ .name = "pciaux", ++ .parent_name = "", ++ .ops = &sifive_fu740_prci_pcieaux_clk_ops, ++ .pwd = &__prci_pcieaux_data, ++ } + }; +diff --git a/drivers/clk/sifive/fu740-prci.h b/drivers/clk/sifive/fu740-prci.h +index 4db6b79..ebd1a07 100644 +--- a/drivers/clk/sifive/fu740-prci.h ++++ b/drivers/clk/sifive/fu740-prci.h +@@ -10,7 +10,7 @@ + + #include "sifive-prci.h" + +-#define NUM_CLOCK_FU740 8 ++#define NUM_CLOCK_FU740 9 + + extern struct __prci_clock __prci_init_clocks_fu740[NUM_CLOCK_FU740]; + +diff --git a/drivers/clk/sifive/sifive-prci.h b/drivers/clk/sifive/sifive-prci.h +index af81ff8..cfe6127 100644 +--- a/drivers/clk/sifive/sifive-prci.h ++++ b/drivers/clk/sifive/sifive-prci.h +@@ -67,6 +67,11 @@ + #define PRCI_DDRPLLCFG1_CKE_SHIFT 31 + #define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT) + ++/* PCIEAUXCFG1 */ ++#define PRCI_PCIEAUXCFG1_OFFSET 0x14 ++#define PRCI_PCIEAUXCFG1_SHIFT 0 ++#define PRCI_PCIEAUXCFG1_MASK (0x1 << PRCI_PCIEAUXCFG1_SHIFT) ++ + /* GEMGXLPLLCFG0 */ + #define PRCI_GEMGXLPLLCFG0_OFFSET 0x1c + #define PRCI_GEMGXLPLLCFG0_DIVR_SHIFT 0 +diff --git a/include/dt-bindings/clock/sifive-fu740-prci.h b/include/dt-bindings/clock/sifive-fu740-prci.h +index 6ee4c6d..ed93ec3 100644 +--- a/include/dt-bindings/clock/sifive-fu740-prci.h ++++ b/include/dt-bindings/clock/sifive-fu740-prci.h +@@ -20,5 +20,6 @@ + #define PRCI_CLK_CLTXPLL 5 + #define PRCI_CLK_TLCLK 6 + #define PRCI_CLK_PCLK 7 ++#define PRCI_CLK_PCIEAUX 8 + + #endif +-- +2.7.4 + diff -Nru u-boot-2021.01+dfsg/debian/patches/riscv64/0030-pci-sifive-add-pcie-driver-for-fu740.patch u-boot-2021.01+dfsg/debian/patches/riscv64/0030-pci-sifive-add-pcie-driver-for-fu740.patch --- u-boot-2021.01+dfsg/debian/patches/riscv64/0030-pci-sifive-add-pcie-driver-for-fu740.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/riscv64/0030-pci-sifive-add-pcie-driver-for-fu740.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,1315 @@ +From b8346c052d42fc8aa034e7ebbff1b04c3d8a300c Mon Sep 17 00:00:00 2001 +From: Green Wan +Date: Fri, 15 Jan 2021 23:36:18 +0800 +Subject: [PATCH 30/41] pci: sifive: add pcie driver for fu740 + +Add pcie driver support root complex in Gen1 and depends on fu740 clock, +reset and gpio drivers. + +Tested adapter: + - e1000 compatible network adapter + - SP M.2 PCIe Gen3 SSD + - 2 and 4 ports PCI to USB adapter + +Signed-off-by: Green Wan +--- + arch/riscv/dts/fu740-c000.dtsi | 38 ++ + configs/sifive_hifive_unmatched_fu740_defconfig | 5 + + drivers/pci/Kconfig | 9 + + drivers/pci/Makefile | 1 + + drivers/pci/pcie_sifive.c | 797 ++++++++++++++++++++++++ + drivers/pci/pcie_sifive.h | 374 +++++++++++ + 6 files changed, 1224 insertions(+) + create mode 100644 drivers/pci/pcie_sifive.c + create mode 100644 drivers/pci/pcie_sifive.h + +diff --git a/arch/riscv/dts/fu740-c000.dtsi b/arch/riscv/dts/fu740-c000.dtsi +index c5964a6..7847879 100644 +--- a/arch/riscv/dts/fu740-c000.dtsi ++++ b/arch/riscv/dts/fu740-c000.dtsi +@@ -4,6 +4,7 @@ + /dts-v1/; + + #include ++#include + + / { + #address-cells = <2>; +@@ -158,6 +159,7 @@ + reg = <0x0 0x10000000 0x0 0x1000>; + clocks = <&hfclk>, <&rtcclk>; + #clock-cells = <1>; ++ #reset-cells = <1>; + }; + uart0: serial@10010000 { + compatible = "sifive,fu740-c000-uart", "sifive,uart0"; +@@ -288,5 +290,41 @@ + clocks = <&prci PRCI_CLK_PCLK>; + status = "disabled"; + }; ++ pcie@e00000000 { ++ #address-cells = <3>; ++ #interrupt-cells = <1>; ++ #num-lanes = <8>; ++ #size-cells = <2>; ++ compatible = "sifive,fu740-pcie"; ++ reg = <0xe 0x00000000 0x1 0x0 ++ 0xd 0xf0000000 0x0 0x10000000 ++ 0x0 0x100d0000 0x0 0x1000>; ++ reg-names = "dbi", "config", "mgmt"; ++ device_type = "pci"; ++ dma-coherent; ++ bus-range = <0x0 0xff>; ++ ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000 ++ 0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000 ++ 0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000 ++ 0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; ++ num-lanes = <0x8>; ++ msi-parent = <&plic0>; ++ interrupts = <56 57 58 59 60 61 62 63 64>; ++ interrupt-names = "msi", "inta", "intb", "intc", "intd"; ++ interrupt-parent = <&plic0>; ++ interrupt-map-mask = <0x0 0x0 0x0 0x7>; ++ interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>, ++ <0x0 0x0 0x0 0x2 &plic0 58>, ++ <0x0 0x0 0x0 0x3 &plic0 59>, ++ <0x0 0x0 0x0 0x4 &plic0 60>; ++ pwren-gpios = <&gpio 5 0>; ++ perstn-gpios = <&gpio 8 0>; ++ clocks = <&prci PRCI_CLK_PCIEAUX>; ++ clock-names = "pcieaux"; ++ resets = <&prci PRCI_RST_PCIE_POWER_UP_N>; ++ reset-names = "rst_n"; ++ ++ status = "okay"; ++ }; + }; + }; +diff --git a/configs/sifive_hifive_unmatched_fu740_defconfig b/configs/sifive_hifive_unmatched_fu740_defconfig +index 17cc047..bf274eb 100644 +--- a/configs/sifive_hifive_unmatched_fu740_defconfig ++++ b/configs/sifive_hifive_unmatched_fu740_defconfig +@@ -21,3 +21,8 @@ CONFIG_SPL_YMODEM_SUPPORT=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_SPL_CLK=y + CONFIG_DM_RESET=y ++CONFIG_CMD_PCI=y ++CONFIG_PCI=y ++CONFIG_DM_PCI=y ++CONFIG_PCI_PNP=y ++CONFIG_PCIE_SIFIVE_FU740=y +diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig +index 65498bc..2f221ed 100644 +--- a/drivers/pci/Kconfig ++++ b/drivers/pci/Kconfig +@@ -97,6 +97,15 @@ config PCIE_DW_MVEBU + Armada-8K SoCs. The PCIe controller on Armada-8K is based on + DesignWare hardware. + ++config PCIE_SIFIVE_FU740 ++ bool "Enable SiFive FU740 PCIe" ++ depends on CLK_SIFIVE_PRCI ++ depends on RESET_SIFIVE ++ depends on SIFIVE_GPIO ++ help ++ Say Y here if you want to enable PCIe controller support on ++ FU740. ++ + config PCIE_FSL + bool "FSL PowerPC PCIe support" + depends on DM_PCI +diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile +index 8b4d49a..0b8b278 100644 +--- a/drivers/pci/Makefile ++++ b/drivers/pci/Makefile +@@ -50,3 +50,4 @@ obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o + obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o + obj-$(CONFIG_PCI_BRCMSTB) += pcie_brcmstb.o + obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o ++obj-$(CONFIG_PCIE_SIFIVE_FU740) += pcie_sifive.o +diff --git a/drivers/pci/pcie_sifive.c b/drivers/pci/pcie_sifive.c +new file mode 100644 +index 0000000..70bc2e1 +--- /dev/null ++++ b/drivers/pci/pcie_sifive.c +@@ -0,0 +1,797 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * SiFive FU740 DesignWare PCIe Controller ++ * ++ * Copyright (C) 2020-2021 SiFive, Inc. ++ * ++ * Based in early part on the i.MX6 PCIe host controller shim which is: ++ * ++ * Copyright (C) 2013 Kosagi ++ * http://www.kosagi.com ++ * ++ * Based on driver from author: Alan Mikhak ++ */ ++#include "pcie_sifive.h" ++#include ++#include ++ ++/* Host Bridge Identification */ ++#define DEVICE_NAME "SiFive FU740 PCIe Host Controller" ++#define VENDOR_ID 0x51fe ++#define DEVICE_ID 0x51fe ++ ++static enum pcie_sifive_devtype pcie_sifive_get_devtype(struct pcie_sifive *sv) ++{ ++ u32 val; ++ ++ val = readl(sv->priv.iobase + MGMT_MISC_DEVICE_TYPE_OFFSET); ++ switch (val) { ++ case MGMT_MISC_DEVICE_TYPE_RC: ++ return SV_PCIE_HOST_TYPE; ++ case MGMT_MISC_DEVICE_TYPE_EP: ++ return SV_PCIE_ENDPOINT_TYPE; ++ default: ++ return SV_PCIE_UNKNOWN_TYPE; ++ } ++} ++ ++static void pcie_sifive_priv_set_state(struct pcie_sifive *sv, u32 reg, ++ u32 bits, int state) ++{ ++ u32 val; ++ ++ val = readl(sv->priv.iobase + reg); ++ val = state ? (val | bits) : (val & !bits); ++ writel(val, sv->priv.iobase + reg); ++} ++ ++static void pcie_sifive_assert_perstn(struct pcie_sifive *sv) ++{ ++ dm_gpio_set_value(&sv->perstn_gpio, 0); ++ writel(0x0, sv->priv.iobase + PCIEX8MGMT_PERST_N); ++ mdelay(100); ++} ++ ++static void pcie_sifive_power_on(struct pcie_sifive *sv) ++{ ++ dm_gpio_set_value(&sv->pwren_gpio, 1); ++ mdelay(100); ++} ++ ++static void pcie_sifive_deassert_perstn(struct pcie_sifive *sv) ++{ ++ writel(0x1, sv->priv.iobase + PCIEX8MGMT_PERST_N); ++ dm_gpio_set_value(&sv->perstn_gpio, 1); ++ mdelay(100); ++} ++ ++static int pcie_sifive_setphy(const u8 phy, const u8 write, ++ const u16 addr, const u16 wrdata, ++ u16 *rddata, struct pcie_sifive *sv) ++{ ++ unsigned char ack = 0; ++ ++ if (!(phy == 0 || phy == 1)) ++ return -2; ++ ++ /* setup phy para */ ++ writel(addr, sv->priv.iobase + ++ (phy ? PCIEX8MGMT_PHY1_CR_PARA_ADDR : ++ PCIEX8MGMT_PHY0_CR_PARA_ADDR)); ++ ++ if (write) ++ writel(wrdata, sv->priv.iobase + ++ (phy ? PCIEX8MGMT_PHY1_CR_PARA_WR_DATA : ++ PCIEX8MGMT_PHY0_CR_PARA_WR_DATA)); ++ ++ /* enable access if write */ ++ if (write) ++ writel(1, sv->priv.iobase + ++ (phy ? PCIEX8MGMT_PHY1_CR_PARA_WR_EN : ++ PCIEX8MGMT_PHY0_CR_PARA_WR_EN)); ++ else ++ writel(1, sv->priv.iobase + ++ (phy ? PCIEX8MGMT_PHY1_CR_PARA_RD_EN : ++ PCIEX8MGMT_PHY0_CR_PARA_RD_EN)); ++ ++ /* wait for wait_idle */ ++ do { ++ u32 val; ++ ++ val = readl(sv->priv.iobase + ++ (phy ? PCIEX8MGMT_PHY1_CR_PARA_ACK : ++ PCIEX8MGMT_PHY0_CR_PARA_ACK)); ++ if (val) { ++ ack = 1; ++ if (!write) ++ readl(sv->priv.iobase + ++ (phy ? PCIEX8MGMT_PHY1_CR_PARA_RD_DATA : ++ PCIEX8MGMT_PHY0_CR_PARA_RD_DATA)); ++ mdelay(1); ++ } ++ } while (!ack); ++ ++ /* clear */ ++ if (write) ++ writel(0, sv->priv.iobase + ++ (phy ? PCIEX8MGMT_PHY1_CR_PARA_WR_EN : ++ PCIEX8MGMT_PHY0_CR_PARA_WR_EN)); ++ else ++ writel(0, sv->priv.iobase + ++ (phy ? PCIEX8MGMT_PHY1_CR_PARA_RD_EN : ++ PCIEX8MGMT_PHY0_CR_PARA_RD_EN)); ++ ++ while (readl(sv->priv.iobase + ++ (phy ? PCIEX8MGMT_PHY1_CR_PARA_ACK : ++ PCIEX8MGMT_PHY0_CR_PARA_ACK))) { ++ /* wait for ~wait_idle */ ++ } ++ ++ return 0; ++} ++ ++static void pcie_sifive_init_phy(struct pcie_sifive *sv) ++{ ++ int lane; ++ ++ /* enable phy cr_para_sel interfaces */ ++ writel(0x1, sv->priv.iobase + PCIEX8MGMT_PHY0_CR_PARA_SEL); ++ writel(0x1, sv->priv.iobase + PCIEX8MGMT_PHY1_CR_PARA_SEL); ++ mdelay(1); ++ ++ /* set PHY AC termination mode */ ++ for (lane = 0; lane < PCIEX8MGMT_LANE_NUM; lane++) { ++ pcie_sifive_setphy(0, 1, ++ PCIEX8MGMT_LANE + ++ (PCIEX8MGMT_LANE_OFF * lane), ++ PCIEX8MGMT_TERM_MODE, NULL, sv); ++ pcie_sifive_setphy(1, 1, ++ PCIEX8MGMT_LANE + ++ (PCIEX8MGMT_LANE_OFF * lane), ++ PCIEX8MGMT_TERM_MODE, NULL, sv); ++ } ++} ++ ++static void pcie_sifive_set_pci_int_pin(struct pcie_sifive *sv, ++ enum pci_interrupt_pin pin) ++{ ++ u32 val; ++ ++ /* ctrl_ro_wr_enable */ ++ val = readl(sv->ctrl.iobase + PCIE_MISC_CONTROL_1); ++ val |= DBI_RO_WR_EN; ++ writel(val, sv->ctrl.iobase + PCIE_MISC_CONTROL_1); ++ ++ writeb(pin, sv->ctrl.iobase + PCI_CONFIG(PCI_INTERRUPT_PIN)); ++ ++ /* ctrl_ro_wr_disable */ ++ val &= ~DBI_RO_WR_EN; ++ writel(val, sv->ctrl.iobase + PCIE_MISC_CONTROL_1); ++} ++ ++static int pcie_sifive_get_property(struct pcie_sifive *sv, ++ const char *property) ++{ ++ u32 value = 0; ++ ++ if (dev_read_u32(sv->pci.dev, property, &value)) ++ return 0; ++ ++ return value; ++} ++ ++static int pcie_sifive_get_required_property(struct pcie_sifive *sv, ++ const char *property) ++{ ++ int value; ++ ++ value = pcie_sifive_get_property(sv, property); ++ if (value == -EINVAL) ++ sv_err(sv, "Unable to read %s property\n", property); ++ ++ return value; ++} ++ ++static u32 pcie_sifive_get_link_width_mask(struct pcie_sifive *sv, int lanes) ++{ ++ switch (lanes) { ++ case 1: return LINK_WIDTH_1_LANE; ++ case 2: return LINK_WIDTH_2_LANES; ++ case 4: return LINK_WIDTH_4_LANES; ++ case 8: return LINK_WIDTH_8_LANES; ++ default: return 0; ++ } ++} ++ ++static u32 pcie_sifive_get_link_lanes_mask(struct pcie_sifive *sv, int lanes) ++{ ++ switch (lanes) { ++ case 1: return LINK_MODE_1_LANE; ++ case 2: return LINK_MODE_2_LANES; ++ case 4: return LINK_MODE_4_LANES; ++ case 8: return LINK_MODE_8_LANES; ++ default: return 0; ++ } ++} ++ ++static void pcie_sifive_set_link_num_lanes(struct pcie_sifive *sv, int lanes) ++{ ++ u32 mode; ++ ++ mode = pcie_sifive_get_link_lanes_mask(sv, lanes); ++ if (mode) { ++ u32 val; ++ ++ val = readl(sv->ctrl.iobase + LINK_CONTROL); ++ val &= ~LINK_MODE_MASK; ++ val |= mode; ++ writel(val, sv->ctrl.iobase + LINK_CONTROL); ++ } ++} ++ ++static void pcie_sifive_set_link_width(struct pcie_sifive *sv, int lanes) ++{ ++ u32 lwidth; ++ ++ lwidth = pcie_sifive_get_link_width_mask(sv, lanes); ++ if (lwidth) { ++ u32 val; ++ ++ val = readl(sv->ctrl.iobase + LINK_WIDTH_SPEED_CONTROL); ++ val &= ~LINK_WIDTH_MASK; ++ val |= lwidth; ++ writel(val, sv->ctrl.iobase + LINK_WIDTH_SPEED_CONTROL); ++ } ++} ++ ++static int pcie_sifive_check_link(struct pcie_sifive *sv) ++{ ++ u32 val; ++ ++ val = readl(sv->ctrl.iobase + PHY_DEBUG_R1); ++ return (val & PHY_DEBUG_R1_LINK_UP) && ++ !(val & PHY_DEBUG_R1_LINK_IN_TRAINING); ++} ++ ++static void pcie_sifive_force_gen1(struct pcie_sifive *sv) ++{ ++ u32 val, linkcap; ++ ++ /* ++ * Force Gen1 operation when starting the link. In case the link is ++ * started in Gen2 mode, there is a possibility the devices on the ++ * bus will not be detected at all. This happens with PCIe switches. ++ */ ++ ++ /* ctrl_ro_wr_enable */ ++ val = readl(sv->ctrl.iobase + PCIE_MISC_CONTROL_1); ++ val |= DBI_RO_WR_EN; ++ writel(val, sv->ctrl.iobase + PCIE_MISC_CONTROL_1); ++ ++ /* configure link cap */ ++ linkcap = readl(sv->ctrl.iobase + PF0_PCIE_CAP_LINK_CAP); ++ linkcap |= PCIE_LINK_CAP_MAX_SPEED_MASK; ++ writel(linkcap, sv->ctrl.iobase + PF0_PCIE_CAP_LINK_CAP); ++ ++ /* ctrl_ro_wr_disable */ ++ val &= ~DBI_RO_WR_EN; ++ writel(val, sv->ctrl.iobase + PCIE_MISC_CONTROL_1); ++} ++ ++static void pcie_sifive_print_phy_debug(struct pcie_sifive *sv) ++{ ++ sv_err(sv, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n", ++ readl(sv->ctrl.iobase + PHY_DEBUG_R0), ++ readl(sv->ctrl.iobase + PHY_DEBUG_R1)); ++} ++ ++static int pcie_sifive_set_check_atu(struct pcie_sifive *sv, u32 region) ++{ ++ u32 retries, val; ++ ++ /* ++ * Make sure ATU enable takes effect before any subsequent config ++ * and I/O accesses. ++ */ ++ for (retries = 0; retries < ATU_WAIT_MAX_RETRIES; retries++) { ++ val = readl(sv->ctrl.iobase + region + ATU_REGION_CTRL2); ++ if (val & ATU_ENABLE) ++ return 0; ++ ++ mdelay(ATU_WAIT); ++ } ++ ++ return -EBUSY; ++} ++ ++static void pcie_sifive_set_atu(struct pcie_sifive *sv, u32 region, ++ u32 ctrl1, u32 ctrl2, u64 size, ++ u64 base_addr, u64 target_addr) ++{ ++ u64 limit_addr = base_addr + size - 1; ++ ++ if (upper_32_bits(size)) ++ ctrl1 |= ATU_INCREASE_REGION_SIZE; ++ ++ writel(lower_32_bits(base_addr), ++ sv->ctrl.iobase + region + ATU_LOWER_BASE); ++ writel(upper_32_bits(base_addr), ++ sv->ctrl.iobase + region + ATU_UPPER_BASE); ++ writel(lower_32_bits(limit_addr), ++ sv->ctrl.iobase + region + ATU_LOWER_LIMIT); ++ writel(upper_32_bits(limit_addr), ++ sv->ctrl.iobase + region + ATU_UPPER_LIMIT); ++ writel(lower_32_bits(target_addr), ++ sv->ctrl.iobase + region + ATU_LOWER_TARGET); ++ writel(upper_32_bits(target_addr), ++ sv->ctrl.iobase + region + ATU_UPPER_TARGET); ++ writel(ctrl1, sv->ctrl.iobase + region + ATU_REGION_CTRL1); ++ writel(ctrl2 | ATU_ENABLE, sv->ctrl.iobase + region + ATU_REGION_CTRL2); ++} ++ ++static void pcie_sifive_set_outbound_atu(struct pcie_sifive *sv, ++ u32 index, u32 ctrl1, u32 ctrl2, ++ u64 size, u64 cpu_addr, u64 pci_addr) ++{ ++ u32 region = ATU_CONFIG(ATU_OUTBOUND_REGION(index)); ++ ++ pcie_sifive_set_atu(sv, region, ctrl1, ctrl2, size, cpu_addr, pci_addr); ++ ++ if (pcie_sifive_set_check_atu(sv, region)) ++ sv_err(sv, "Outbound ATU could not be enabled\n"); ++} ++ ++static void __iomem *pcie_sifive_cfg_outbound_atu(struct pcie_sifive *sv, ++ u32 bdf, u32 where) ++{ ++ u32 bus, ctrl1; ++ ++ where &= ~0x3; ++ ++ bus = ((bdf >> 16) & 0xff) - sv->pci.pp.root_bus_nr; ++ if (!bus) ++ return sv->ctrl.iobase + PCI_CONFIG(where); ++ ++ if (bus == 1) ++ ctrl1 = ATU_TYPE_CFG0; ++ else ++ ctrl1 = ATU_TYPE_CFG1; ++ ++ bdf = (bus << 16) | (bdf & 0xffff); ++ pcie_sifive_set_outbound_atu(sv, 1, ctrl1, 0, SZ_4K, ++ sv->pci.pp.cfg1_base, ++ (u64)(bdf << 8)); ++ ++ return sv->pci.pp.va_cfg1_base + where; ++} ++ ++static void pcie_sifive_set_outbound_mem_atu(struct pcie_sifive *sv, u32 index, ++ u64 size, u64 cpu_addr, ++ u64 pci_addr) ++{ ++ pcie_sifive_set_outbound_atu(sv, index, ATU_TYPE_MEM, 0, ++ size, cpu_addr, pci_addr); ++} ++ ++static void pcie_sifive_set_outbound_io_atu(struct pcie_sifive *sv, u32 index, ++ u64 size, u64 cpu_addr, ++ u64 pci_addr) ++{ ++ pcie_sifive_set_outbound_atu(sv, index, ATU_TYPE_IO, 0, ++ size, cpu_addr, pci_addr); ++} ++ ++static int pcie_sifive_set_outbound_ecam_atu(struct pcie_sifive *sv, u32 index, ++ u64 cpu_addr) ++{ ++ pcie_sifive_set_outbound_atu(sv, index++, ++ ATU_TYPE_CFG0, ATU_CFG_SHIFT_MODE, ++ SZ_4K, cpu_addr, 0); ++ ++ pcie_sifive_set_outbound_atu(sv, index++, ++ ATU_TYPE_CFG1, ATU_CFG_SHIFT_MODE, ++ SZ_256M - SZ_1M, ++ cpu_addr + SZ_1M, ++ SZ_1M); ++ return index; ++} ++ ++static void pcie_sifive_assert_phy_reset(struct pcie_sifive *sv) ++{ ++ writel(0x1, sv->priv.iobase + PCIEX8MGMT_APP_HOLD_PHY_RST); ++} ++ ++static int pcie_sifive_wait_for_link(struct pcie_sifive *sv) ++{ ++ u32 val; ++ int timeout; ++ ++ /* Wait for the link to train */ ++ mdelay(20); ++ timeout = 20; ++ ++ do { ++ mdelay(1); ++ } while (--timeout && !pcie_sifive_check_link(sv)); ++ ++ val = readl(sv->ctrl.iobase + PHY_DEBUG_R1); ++ if (!(val & PHY_DEBUG_R1_LINK_UP) || ++ (val & PHY_DEBUG_R1_LINK_IN_TRAINING)) { ++ sv_info(sv, "Failed to negotiate PCIe link!\n"); ++ pcie_sifive_print_phy_debug(sv); ++ pcie_sifive_assert_phy_reset(sv); ++ return -ETIMEDOUT; ++ } ++ ++ sv_info(sv, "PCIe Link up, Gen%i\n", ++ readw(sv->ctrl.iobase + PF0_PCIE_CAP_LINK_STATUS) & ++ PCIE_LINK_STATUS_SPEED_MASK); ++ ++ return 0; ++} ++ ++static void pcie_sifive_setup_link(struct pcie_sifive *sv) ++{ ++ u32 lanes; ++ ++ lanes = pcie_sifive_get_required_property(sv, "num-lanes"); ++ if (lanes > 0) { ++ pcie_sifive_set_link_num_lanes(sv, lanes); ++ pcie_sifive_set_link_width(sv, lanes); ++ } ++} ++ ++static int pcie_sifive_start_link(struct pcie_sifive *sv) ++{ ++ if (pcie_sifive_check_link(sv)) ++ return -EALREADY; ++ ++ pcie_sifive_force_gen1(sv); ++ ++ /* set ltssm */ ++ pcie_sifive_priv_set_state(sv, MGMT_MISC_LTSSM_ENABLE_OFFSET, ++ MGMT_MISC_LTSSM_ENABLE_BIT, 1); ++ return 0; ++} ++ ++static void pcie_sifive_setup_host_atu(struct pcie_sifive *sv) ++{ ++ pcie_sifive_set_outbound_mem_atu(sv, 0, ++ sv->pci.pp.mem_size, ++ sv->pci.pp.mem_base, ++ sv->pci.pp.mem_bus_addr); ++ ++ if (sv->pci.num_viewport > 2) ++ pcie_sifive_set_outbound_io_atu(sv, 2, ++ sv->pci.pp.io_size, ++ sv->pci.pp.io_base, ++ sv->pci.pp.io_bus_addr); ++ ++ if (sv->pci.pp.ecam.iobase) ++ pcie_sifive_set_outbound_ecam_atu(sv, 3, ++ (u64)sv->pci.pp.ecam.iobase); ++} ++ ++static void pcie_sifive_setup_host_prefetch(struct pcie_sifive *sv) ++{ ++ u32 val; ++ ++ /* ctrl_ro_wr_enable */ ++ val = readl(sv->ctrl.iobase + PCIE_MISC_CONTROL_1); ++ val |= DBI_RO_WR_EN; ++ writel(val, sv->ctrl.iobase + PCIE_MISC_CONTROL_1); ++ ++ writew(0xf, sv->ctrl.iobase + PCI_CONFIG(PCI_PREF_MEMORY_BASE)); ++ writew(0xf, sv->ctrl.iobase + PCI_CONFIG(PCI_PREF_MEMORY_LIMIT)); ++ writel(0x20, sv->ctrl.iobase + PCI_CONFIG(PCI_PREF_BASE_UPPER32)); ++ writel(0x40, sv->ctrl.iobase + PCI_CONFIG(PCI_PREF_LIMIT_UPPER32)); ++ ++ /* ctrl_ro_wr_disable */ ++ val &= ~DBI_RO_WR_EN; ++ writel(val, sv->ctrl.iobase + PCIE_MISC_CONTROL_1); ++} ++ ++static void pcie_sifive_setup_host(struct pcie_sifive *sv) ++{ ++ u32 val; ++ ++ sv->pci.iatu_unroll_enabled = true; ++ ++ pcie_sifive_setup_link(sv); ++ ++ /* ctrl_ro_wr_enable */ ++ val = readl(sv->ctrl.iobase + PCIE_MISC_CONTROL_1); ++ val |= DBI_RO_WR_EN; ++ writel(val, sv->ctrl.iobase + PCIE_MISC_CONTROL_1); ++ ++ /* Setup correct class code for host bridge */ ++ writew(PCI_CLASS_BRIDGE_PCI, ++ sv->ctrl.iobase + PCI_CONFIG(PCI_CLASS_DEVICE)); ++ ++ /* ctrl_ro_wr_disable */ ++ val &= ~DBI_RO_WR_EN; ++ writel(val, sv->ctrl.iobase + PCIE_MISC_CONTROL_1); ++ ++ writeb(PCI_HEADER_TYPE_BRIDGE, ++ sv->ctrl.iobase + PCI_CONFIG(PCI_HEADER_TYPE)); ++ ++ /* Setup RC BARs */ ++ writel(0x4, sv->ctrl.iobase + PCI_CONFIG(PCI_BASE_ADDRESS_0)); ++ writel(0x0, sv->ctrl.iobase + PCI_CONFIG(PCI_BASE_ADDRESS_1)); ++ ++ pcie_sifive_set_pci_int_pin(sv, PCI_INTERRUPT_INTA); ++ ++ /* Setup bus numbers */ ++ val = readl(sv->ctrl.iobase + PCI_CONFIG(PCI_PRIMARY_BUS)) & ++ ~0x00ffffff; ++ val |= 0x00ff0100; ++ writel(val, sv->ctrl.iobase + PCI_CONFIG(PCI_PRIMARY_BUS)); ++ ++ /* Setup command register */ ++ writew(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | ++ PCI_COMMAND_SERR, sv->ctrl.iobase + PCI_CONFIG(PCI_COMMAND)); ++ ++ pcie_sifive_setup_host_atu(sv); ++ ++ writel(0x0, sv->ctrl.iobase + PCI_CONFIG(PCI_BASE_ADDRESS_0)); ++ ++ pcie_sifive_setup_host_prefetch(sv); ++} ++ ++static int pcie_sifive_init_host(struct pcie_sifive *sv) ++{ ++ pcie_sifive_setup_host(sv); ++ ++ if (pcie_sifive_start_link(sv) == -EALREADY) ++ sv_info(sv, "PCIe link is already up\n"); ++ else if (pcie_sifive_wait_for_link(sv) == -ETIMEDOUT) ++ return -ETIMEDOUT; ++ ++ return 0; ++} ++ ++static int pcie_sifive_addr_valid(struct pcie_sifive *sv, pci_dev_t bdf) ++{ ++ if ((PCI_BUS(bdf) == sv->pci.pp.root_bus_nr) && (PCI_DEV(bdf) > 0)) ++ return 0; ++ if ((PCI_BUS(bdf) == sv->pci.pp.root_bus_nr + 1) && (PCI_DEV(bdf) > 0)) ++ return 0; ++ ++ return 1; ++} ++ ++static int pcie_sifive_read_config(const struct udevice *bus, pci_dev_t bdf, ++ uint offset, ulong *valuep, ++ enum pci_size_t size) ++{ ++ struct pcie_sifive *sv = dev_get_priv(bus); ++ void __iomem *va; ++ ulong value; ++ ++ sv_debug(sv, "PCIe CFG read: (b,d,f)=(%2d,%2d,%2d) ", ++ PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); ++ ++ if (!pcie_sifive_addr_valid(sv, bdf)) { ++ sv_debug(sv, "- out of range\n"); ++ *valuep = pci_get_ff(size); ++ return 0; ++ } ++ ++ va = pcie_sifive_cfg_outbound_atu(sv, bdf, offset); ++ value = readl(va); ++ ++ sv_debug(sv, "(addr,val)=(0x%04x, 0x%08lx)\n", offset, value); ++ *valuep = pci_conv_32_to_size(value, offset, size); ++ ++ if (sv->pci.num_viewport <= 2) ++ pcie_sifive_set_outbound_io_atu(sv, 1, ++ sv->pci.pp.io_size, ++ sv->pci.pp.io_base, ++ sv->pci.pp.io_bus_addr); ++ return 0; ++} ++ ++static int pcie_sifive_write_config(struct udevice *bus, pci_dev_t bdf, ++ uint offset, ulong value, ++ enum pci_size_t size) ++{ ++ struct pcie_sifive *sv = dev_get_priv(bus); ++ void __iomem *va; ++ ulong old; ++ ++ sv_debug(sv, "PCIe CFG write: (b,d,f)=(%2d,%2d,%2d) ", ++ PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); ++ sv_debug(sv, "(addr,val)=(0x%04x, 0x%08lx)\n", offset, value); ++ ++ if (!pcie_sifive_addr_valid(sv, bdf)) { ++ sv_debug(sv, "- out of range\n"); ++ return 0; ++ } ++ ++ va = pcie_sifive_cfg_outbound_atu(sv, bdf, offset); ++ old = readl(va); ++ value = pci_conv_size_to_32(old, value, offset, size); ++ writel(value, va); ++ ++ if (sv->pci.num_viewport <= 2) ++ pcie_sifive_set_outbound_io_atu(sv, 1, ++ sv->pci.pp.io_size, ++ sv->pci.pp.io_base, ++ sv->pci.pp.io_bus_addr); ++ return 0; ++} ++ ++bool pcie_sifive_set_mode(struct pcie_sifive *sv, enum pcie_sifive_devtype mode) ++{ ++ int ret; ++ ++ pcie_sifive_assert_perstn(sv); ++ pcie_sifive_power_on(sv); ++ pcie_sifive_deassert_perstn(sv); ++ ++ clk_enable(&sv->aux_ck); ++ ++ /* ++ * assert hold_phy_rst (hold the controller LTSSM in reset ++ * after power_up_rst_n for register programming with cr_para) ++ */ ++ pcie_sifive_assert_phy_reset(sv); ++ ++ /* deassert power_up_rst_n */ ++ ret = reset_deassert(&sv->reset); ++ if (ret < 0) { ++ pr_err("reset_assert() failed: %d", ret); ++ return false; ++ } ++ ++ pcie_sifive_init_phy(sv); ++ ++ clk_disable(&sv->aux_ck); ++ ++ /* deassert phy reset */ ++ writel(0x0, sv->priv.iobase + PCIEX8MGMT_APP_HOLD_PHY_RST); ++ ++ /* enable pcieauxclk */ ++ clk_enable(&sv->aux_ck); ++ ++ /* Set desired mode while core is not operational */ ++ if (mode == SV_PCIE_HOST_TYPE) ++ writel(MGMT_MISC_DEVICE_TYPE_RC, ++ sv->priv.iobase + MGMT_MISC_DEVICE_TYPE_OFFSET); ++ else ++ writel(MGMT_MISC_DEVICE_TYPE_EP, ++ sv->priv.iobase + MGMT_MISC_DEVICE_TYPE_OFFSET); ++ ++ /* Confirm desired mode from operational core */ ++ if (pcie_sifive_get_devtype(sv) != mode) ++ return false; ++ ++ sv->mode = mode; ++ ++ return true; ++} ++ ++static int pcie_sifive_probe(struct udevice *dev) ++{ ++ struct pcie_sifive *sv = dev_get_priv(dev); ++ struct udevice *parent = pci_get_controller(dev); ++ struct pci_controller *hose = dev_get_uclass_priv(parent); ++ int err; ++ ++ sv->ctrl.iobase = (void __iomem *)sv->ctrl.phys_base; ++ sv->priv.iobase = (void __iomem *)sv->priv.phys_base; ++ ++ sv->pci.dev = dev; ++ sv->pci.pp.root_bus_nr = dev->seq; ++ ++ sv->pci.pp.io_size = hose->regions[0].size; ++ sv->pci.pp.io_base = hose->regions[0].phys_start; ++ sv->pci.pp.io_bus_addr = hose->regions[0].bus_start; ++ ++ sv->pci.pp.mem_size = hose->regions[1].size; ++ sv->pci.pp.mem_base = hose->regions[1].phys_start; ++ sv->pci.pp.mem_bus_addr = hose->regions[1].bus_start; ++ ++ sv->pci.pp.config.iobase = (void __iomem *)sv->pci.pp.config.phys_base; ++ sv->pci.pp.ecam.iobase = (void __iomem *)sv->pci.pp.ecam.phys_base; ++ ++ sv->pci.pp.cfg0_base = sv->pci.pp.config.phys_base; ++ sv->pci.pp.va_cfg0_base = (void __iomem *)sv->pci.pp.cfg0_base; ++ sv->pci.pp.cfg0_size = SZ_4K; ++ ++ sv->pci.pp.cfg1_base = sv->pci.pp.cfg0_base + sv->pci.pp.cfg0_size; ++ sv->pci.pp.va_cfg1_base = (void __iomem *)sv->pci.pp.cfg1_base; ++ sv->pci.pp.cfg1_size = SZ_4K; ++ ++ sv->pci.pp.msi_data = sv->pci.pp.cfg1_base + sv->pci.pp.cfg1_size; ++ ++ gpio_request_by_name(dev, "pwren-gpios", 0, &sv->pwren_gpio, ++ GPIOD_IS_OUT); ++ ++ if (!dm_gpio_is_valid(&sv->pwren_gpio)) { ++ sv_info(sv, "pwren_gpio is invalid\n"); ++ return -EINVAL; ++ } ++ ++ gpio_request_by_name(dev, "perstn-gpios", 0, &sv->perstn_gpio, ++ GPIOD_IS_OUT); ++ ++ if (!dm_gpio_is_valid(&sv->perstn_gpio)) { ++ sv_info(sv, "perstn_gpio is invalid\n"); ++ return -EINVAL; ++ } ++ ++ err = clk_get_by_index(dev, 0, &sv->aux_ck); ++ if (err) { ++ sv_info(sv, "clk_get_by_index(aux_ck) failed: %d\n", err); ++ return err; ++ } ++ ++ err = reset_get_by_index(dev, 0, &sv->reset); ++ if (err) { ++ sv_info(sv, "reset_get_by_index(reset) failed: %d\n", err); ++ return err; ++ } ++ ++ if (!pcie_sifive_set_mode(sv, SV_PCIE_HOST_TYPE)) { ++ sv_info(sv, "Unable to set desired PCIe operation mode\n"); ++ return -EINVAL; ++ } ++ ++ return pcie_sifive_init_host(sv); ++} ++ ++static int pcie_sifive_ofdata_to_platdata(struct udevice *dev) ++{ ++ struct pcie_sifive *sv = dev_get_priv(dev); ++ ++ sv->pci.dev = dev; ++ ++ sv->ctrl.phys_base = dev_read_addr_size_name(dev, "dbi", ++ &sv->ctrl.iosize); ++ if (sv->ctrl.phys_base == FDT_ADDR_T_NONE) ++ return -EINVAL; ++ ++ sv->priv.phys_base = dev_read_addr_size_name(dev, "mgmt", ++ &sv->priv.iosize); ++ if (sv->priv.phys_base == FDT_ADDR_T_NONE) ++ return -EINVAL; ++ ++ sv->pci.pp.config.phys_base = ++ dev_read_addr_size_name(dev, "config", ++ &sv->pci.pp.config.iosize); ++ if (sv->pci.pp.config.phys_base == FDT_ADDR_T_NONE) ++ return -EINVAL; ++ ++ sv->pci.pp.ecam.phys_base = ++ dev_read_addr_size_name(dev, "ecam", &sv->pci.pp.ecam.iosize); ++ if (sv->pci.pp.config.phys_base == FDT_ADDR_T_NONE) ++ sv->pci.pp.ecam.phys_base = 0; ++ ++ sv->pci.num_viewport = pcie_sifive_get_property(sv, "num-viewport"); ++ if (sv->pci.num_viewport == 0) ++ sv->pci.num_viewport = 2; ++ ++ return 0; ++} ++ ++static const struct dm_pci_ops pcie_sifive_ops = { ++ .read_config = pcie_sifive_read_config, ++ .write_config = pcie_sifive_write_config ++}; ++ ++static const struct udevice_id pcie_sifive_ids[] = { ++ { .compatible = "sifive,fu740-pcie" }, ++ { .compatible = "sifive,fu740-pcie-ecam" }, ++ {} ++}; ++ ++U_BOOT_DRIVER(pcie_sifive) = { ++ .name = "pcie_sifive", ++ .id = UCLASS_PCI, ++ .of_match = pcie_sifive_ids, ++ .ops = &pcie_sifive_ops, ++ .ofdata_to_platdata = pcie_sifive_ofdata_to_platdata, ++ .probe = pcie_sifive_probe, ++ .priv_auto_alloc_size = sizeof(struct pcie_sifive), ++}; +diff --git a/drivers/pci/pcie_sifive.h b/drivers/pci/pcie_sifive.h +new file mode 100644 +index 0000000..45070f7 +--- /dev/null ++++ b/drivers/pci/pcie_sifive.h +@@ -0,0 +1,374 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * SiFive FU740 DesignWare PCIe Controller ++ * ++ * Copyright (C) 2020-2021 SiFive, Inc. ++ * ++ * Based in early part on the i.MX6 PCIe host controller shim which is: ++ * ++ * Copyright (C) 2013 Kosagi ++ * http://www.kosagi.com ++ * ++ * Based on driver from author: Alan Mikhak ++ */ ++ ++#ifndef __PCIE_SIFIVE_H__ ++#define __PCIE_SIFIVE_H__ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define MAX_MSI_IRQS 256 ++#define MAX_MSI_IRQS_PER_CTRL 32 ++#define MAX_MSI_CTRLS (MAX_MSI_IRQS / MAX_MSI_IRQS_PER_CTRL) ++ ++enum pcie_sifive_devtype { ++ SV_PCIE_UNKNOWN_TYPE = 0, ++ SV_PCIE_ENDPOINT_TYPE = 1, ++ SV_PCIE_HOST_TYPE = 3 ++}; ++ ++struct sv_iomem { ++ size_t iosize; ++ void __iomem *iobase; ++ fdt_addr_t phys_base; ++}; ++ ++struct pcie_sifive { ++ struct { ++ struct udevice *dev; ++ u32 num_viewport; ++ u8 iatu_unroll_enabled; ++ struct { ++ u8 root_bus_nr; ++ u64 cfg0_base; ++ void __iomem *va_cfg0_base; ++ fdt_size_t cfg0_size; ++ u64 cfg1_base; ++ void __iomem *va_cfg1_base; ++ fdt_size_t cfg1_size; ++ u32 io_size; ++ u64 io_base; ++ u64 io_bus_addr; ++ u64 mem_size; ++ u64 mem_base; ++ u64 mem_bus_addr; ++ u64 msi_data; ++ u32 num_vectors; ++ u32 irq_mask[MAX_MSI_CTRLS]; ++ struct sv_iomem config; ++ struct sv_iomem ecam; ++ } pp; ++ } pci; ++ struct sv_iomem ctrl; ++ struct sv_iomem priv; ++ enum pcie_sifive_devtype mode; ++ int sys_int_pin; ++ struct gpio_desc pwren_gpio; ++ struct gpio_desc perstn_gpio; ++ struct clk aux_ck; ++ struct reset_ctl reset; ++}; ++ ++#define sv_info(sv, fmt, arg...) printf(fmt, ## arg) ++#define sv_warn(sv, fmt, arg...) printf(fmt, ## arg) ++#define sv_debug(sv, fmt, arg...) debug(fmt, ## arg) ++#define sv_err(sv, fmt, arg...) printf(fmt, ## arg) ++ ++#define pci_epf_header pci_ep_header ++ ++#define VENDOR_ID_MASK GENMASK(15, 0) ++#define DEVICE_ID_SHIFT 16 ++ ++#ifndef PCI_MSIX_FLAGS ++#define PCI_MSIX_FLAGS 2 /* Message Control */ ++#define PCI_MSIX_FLAGS_QSIZE 0x07FF /* Table size */ ++#define PCI_MSIX_FLAGS_MASKALL 0x4000 /* Mask all vectors */ ++#define PCI_MSIX_FLAGS_ENABLE 0x8000 /* MSI-X enable */ ++#endif ++ ++#ifndef PCI_REBAR_CAP ++#define PCI_REBAR_CAP 4 /* capability register */ ++#define PCI_REBAR_CAP_SIZES 0x00FFFFF0 /* supported BAR sizes */ ++#endif ++ ++#ifndef PCI_REBAR_CTRL ++#define PCI_REBAR_CTRL 8 /* control register */ ++#define PCI_REBAR_CTRL_BAR_IDX 0x00000007 /* BAR index */ ++#define PCI_REBAR_CTRL_NBAR_MASK 0x000000E0 /* # of resizable BARs */ ++#define PCI_REBAR_CTRL_NBAR_SHIFT 5 /* shift for # of BARs */ ++#define PCI_REBAR_CTRL_BAR_SIZE 0x00001F00 /* BAR size */ ++#define PCI_REBAR_CTRL_BAR_SHIFT 8 /* shift for BAR size */ ++#endif ++ ++#define MGMT_MISC_LTSSM_ENABLE_OFFSET 0x10 ++#define MGMT_MISC_SYS_INT_OFFSET 0x238 ++#define MGMT_MISC_EDMA_XFER_PEND_OFFSET 0x4d0 ++#define MGMT_MISC_EDMA_INT_OFFSET 0x630 ++#define MGMT_MISC_DEVICE_TYPE_OFFSET 0x708 ++ ++#define MGMT_MISC_LTSSM_ENABLE_BIT BIT(0) ++#define MGMT_MISC_EDMA_XFER_PEND_BIT BIT(0) ++#define MGMT_MISC_EDMA_INT_BITS (BIT(1) | BIT(0)) ++ ++#define MGMT_MISC_DEVICE_TYPE_EP 0x0 ++#define MGMT_MISC_DEVICE_TYPE_RC 0x4 ++ ++/* Doorbell Interface */ ++#define DBI_OFFSET 0x0 ++#define DBI_SIZE 0x1000 ++ ++/* Doorbell Interface 2 */ ++#define DBI2_OFFSET 0x100000 ++#define DBI2_SIZE 0x80 ++ ++/* Address Translation Units */ ++#define ATU_OFFSET 0x300000 ++#define ATU_SIZE 0x80000 ++ ++/* DMA Engines */ ++#define DMA_OFFSET 0x380000 ++#define DMA_SIZE 0x80000 ++ ++#define DMA_WRITE_ENGINE_EN_OFFSET 0x0C ++ ++#define DMA_WRITE_DOORBELL_OFFSET 0x10 ++ ++#define DMA_READ_ENGINE_EN_OFFSET 0x2C ++ ++#define DMA_READ_DOORBELL_OFFSET 0x30 ++ ++#define DMA_WRITE_INT_STATUS_OFFSET 0x4C ++#define DMA_WRITE_INT_MASK_OFFSET 0x54 ++#define DMA_WRITE_INT_CLEAR_OFFSET 0x58 ++ ++#define DMA_READ_INT_STATUS_OFFSET 0xA0 ++#define DMA_READ_INT_MASK_OFFSET 0xA8 ++#define DMA_READ_INT_CLEAR_OFFSET 0xAC ++ ++#define DMA_WRITE_LL_ERR_EN_OFFSET 0x90 ++ ++#define DMA_READ_LL_ERR_EN_OFFSET 0xC4 ++ ++#define DMA_WRITE_CONTROL1_OFFSET 0x200 ++#define DMA_WRITE_TRANSFER_SIZE_OFFSET 0x208 ++#define DMA_WRITE_SAR_LOW_OFFSET 0x20C ++#define DMA_WRITE_SAR_HI_OFFSET 0x210 ++#define DMA_WRITE_DAR_LOW_OFFSET 0x214 ++#define DMA_WRITE_DAR_HI_OFFSET 0x218 ++ ++#define DMA_READ_CONTROL1_OFFSET 0x300 ++#define DMA_READ_TRANSFER_SIZE_OFFSET 0x308 ++#define DMA_READ_SAR_LOW_OFFSET 0x30C ++#define DMA_READ_SAR_HI_OFFSET 0x310 ++#define DMA_READ_DAR_LOW_OFFSET 0x314 ++#define DMA_READ_DAR_HI_OFFSET 0x318 ++ ++#define DMA_CHAN_BIT(chan) (BIT(chan)) ++#define DMA_ENABLE_BIT_CHAN(chan) DMA_CHAN_BIT(chan) ++#define DMA_LLLAIE_BIT_CHAN(chan) DMA_CHAN_BIT(chan) ++#define DMA_INT_DONE_BIT_CHAN(chan) DMA_CHAN_BIT(chan) ++#define DMA_INT_ABORT_BIT_CHAN(chan) (BIT((chan) + 16)) ++ ++/* PCIe Port Logic registers (memory-mapped) */ ++#define PL_OFFSET 0x700 ++#define PCIE_PL_PFLR (PL_OFFSET + 0x08) ++#define PCIE_PL_PFLR_LINK_STATE (0x3f << 16) ++#define PCIE_PL_PFLR_FORCE_LINK BIT(15) ++ ++#define LINK_CONTROL (PL_OFFSET + 0x10) ++#define LINK_MODE(n) ((n) << 16) ++#define LINK_MODE_MASK LINK_MODE(0x3f) ++#define LINK_MODE_1_LANE LINK_MODE(0x1) ++#define LINK_MODE_2_LANES LINK_MODE(0x3) ++#define LINK_MODE_4_LANES LINK_MODE(0x7) ++#define LINK_MODE_8_LANES LINK_MODE(0xf) ++ ++#define PHY_DEBUG_R0 (PL_OFFSET + 0x28) ++ ++#define PHY_DEBUG_R1 (PL_OFFSET + 0x2c) ++#define PHY_DEBUG_R1_LINK_UP (0x1 << 4) ++#define PHY_DEBUG_R1_LINK_IN_TRAINING (0x1 << 29) ++ ++#define LINK_WIDTH_SPEED_CONTROL (PL_OFFSET + 0x10c) ++#define LINK_WIDTH(n) ((n) << 8) ++#define LINK_WIDTH_MASK LINK_WIDTH(0x1f) ++#define LINK_WIDTH_1_LANE LINK_WIDTH(0x1) ++#define LINK_WIDTH_2_LANES LINK_WIDTH(0x2) ++#define LINK_WIDTH_4_LANES LINK_WIDTH(0x4) ++#define LINK_WIDTH_8_LANES LINK_WIDTH(0x8) ++ ++#define PHY_STAT (PL_OFFSET + 0x110) ++#define PHY_STAT_ACK_LOC 16 ++ ++#define PHY_CTRL (PL_OFFSET + 0x114) ++#define PHY_CTRL_DATA_LOC 0 ++#define PHY_CTRL_CAP_ADR_LOC 16 ++#define PHY_CTRL_CAP_DAT_LOC 17 ++#define PHY_CTRL_WR_LOC 18 ++#define PHY_CTRL_RD_LOC 19 ++ ++#define MSI_CTRL_BLOCK_SIZE 12 ++#define MSI_CTRL_BLOCK(ctrl) ((ctrl) * MSI_CTRL_BLOCK_SIZE) ++#define MSI_CTRL_INT_ENABLE(ctrl) (0x828 + MSI_CTRL_BLOCK(ctrl)) ++#define MSI_CTRL_INT_MASK(ctrl) (0x82c + MSI_CTRL_BLOCK(ctrl)) ++#define MSI_CTRL_INT_STATUS(ctrl) (0x830 + MSI_CTRL_BLOCK(ctrl)) ++ ++#define PCIE_MISC_CONTROL_1 0x8bc ++#define DBI_RO_WR_EN BIT(0) ++ ++#define ATU_VIEWPORT 0x900 ++#define ATU_REGION_MIN_SIZE BIT(16) ++#define ATU_REGION_INBOUND BIT(31) ++#define ATU_REGION_OUTBOUND 0 ++ ++#define ATU_VIEWPORT_CTRL_1 0x904 ++#define ATU_TYPE_MASK 0xf ++#define ATU_TYPE_MEM 0x0 ++#define ATU_TYPE_IO 0x2 ++#define ATU_TYPE_CFG0 0x4 ++#define ATU_TYPE_CFG1 0x5 ++#ifdef CONFIG_PCI_ALMOND_FPGA_REV8 ++#define ATU_INCREASE_REGION_SIZE 0 ++#else ++#define ATU_INCREASE_REGION_SIZE BIT(13) ++#endif ++ ++#define ATU_VIEWPORT_CTRL_2 0x908 ++#define ATU_CFG_SHIFT_MODE BIT(28) ++#define ATU_BAR_MATCH_MODE BIT(30) ++#define ATU_ENABLE BIT(31) ++#define ATU_DISABLE (u32)~ATU_ENABLE ++ ++#define ATU_MAX_IN 16 ++#define ATU_MAX_OUT 16 ++ ++#define ATU_WAIT_MAX_RETRIES 5 ++#define ATU_WAIT 9 ++ ++/* ++ * iATU Unroll-specific register definitions ++ * From 4.80 core version the address translation will be made by unroll ++ */ ++#define ATU_REGION_CTRL1 0x00 ++#define ATU_REGION_CTRL2 0x04 ++#define ATU_LOWER_BASE 0x08 ++#define ATU_UPPER_BASE 0x0C ++#define ATU_LOWER_LIMIT 0x10 ++#define ATU_LOWER_TARGET 0x14 ++#define ATU_UPPER_TARGET 0x18 ++#define ATU_UPPER_LIMIT 0x20 ++ ++#define ATU_OUTBOUND_REGION(region) ((region) << 9) ++#define ATU_INBOUND_REGION(region) (((region) << 9) | BIT(8)) ++ ++#define SIFIVE_PCIEAUXGATECFG 0x14 ++#define SIFIVE_DEVICESRESETREG 0x28 ++ ++#define PCIEX8MGMT_PERST_N 0x0 ++#define PCIEX8MGMT_APP_LTSSM_ENABLE 0x10 ++#define PCIEX8MGMT_APP_HOLD_PHY_RST 0x18 ++#define PCIEX8MGMT_DEVICE_TYPE 0x708 ++#define PCIEX8MGMT_PHY0_CR_PARA_ADDR 0x860 ++#define PCIEX8MGMT_PHY0_CR_PARA_RD_EN 0x870 ++#define PCIEX8MGMT_PHY0_CR_PARA_RD_DATA 0x878 ++#define PCIEX8MGMT_PHY0_CR_PARA_SEL 0x880 ++#define PCIEX8MGMT_PHY0_CR_PARA_WR_DATA 0x888 ++#define PCIEX8MGMT_PHY0_CR_PARA_WR_EN 0x890 ++#define PCIEX8MGMT_PHY0_CR_PARA_ACK 0x898 ++#define PCIEX8MGMT_PHY1_CR_PARA_ADDR 0x8a0 ++#define PCIEX8MGMT_PHY1_CR_PARA_RD_EN 0x8b0 ++#define PCIEX8MGMT_PHY1_CR_PARA_RD_DATA 0x8b8 ++#define PCIEX8MGMT_PHY1_CR_PARA_SEL 0x8c0 ++#define PCIEX8MGMT_PHY1_CR_PARA_WR_DATA 0x8c8 ++#define PCIEX8MGMT_PHY1_CR_PARA_WR_EN 0x8d0 ++#define PCIEX8MGMT_PHY1_CR_PARA_ACK 0x8d8 ++ ++#define PCIEX8MGMT_LANE_NUM 8 ++#define PCIEX8MGMT_LANE 0x1008 ++#define PCIEX8MGMT_LANE_OFF 0x100 ++#define PCIEX8MGMT_TERM_MODE 0x0e21 ++ ++/* PCIe Port Logic registers (memory-mapped) */ ++#define PL_OFFSET 0x700 ++#define PCIE_PL_PFLR (PL_OFFSET + 0x08) ++#define PCIE_PL_PFLR_LINK_STATE_MASK (0x3f << 16) ++#define PCIE_PL_PFLR_FORCE_LINK BIT(15) ++#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28) ++#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c) ++#define PCIE_PL_GEN2_CTRL_OFF (PL_OFFSET + 0x10c) ++#define PCIE_PL_DIRECTED_SPEED_CHANGE_OFF 0x20000 ++ ++#define PCIE_PHY_CTRL (PL_OFFSET + 0x114) ++#define PCIE_PHY_CTRL_DATA_LOC 0 ++#define PCIE_PHY_CTRL_CAP_ADR_LOC 16 ++#define PCIE_PHY_CTRL_CAP_DAT_LOC 17 ++#define PCIE_PHY_CTRL_WR_LOC 18 ++#define PCIE_PHY_CTRL_RD_LOC 19 ++ ++#define PCIE_PHY_STAT (PL_OFFSET + 0x110) ++#define PCIE_PHY_STAT_ACK_LOC 16 ++ ++#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C ++ ++/* PCIe Root Complex registers (memory-mapped) */ ++#define PCIE_RC_PF0_MSI_CAP 0x50 ++#define PCI_MSI_CAP_ID_NEXT_CTRL_REG (PCIE_RC_PF0_MSI_CAP + 0x0) ++ ++#define PCIE_RC_PF0_MSIX_CAP 0x0 ++ ++#define PCIE_DSP_PF0_PCIE_CAP_BASE 0x70 ++#define PCIE_RC_LCR (PCIE_DSP_PF0_PCIE_CAP_BASE + 0xc) ++#define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1 0x1 ++#define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2 0x2 ++#define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN3 0x3 ++#define PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK 0xf ++ ++#define PCIE_RC_LCSR (PCIE_DSP_PF0_PCIE_CAP_BASE + 0x10) ++ ++#define DMA_CONFIG(r) (DMA_OFFSET + (r)) ++#define ATU_CONFIG(r) (ATU_OFFSET + (r)) ++#define PCI_SHADOW(r) (DBI2_OFFSET + (r)) ++#define PCI_CONFIG(r) (DBI_OFFSET + (r)) ++#define MSI_CAPABILITIES(r) PCI_CONFIG(PCIE_RC_PF0_MSI_CAP + (r)) ++#define MSIX_CAPABILITIES(r) PCI_CONFIG(PCIE_RC_PF0_MSIX_CAP + (r)) ++#define PCIE_CAPABILITIES(r) PCI_CONFIG(PCIE_DSP_PF0_PCIE_CAP_BASE + (r)) ++ ++#define PF0_PCIE_CAP_LINK_CAP PCIE_CAPABILITIES(0xc) ++#define PCIE_LINK_CAP_MAX_SPEED_MASK 0xf ++#define PCIE_LINK_CAP_MAX_SPEED_GEN1 BIT(0) ++#define PCIE_LINK_CAP_MAX_SPEED_GEN2 BIT(1) ++#define PCIE_LINK_CAP_MAX_SPEED_GEN3 BIT(2) ++#define PCIE_LINK_CAP_MAX_SPEED_GEN4 BIT(3) ++ ++#define PF0_PCIE_CAP_LINK_CONTROL PCIE_CAPABILITIES(0x10) ++ ++#define PF0_PCIE_CAP_LINK_STATUS PCIE_CAPABILITIES(0x12) ++#define PCIE_LINK_STATUS_SPEED_MASK 0xf ++ ++#define PCI_CFG0_REGION_OFFSET 0x00000000 ++#define PCI_CFG0_REGION_SIZE 0x00001000 /* 2^12 = 4KB */ ++#define PCI_CFG1_REGION_OFFSET 0x00001000 ++#define PCI_CFG1_REGION_SIZE 0x00001000 /* 2^12 = 4KB */ ++#define PCI_MSI_REGION_OFFSET 0x00002000 ++#define PCI_MSI_REGION_SIZE 0x00001000 /* 2^12 = 4KB */ ++#define PCI_IO_REGION_OFFSET 0x00080000 ++#define PCI_IO_REGION_SIZE 0x00010000 /* 2^16 = 64KB */ ++#define PCI_MEM_REGION_OFFSET 0x04000000 ++#define PCI_MEM_REGION_SIZE 0x04000000 /* 2^26 = 64MB */ ++#define PCI_AUTOCFG_REGION_OFFSET 0x08000000 ++#define PCI_AUTOCFG_REGION_SIZE 0x08000000 /* 2^27 = 128MB */ ++#define PCI_ECAM_REGION_OFFSET 0x10000000 ++#define PCI_ECAM_REGION_SIZE 0x10000000 /* 2^28 = 256MB */ ++ ++#endif /* __PCIE_SIFIVE_H__ */ +-- +2.7.4 + diff -Nru u-boot-2021.01+dfsg/debian/patches/riscv64/0031-Update-SiFive-Unmatched-defconfig.patch u-boot-2021.01+dfsg/debian/patches/riscv64/0031-Update-SiFive-Unmatched-defconfig.patch --- u-boot-2021.01+dfsg/debian/patches/riscv64/0031-Update-SiFive-Unmatched-defconfig.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/riscv64/0031-Update-SiFive-Unmatched-defconfig.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,42 @@ +From a271d3339f9b1c5ec1e29f5e5bc9938c23afc213 Mon Sep 17 00:00:00 2001 +From: David Abdurachmanov +Date: Tue, 23 Feb 2021 06:28:24 -0800 +Subject: [PATCH 31/41] Update SiFive Unmatched defconfig + +Expand defconfig to support NVMe, PCIe, USB. + +This seems to be USB gadget feature. + +Signed-off-by: David Abdurachmanov +--- + configs/sifive_hifive_unmatched_fu740_defconfig | 17 +++++++++++++++++ + 1 file changed, 17 insertions(+) + +diff --git a/configs/sifive_hifive_unmatched_fu740_defconfig b/configs/sifive_hifive_unmatched_fu740_defconfig +index bf274eb..2a5ff39 100644 +--- a/configs/sifive_hifive_unmatched_fu740_defconfig ++++ b/configs/sifive_hifive_unmatched_fu740_defconfig +@@ -26,3 +26,20 @@ CONFIG_PCI=y + CONFIG_DM_PCI=y + CONFIG_PCI_PNP=y + CONFIG_PCIE_SIFIVE_FU740=y ++CONFIG_NVME=y ++CONFIG_DM_ETH=y ++CONFIG_NETDEVICES=y ++CONFIG_E1000=y ++CONFIG_USB=y ++CONFIG_CMD_USB=y ++CONFIG_DM_USB=y ++CONFIG_USB_STORAGE=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_PCI=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_USB_OHCI_GENERIC=y ++CONFIG_CMD_PART=y ++CONFIG_CMD_NVME=y ++CONFIG_SYS_USB_EVENT_POLL=y +-- +2.7.4 + diff -Nru u-boot-2021.01+dfsg/debian/patches/riscv64/0032-riscv-sifive-unmatched-set-cacheline-size-to-64-byte.patch u-boot-2021.01+dfsg/debian/patches/riscv64/0032-riscv-sifive-unmatched-set-cacheline-size-to-64-byte.patch --- u-boot-2021.01+dfsg/debian/patches/riscv64/0032-riscv-sifive-unmatched-set-cacheline-size-to-64-byte.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/riscv64/0032-riscv-sifive-unmatched-set-cacheline-size-to-64-byte.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,30 @@ +From 2d84c2e547bdcf8cd228d6259dce9826c49483be Mon Sep 17 00:00:00 2001 +From: David Abdurachmanov +Date: Tue, 23 Feb 2021 06:29:45 -0800 +Subject: [PATCH 32/41] riscv: sifive: unmatched: set cacheline size to 64 + bytes; max USB ports + +Signed-off-by: David Abdurachmanov +--- + include/configs/sifive-hifive-unmatched-fu740.h | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/include/configs/sifive-hifive-unmatched-fu740.h b/include/configs/sifive-hifive-unmatched-fu740.h +index 30458d2..255031d 100644 +--- a/include/configs/sifive-hifive-unmatched-fu740.h ++++ b/include/configs/sifive-hifive-unmatched-fu740.h +@@ -38,6 +38,11 @@ + + #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit resources */ + ++#define CONFIG_SYS_CACHELINE_SIZE 64 ++ ++#define CONFIG_USB_OHCI_NEW ++#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 4 ++ + /* Environment options */ + + #ifndef CONFIG_SPL_BUILD +-- +2.7.4 + diff -Nru u-boot-2021.01+dfsg/debian/patches/riscv64/0033-fu740-add-CONFIG_CMD_GPT-and-CONFIG_CMD_GPT_RENAME.patch u-boot-2021.01+dfsg/debian/patches/riscv64/0033-fu740-add-CONFIG_CMD_GPT-and-CONFIG_CMD_GPT_RENAME.patch --- u-boot-2021.01+dfsg/debian/patches/riscv64/0033-fu740-add-CONFIG_CMD_GPT-and-CONFIG_CMD_GPT_RENAME.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/riscv64/0033-fu740-add-CONFIG_CMD_GPT-and-CONFIG_CMD_GPT_RENAME.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,23 @@ +From 22b0d48143552fd24957178bf881fb8414ad5ff1 Mon Sep 17 00:00:00 2001 +From: David Abdurachmanov +Date: Thu, 21 Jan 2021 06:44:41 -0800 +Subject: [PATCH 33/41] fu740: add CONFIG_CMD_GPT and CONFIG_CMD_GPT_RENAME + +Signed-off-by: David Abdurachmanov +--- + configs/sifive_hifive_unmatched_fu740_defconfig | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/configs/sifive_hifive_unmatched_fu740_defconfig b/configs/sifive_hifive_unmatched_fu740_defconfig +index 2a5ff39..5a1b8b0 100644 +--- a/configs/sifive_hifive_unmatched_fu740_defconfig ++++ b/configs/sifive_hifive_unmatched_fu740_defconfig +@@ -43,3 +43,5 @@ CONFIG_USB_OHCI_GENERIC=y + CONFIG_CMD_PART=y + CONFIG_CMD_NVME=y + CONFIG_SYS_USB_EVENT_POLL=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_GPT_RENAME=y +-- +2.7.4 + diff -Nru u-boot-2021.01+dfsg/debian/patches/riscv64/0034-Unmathced-FU740-add-NVME-USB-and-PXE-to-boot-targets.patch u-boot-2021.01+dfsg/debian/patches/riscv64/0034-Unmathced-FU740-add-NVME-USB-and-PXE-to-boot-targets.patch --- u-boot-2021.01+dfsg/debian/patches/riscv64/0034-Unmathced-FU740-add-NVME-USB-and-PXE-to-boot-targets.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/riscv64/0034-Unmathced-FU740-add-NVME-USB-and-PXE-to-boot-targets.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,30 @@ +From b7737239076ae5f0f05ac8353b1e3a29cfb7a374 Mon Sep 17 00:00:00 2001 +From: David Abdurachmanov +Date: Tue, 19 Jan 2021 04:34:26 -0800 +Subject: [PATCH 34/41] Unmathced/FU740 add NVME, USB and PXE to boot targets + +1st try NVMe, 2nd USB, 3rd MMC, 4th PXE, 5th/final DHCP + +Signed-off-by: David Abdurachmanov +--- + include/configs/sifive-hifive-unmatched-fu740.h | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/include/configs/sifive-hifive-unmatched-fu740.h b/include/configs/sifive-hifive-unmatched-fu740.h +index 255031d..f915000 100644 +--- a/include/configs/sifive-hifive-unmatched-fu740.h ++++ b/include/configs/sifive-hifive-unmatched-fu740.h +@@ -47,7 +47,10 @@ + + #ifndef CONFIG_SPL_BUILD + #define BOOT_TARGET_DEVICES(func) \ ++ func(NVME, nvme, 0) \ ++ func(USB, usb, 0) \ + func(MMC, mmc, 0) \ ++ func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + + #include +-- +2.7.4 + diff -Nru u-boot-2021.01+dfsg/debian/patches/riscv64/0035-riscv-clear-feature-disable-CSR.patch u-boot-2021.01+dfsg/debian/patches/riscv64/0035-riscv-clear-feature-disable-CSR.patch --- u-boot-2021.01+dfsg/debian/patches/riscv64/0035-riscv-clear-feature-disable-CSR.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/riscv64/0035-riscv-clear-feature-disable-CSR.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,28 @@ +From 7e19c3e209a4acfd9698702ddaa3a724c59edc7a Mon Sep 17 00:00:00 2001 +From: Green Wan +Date: Mon, 22 Feb 2021 10:56:35 +0000 +Subject: [PATCH 35/41] riscv: clear feature disable CSR + +feature disable CSR should be cleared for each core to gain +performance. + +Signed-off-by: Green Wan +--- + arch/riscv/cpu/start.S | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S +index 8589509..c3d4647 100644 +--- a/arch/riscv/cpu/start.S ++++ b/arch/riscv/cpu/start.S +@@ -41,6 +41,7 @@ secondary_harts_relocation_error: + _start: + #if CONFIG_IS_ENABLED(RISCV_MMODE) + csrr a0, CSR_MHARTID ++ csrwi 0x7c1, 0 + #endif + + /* +-- +2.7.4 + diff -Nru u-boot-2021.01+dfsg/debian/patches/riscv64/0036-riscv-sifive-unmatched-add-I2C-EEPROM.patch u-boot-2021.01+dfsg/debian/patches/riscv64/0036-riscv-sifive-unmatched-add-I2C-EEPROM.patch --- u-boot-2021.01+dfsg/debian/patches/riscv64/0036-riscv-sifive-unmatched-add-I2C-EEPROM.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/riscv64/0036-riscv-sifive-unmatched-add-I2C-EEPROM.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,615 @@ +From 79e471393ecb48d21f2e28a349f63dc54781d456 Mon Sep 17 00:00:00 2001 +From: David Abdurachmanov +Date: Thu, 11 Mar 2021 05:36:41 -0800 +Subject: [PATCH 36/41] riscv: sifive: unmatched: add I2C EEPROM + +- Print board serial number of the board +- Print PCB revision +- Set Ethernet address +- Set board serial number in U-Boot environment + +Signed-off-by: David Abdurachmanov +--- + board/sifive/hifive_unmatched_fu740/Makefile | 1 + + .../hifive-platform-i2c-eeprom.c | 536 +++++++++++++++++++++ + configs/sifive_hifive_unmatched_fu740_defconfig | 7 + + include/configs/sifive-hifive-unmatched-fu740.h | 6 + + 4 files changed, 550 insertions(+) + create mode 100644 board/sifive/hifive_unmatched_fu740/hifive-platform-i2c-eeprom.c + +diff --git a/board/sifive/hifive_unmatched_fu740/Makefile b/board/sifive/hifive_unmatched_fu740/Makefile +index aeab025..cd173da 100644 +--- a/board/sifive/hifive_unmatched_fu740/Makefile ++++ b/board/sifive/hifive_unmatched_fu740/Makefile +@@ -3,6 +3,7 @@ + # Copyright (c) 2020 SiFive, Inc + + obj-y += hifive-unmatched-fu740.o ++obj-$(CONFIG_ID_EEPROM) += hifive-platform-i2c-eeprom.o + + ifdef CONFIG_SPL_BUILD + obj-y += spl.o +diff --git a/board/sifive/hifive_unmatched_fu740/hifive-platform-i2c-eeprom.c b/board/sifive/hifive_unmatched_fu740/hifive-platform-i2c-eeprom.c +new file mode 100644 +index 0000000..be7a4fe +--- /dev/null ++++ b/board/sifive/hifive_unmatched_fu740/hifive-platform-i2c-eeprom.c +@@ -0,0 +1,536 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) 2020-2021 SiFive, Inc. ++ * ++ * Based on board/freescale/common/sys_eeprom.c: ++ * Copyright 2006, 2008-2009, 2011 Freescale Semiconductor ++ * York Sun (yorksun@freescale.com) ++ * Haiying Wang (haiying.wang@freescale.com) ++ * Timur Tabi (timur@freescale.com) ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifndef CONFIG_SYS_EEPROM_BUS_NUM ++#error Requires CONFIG_SYS_EEPROM_BUS_NUM to be defined ++#endif ++ ++#define DEBUG ++ ++#define FORMAT_VERSION 0x1 ++ ++/* Options for the manuf_test_status field */ ++#define SIFIVE_MANUF_TEST_STATUS_UNKNOWN 0 ++#define SIFIVE_MANUF_TEST_STATUS_PASS 1 ++#define SIFIVE_MANUF_TEST_STATUS_FAIL 2 ++ ++/* ++ * BYTES_PER_EEPROM_PAGE: the AT24C02 datasheet says that data can ++ * only be written in page mode, which means 8 bytes at a time ++ */ ++#define BYTES_PER_EEPROM_PAGE 8 ++ ++/* ++ * EEPROM_WRITE_DELAY_MS: the AT24C02 datasheet says it takes up to ++ * 5ms to complete a given write ++ */ ++#define EEPROM_WRITE_DELAY_MS 5000 ++ ++/* ++ * MAGIC_NUMBER_BYTES: number of bytes used by the magic number ++ */ ++#define MAGIC_NUMBER_BYTES 4 ++ ++/* ++ * SERIAL_NUMBER_BYTES: number of bytes used by the board serial ++ * number ++ */ ++#define SERIAL_NUMBER_BYTES 16 ++ ++/* ++ * MAC_ADDR_BYTES: number of bytes used by the Ethernet MAC address ++ */ ++#define MAC_ADDR_BYTES 6 ++ ++ ++/** ++ * static eeprom: EEPROM layout for the SiFive platform I2C format ++ */ ++struct __attribute__ ((__packed__)) sifive_eeprom { ++ u8 magic[MAGIC_NUMBER_BYTES]; ++ u8 format_ver; ++ u16 product_id; ++ u8 pcb_revision; ++ u8 bom_revision; ++ u8 bom_variant; ++ u8 serial[SERIAL_NUMBER_BYTES]; ++ u8 manuf_test_status; ++ u8 mac_addr[MAC_ADDR_BYTES]; ++ u32 crc; ++}; ++ ++static struct sifive_eeprom e; ++ ++/* Set to 1 if we've read EEPROM into memory */ ++static int has_been_read = 0; ++ ++static const unsigned char magic[MAGIC_NUMBER_BYTES] = { 0xf1, 0x5e, 0x50, ++ 0x45 }; ++ ++ ++static u32 __compute_eeprom_crc(struct sifive_eeprom *eeprom) { ++ return crc32(0, (void *)&eeprom, ++ sizeof(eeprom) - sizeof(eeprom->crc)); ++} ++ ++/* Does the magic number match that of a SiFive EEPROM? */ ++static int test_magic(struct sifive_eeprom *e) ++{ ++ return (memcmp(e->magic, &magic, MAGIC_NUMBER_BYTES) == 0); ++} ++ ++/** ++ * show_parsed_eeprom - display the contents of the EEPROM, parsed into fields ++ */ ++static void show_parsed_eeprom(void) ++{ ++ char board_serial[SERIAL_NUMBER_BYTES + 1] = { 0 }; ++ ++ printf("SiFive PCB EEPROM format v%u\n", e.format_ver); ++ snprintf(board_serial, sizeof(board_serial), "%s", e.serial); ++ printf("Serial number: %s\n", board_serial); ++ printf("PCB revision: %u\n", (unsigned int)e.pcb_revision); ++ ++ /* Show MAC address */ ++ printf("Ethernet MAC address: %02x:%02x:%02x:%02x:%02x:%02x\n", ++ e.mac_addr[0], e.mac_addr[1], e.mac_addr[2], ++ e.mac_addr[3], e.mac_addr[4], e.mac_addr[5]); ++} ++ ++/** ++ * show_raw_eeprom - display the raw contents of the EEPROM ++ */ ++static void show_raw_eeprom(void) ++{ ++ int i; ++ ++ printf("EEPROM dump: (0x%lx bytes)\n", sizeof(e)); ++ for (i = 0; i < sizeof(e); i++) { ++ if ((i % 16) == 0) ++ printf("%02X: ", i); ++ printf("%02X ", ((u8 *)&e)[i]); ++ if (((i % 16) == 15) || (i == sizeof(e) - 1)) ++ printf("\n"); ++ } ++} ++ ++/** ++ * show_eeprom - display the contents of the EEPROM ++ */ ++static void show_eeprom(void) ++{ ++ unsigned int crc; ++ ++ if (!test_magic(&e)) { ++ printf("Not a SiFive EEPROM data format - magic bytes don't match\n"); ++ show_raw_eeprom(); ++ return; ++ }; ++ ++ show_parsed_eeprom(); ++ ++ crc = __compute_eeprom_crc(&e); ++ if (crc == le32_to_cpu(e.crc)) ++ printf("CRC: %08x\n", le32_to_cpu(e.crc)); ++ else ++ printf("CRC: %08x (should be %08x)\n", ++ le32_to_cpu(e.crc), crc); ++ ++#ifdef DEBUG ++ show_raw_eeprom(); ++#endif ++} ++ ++/** ++ * __read_eeprom() - read the EEPROM into memory ++ */ ++static int __read_eeprom(struct sifive_eeprom *eeprom) ++{ ++ int ret; ++ ++ struct udevice *dev; ++ ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM, ++ CONFIG_SYS_I2C_EEPROM_ADDR, 1, &dev); ++ if (!ret) ++ ret = dm_i2c_read(dev, 0, (void *)eeprom, ++ sizeof(struct sifive_eeprom)); ++ ++ return ret; ++} ++ ++ ++/** ++ * read_eeprom() - read the EEPROM into memory, if it hsan't been read already ++ */ ++static int read_eeprom(void) ++{ ++ int ret; ++ ++ if (has_been_read) ++ return 0; ++ ++ ret = __read_eeprom(&e); ++ ++#ifdef DEBUG ++ show_eeprom(); ++#endif ++ ++ has_been_read = (ret == 0) ? 1 : 0; ++ ++ return ret; ++} ++ ++/** ++ * update_crc() - update the CRC ++ * ++ * This function should be called after each update to the EEPROM structure, ++ * to make sure the CRC is always correct. ++ */ ++static void update_crc(void) ++{ ++ e.crc = cpu_to_le32(__compute_eeprom_crc(&e)); ++} ++ ++/** ++ * prog_eeprom() - write the EEPROM from memory ++ */ ++static int prog_eeprom(void) ++{ ++ int ret = 0; ++ int i; ++ void *p; ++ ++ if (!test_magic(&e)) { ++ printf("Please read the EEPROM ('read_eeprom') and/or initialize the EEPROM ('initialize') first.\n"); ++ return 0; ++ } ++ ++ for (i = 0, p = &e; i < sizeof(e); ++ i += BYTES_PER_EEPROM_PAGE, p += BYTES_PER_EEPROM_PAGE) { ++ struct udevice *dev; ++ ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM, ++ CONFIG_SYS_I2C_EEPROM_ADDR, ++ CONFIG_SYS_I2C_EEPROM_ADDR_LEN, ++ &dev); ++ if (!ret) ++ ret = dm_i2c_write(dev, i, p, min((int)(sizeof(e) - i), ++ BYTES_PER_EEPROM_PAGE)); ++ if (ret) ++ break; ++ ++ udelay(EEPROM_WRITE_DELAY_MS); ++ } ++ ++ if (!ret) { ++ /* Verify the write by reading back the EEPROM and comparing */ ++ struct sifive_eeprom e2; ++ ++ struct udevice *dev; ++ ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM, ++ CONFIG_SYS_I2C_EEPROM_ADDR, ++ CONFIG_SYS_I2C_EEPROM_ADDR_LEN, ++ &dev); ++ if (!ret) ++ ret = dm_i2c_read(dev, 0, (void *)&e2, sizeof(e2)); ++ if (!ret && memcmp(&e, &e2, sizeof(e))) ++ ret = -1; ++ } ++ ++ if (ret) { ++ printf("Programming failed.\n"); ++ has_been_read = 0; ++ return -1; ++ } ++ ++ printf("Programming passed.\n"); ++ return 0; ++} ++ ++/** ++ * set_mac_address() - stores a MAC address into the local EEPROM copy ++ * ++ * This function takes a pointer to MAC address string ++ * (i.e."XX:XX:XX:XX:XX:XX", where "XX" is a two-digit hex number), ++ * stores it in the MAC address field of the EEPROM local copy, and ++ * updates the local copy of the CRC. ++ */ ++static void set_mac_address(char *string) ++{ ++ unsigned int i; ++ ++ /* XXX Validate that the MAC address uses the SiFive OUI */ ++ for (i = 0; *string && (i < MAC_ADDR_BYTES); i++) { ++ e.mac_addr[i] = simple_strtoul(string, &string, 16); ++ if (*string == ':') ++ string++; ++ } ++ ++ update_crc(); ++} ++ ++/** ++ * set_manuf_test_status() - stores a test status byte into the in-memory copy ++ * ++ * Takes a pointer to a manufacturing test status string ("unknown", ++ * "pass", "fail") and stores the corresponding numeric ID to the ++ * manuf_test_status field of the EEPROM local copy, and updates the ++ * CRC of the local copy. ++ */ ++static void set_manuf_test_status(char *string) ++{ ++ if (!strcasecmp(string, "unknown")) { ++ e.manuf_test_status = SIFIVE_MANUF_TEST_STATUS_UNKNOWN; ++ } else if (!strcasecmp(string, "pass")) { ++ e.manuf_test_status = SIFIVE_MANUF_TEST_STATUS_PASS; ++ } else if (!strcasecmp(string, "fail")) { ++ e.manuf_test_status = SIFIVE_MANUF_TEST_STATUS_FAIL; ++ } else { ++ printf("Usage: mac manuf_test_status (unknown|pass|fail)\n"); ++ return; ++ } ++ ++ update_crc(); ++} ++ ++/** ++ * set_pcb_revision() - stores a SiFive PCB revision into the local EEPROM copy ++ * ++ * Takes a pointer to a string representing the numeric PCB revision in ++ * decimal ("0" - "255"), stores it in the pcb_revision field of the ++ * EEPROM local copy, and updates the CRC of the local copy. ++ */ ++static void set_pcb_revision(char *string) ++{ ++ unsigned long p; ++ ++ p = simple_strtoul(string, &string, 10); ++ if (p > U8_MAX) { ++ printf("%s must not be greater than %d\n", "PCB revision", ++ U8_MAX); ++ return; ++ } ++ ++ e.pcb_revision = p; ++ ++ update_crc(); ++} ++ ++/** ++ * set_bom_revision() - stores a SiFive BOM revision into the local EEPROM copy ++ * ++ * Takes a pointer to a uppercase ASCII character representing the BOM ++ * revision ("A" - "Z"), stores it in the bom_revision field of the ++ * EEPROM local copy, and updates the CRC of the local copy. ++ */ ++static void set_bom_revision(char *string) ++{ ++ if (string[0] < 'A' || string[0] > 'Z') { ++ printf("BOM revision must be an uppercase letter between A and Z\n"); ++ return; ++ } ++ ++ e.bom_revision = string[0]; ++ ++ update_crc(); ++} ++ ++/** ++ * set_bom_variant() - stores a SiFive BOM variant into the local EEPROM copy ++ * ++ * Takes a pointer to a string representing the numeric BOM variant in ++ * decimal ("0" - "255"), stores it in the bom_variant field of the ++ * EEPROM local copy, and updates the CRC of the local copy. ++ */ ++static void set_bom_variant(char *string) ++{ ++ unsigned long p; ++ ++ p = simple_strtoul(string, &string, 10); ++ if (p > U8_MAX) { ++ printf("%s must not be greater than %d\n", "BOM variant", ++ U8_MAX); ++ return; ++ } ++ ++ e.bom_variant = p; ++ ++ update_crc(); ++} ++ ++/** ++ * set_product_id() - stores a SiFive product ID into the local EEPROM copy ++ * ++ * Takes a pointer to a string representing the numeric product ID in ++ * decimal ("0" - "65535"), stores it in the product ID field of the ++ * EEPROM local copy, and updates the CRC of the local copy. ++ */ ++static void set_product_id(char *string) ++{ ++ unsigned long p; ++ ++ p = simple_strtoul(string, &string, 10); ++ if (p > U16_MAX) { ++ printf("%s must not be greater than %d\n", "Product ID", ++ U16_MAX); ++ return; ++ } ++ ++ e.product_id = p; ++ ++ update_crc(); ++} ++ ++/** ++ * init_local_copy() - initialize the in-memory EEPROM copy ++ * ++ * Initialize the in-memory EEPROM copy with the magic number. Must ++ * be done when preparing to initialize a blank EEPROM, or overwrite ++ * one with a corrupted magic number. ++ */ ++static void init_local_copy(void) ++{ ++ memset(&e, 0, sizeof(e)); ++ memcpy(e.magic, magic, sizeof(e.magic)); ++ e.format_ver = FORMAT_VERSION; ++ update_crc(); ++} ++ ++/** ++ * set_serial_number() - set the PCB serial number in the in-memory copy ++ * ++ * Set the board serial number in the in-memory EEPROM copy from the supplied ++ * string argument, and update the CRC. ++ */ ++static void set_serial_number(char *string) ++{ ++ memset(e.serial, 0, sizeof(e.serial)); ++ strncpy((char *)e.serial, string, sizeof(e.serial) - 1); ++ update_crc(); ++} ++ ++ ++/* XXX Add command table structure */ ++ ++int do_mac(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) ++{ ++ char *cmd; ++ ++ if (argc == 1) { ++ show_eeprom(); ++ return 0; ++ } ++ ++ if (argc > 3) ++ return cmd_usage(cmdtp); ++ ++ cmd = argv[1]; ++ ++ /* Commands with no argument */ ++ if (!strcmp(cmd, "read_eeprom")) { ++ read_eeprom(); ++ return 0; ++ } else if (!strcmp(cmd, "initialize")) { ++ init_local_copy(); ++ return 0; ++ } else if (!strcmp(cmd, "write_eeprom")) { ++ prog_eeprom(); ++ return 0; ++ } ++ ++ if (argc != 3) ++ return cmd_usage(cmdtp); ++ ++ if (!test_magic(&e)) { ++ printf("Please read the EEPROM ('read_eeprom') and/or initialize the EEPROM ('initialize') first.\n"); ++ return 0; ++ } ++ ++ if (!strcmp(cmd, "serial_number")) { ++ set_serial_number(argv[2]); ++ return 0; ++ } else if (!strcmp(cmd, "manuf_test_status")) { ++ set_manuf_test_status(argv[2]); ++ return 0; ++ } else if (!strcmp(cmd, "mac_address")) { ++ set_mac_address(argv[2]); ++ return 0; ++ } else if (!strcmp(cmd, "pcb_revision")) { ++ set_pcb_revision(argv[2]); ++ return 0; ++ } else if (!strcmp(cmd, "bom_variant")) { ++ set_bom_variant(argv[2]); ++ return 0; ++ } else if (!strcmp(cmd, "bom_revision")) { ++ set_bom_revision(argv[2]); ++ return 0; ++ } else if (!strcmp(cmd, "product_id")) { ++ set_product_id(argv[2]); ++ return 0; ++ } ++ ++ return cmd_usage(cmdtp); ++} ++ ++/** ++ * mac_read_from_eeprom() - read the MAC address from EEPROM ++ * ++ * This function reads the MAC address from EEPROM and sets the ++ * appropriate environment variables for each one read. ++ * ++ * The environment variables are only set if they haven't been set already. ++ * This ensures that any user-saved variables are never overwritten. ++ * ++ * This function must be called after relocation. ++ */ ++int mac_read_from_eeprom(void) ++{ ++ u32 crc; ++ char board_serial[SERIAL_NUMBER_BYTES + 1] = { 0 }; ++ ++ puts("EEPROM: "); ++ ++ if (read_eeprom()) { ++ printf("Read failed.\n"); ++ return 0; ++ } ++ ++ if (!test_magic(&e)) { ++ printf("Invalid ID (%02x %02x %02x %02x)\n", ++ e.magic[0], e.magic[1], e.magic[2], e.magic[3]); ++ return 0; ++ } ++ ++ crc = __compute_eeprom_crc(&e); ++ if (crc != le32_to_cpu(e.crc)) { ++ printf("CRC mismatch (%08x != %08x)\n", crc, ++ le32_to_cpu(e.crc)); ++ } ++ ++ eth_env_set_enetaddr("ethaddr", e.mac_addr); ++ ++ if (!env_get("serial#")) { ++ snprintf(board_serial, sizeof(board_serial), "%s", e.serial); ++ env_set("serial#", board_serial); ++ } ++ ++ printf("found SiFive v%u\n", le32_to_cpu(e.format_ver)); ++ ++ return 0; ++} +diff --git a/configs/sifive_hifive_unmatched_fu740_defconfig b/configs/sifive_hifive_unmatched_fu740_defconfig +index 5a1b8b0..a853177 100644 +--- a/configs/sifive_hifive_unmatched_fu740_defconfig ++++ b/configs/sifive_hifive_unmatched_fu740_defconfig +@@ -15,6 +15,7 @@ CONFIG_FIT=y + CONFIG_SPL_LOAD_FIT_ADDRESS=0x84000000 + CONFIG_DISPLAY_CPUINFO=y + CONFIG_DISPLAY_BOARDINFO=y ++CONFIG_DISPLAY_BOARDINFO_LATE=y + CONFIG_SPL_SEPARATE_BSS=y + CONFIG_SPL_DM_RESET=y + CONFIG_SPL_YMODEM_SUPPORT=y +@@ -45,3 +46,9 @@ CONFIG_CMD_NVME=y + CONFIG_SYS_USB_EVENT_POLL=y + CONFIG_CMD_GPT=y + CONFIG_CMD_GPT_RENAME=y ++CONFIG_CMD_EEPROM=y ++CONFIG_CMD_MEMINFO=y ++CONFIG_CMD_I2C=y ++CONFIG_DM_I2C=y ++CONFIG_SYS_I2C_OCORES=y ++CONFIG_CLK_SIFIVE_PRCI=y +diff --git a/include/configs/sifive-hifive-unmatched-fu740.h b/include/configs/sifive-hifive-unmatched-fu740.h +index f915000..deb3414 100644 +--- a/include/configs/sifive-hifive-unmatched-fu740.h ++++ b/include/configs/sifive-hifive-unmatched-fu740.h +@@ -43,6 +43,12 @@ + #define CONFIG_USB_OHCI_NEW + #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 4 + ++#define CONFIG_SYS_EEPROM_BUS_NUM 0 ++#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 ++#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 0x1 ++ ++#define CONFIG_ID_EEPROM ++ + /* Environment options */ + + #ifndef CONFIG_SPL_BUILD +-- +2.7.4 + diff -Nru u-boot-2021.01+dfsg/debian/patches/riscv64/0037-cmd-Add-a-pwm-command.patch u-boot-2021.01+dfsg/debian/patches/riscv64/0037-cmd-Add-a-pwm-command.patch --- u-boot-2021.01+dfsg/debian/patches/riscv64/0037-cmd-Add-a-pwm-command.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/riscv64/0037-cmd-Add-a-pwm-command.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,267 @@ +From 7afc1b96da3a02bef2260add64ac36111ab7558d Mon Sep 17 00:00:00 2001 +From: Pragnesh Patel +Date: Tue, 22 Dec 2020 11:30:05 +0530 +Subject: [PATCH 37/41] cmd: Add a pwm command + +Add the command "pwm" for controlling the pwm channels. This +command provides pwm invert/config/enable/disable functionalities +via PWM uclass drivers + +Signed-off-by: Pragnesh Patel +Reviewed-by: Simon Glass +(cherry picked from commit 9e9a530a61c01e412a239d8c211d5b1e26b578fa) +Signed-off-by: David Abdurachmanov +--- + README | 1 + + cmd/Kconfig | 6 +++ + cmd/Makefile | 1 + + cmd/pwm.c | 117 ++++++++++++++++++++++++++++++++++++++++++++++ + configs/sandbox_defconfig | 1 + + test/cmd/Makefile | 2 + + test/cmd/pwm.c | 47 +++++++++++++++++++ + 7 files changed, 175 insertions(+) + create mode 100644 cmd/pwm.c + create mode 100644 test/cmd/pwm.c + +diff --git a/README b/README +index 7b73a1c..599b2a0 100644 +--- a/README ++++ b/README +@@ -3160,6 +3160,7 @@ i2c - I2C sub-system + sspi - SPI utility commands + base - print or set address offset + printenv- print environment variables ++pwm - control pwm channels + setenv - set environment variables + saveenv - save environment variables to persistent storage + protect - enable or disable FLASH write protection +diff --git a/cmd/Kconfig b/cmd/Kconfig +index 1595de9..0d08510 100644 +--- a/cmd/Kconfig ++++ b/cmd/Kconfig +@@ -918,6 +918,12 @@ config CMD_GPIO + help + GPIO support. + ++config CMD_PWM ++ bool "pwm" ++ depends on DM_PWM ++ help ++ Control PWM channels, this allows invert/config/enable/disable PWM channels. ++ + config CMD_GPT + bool "GPT (GUID Partition Table) command" + select EFI_PARTITION +diff --git a/cmd/Makefile b/cmd/Makefile +index dd86675..75df3c1 100644 +--- a/cmd/Makefile ++++ b/cmd/Makefile +@@ -120,6 +120,7 @@ endif + obj-$(CONFIG_CMD_PINMUX) += pinmux.o + obj-$(CONFIG_CMD_PMC) += pmc.o + obj-$(CONFIG_CMD_PSTORE) += pstore.o ++obj-$(CONFIG_CMD_PWM) += pwm.o + obj-$(CONFIG_CMD_PXE) += pxe.o pxe_utils.o + obj-$(CONFIG_CMD_WOL) += wol.o + obj-$(CONFIG_CMD_QFW) += qfw.o +diff --git a/cmd/pwm.c b/cmd/pwm.c +new file mode 100644 +index 0000000..5849fc5 +--- /dev/null ++++ b/cmd/pwm.c +@@ -0,0 +1,117 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Control PWM channels ++ * ++ * Copyright (c) 2020 SiFive, Inc ++ * author: Pragnesh Patel ++ */ ++ ++#include ++#include ++#include ++ ++enum pwm_cmd { ++ PWM_SET_INVERT, ++ PWM_SET_CONFIG, ++ PWM_SET_ENABLE, ++ PWM_SET_DISABLE, ++}; ++ ++static int do_pwm(struct cmd_tbl *cmdtp, int flag, int argc, ++ char *const argv[]) ++{ ++ const char *str_cmd, *str_channel = NULL, *str_enable = NULL; ++ const char *str_pwm = NULL, *str_period = NULL, *str_duty = NULL; ++ enum pwm_cmd sub_cmd; ++ struct udevice *dev; ++ u32 channel, pwm_enable, pwm_dev, period_ns = 0, duty_ns = 0; ++ int ret; ++ ++ if (argc < 4) ++ return CMD_RET_USAGE; ++ ++ str_cmd = argv[1]; ++ argc -= 2; ++ argv += 2; ++ ++ if (argc > 0) { ++ str_pwm = *argv; ++ argc--; ++ argv++; ++ } ++ ++ if (!str_pwm) ++ return CMD_RET_USAGE; ++ ++ switch (*str_cmd) { ++ case 'i': ++ sub_cmd = PWM_SET_INVERT; ++ break; ++ case 'c': ++ sub_cmd = PWM_SET_CONFIG; ++ break; ++ case 'e': ++ sub_cmd = PWM_SET_ENABLE; ++ break; ++ case 'd': ++ sub_cmd = PWM_SET_DISABLE; ++ break; ++ default: ++ return CMD_RET_USAGE; ++ } ++ ++ pwm_dev = simple_strtoul(str_pwm, NULL, 10); ++ ret = uclass_get_device(UCLASS_PWM, pwm_dev, &dev); ++ if (ret) { ++ printf("pwm: '%s' not found\n", str_pwm); ++ return cmd_process_error(cmdtp, ret); ++ } ++ ++ if (argc > 0) { ++ str_channel = *argv; ++ channel = simple_strtoul(str_channel, NULL, 10); ++ argc--; ++ argv++; ++ } else { ++ return CMD_RET_USAGE; ++ } ++ ++ if (sub_cmd == PWM_SET_INVERT && argc > 0) { ++ str_enable = *argv; ++ pwm_enable = simple_strtoul(str_enable, NULL, 10); ++ ret = pwm_set_invert(dev, channel, pwm_enable); ++ } else if (sub_cmd == PWM_SET_CONFIG && argc == 2) { ++ str_period = *argv; ++ argc--; ++ argv++; ++ period_ns = simple_strtoul(str_period, NULL, 10); ++ ++ if (argc > 0) { ++ str_duty = *argv; ++ duty_ns = simple_strtoul(str_duty, NULL, 10); ++ } ++ ++ ret = pwm_set_config(dev, channel, period_ns, duty_ns); ++ } else if (sub_cmd == PWM_SET_ENABLE) { ++ ret = pwm_set_enable(dev, channel, 1); ++ } else if (sub_cmd == PWM_SET_DISABLE) { ++ ret = pwm_set_enable(dev, channel, 0); ++ } else { ++ printf("PWM arguments missing\n"); ++ return CMD_RET_FAILURE; ++ } ++ ++ if (ret) { ++ printf("error(%d)\n", ret); ++ return CMD_RET_FAILURE; ++ } ++ ++ return CMD_RET_SUCCESS; ++} ++ ++U_BOOT_CMD(pwm, 6, 0, do_pwm, ++ "control pwm channels", ++ "pwm \n" ++ "pwm \n" ++ "pwm \n" ++ "Note: All input values are in decimal"); +diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig +index f1ec701..c5eae32 100644 +--- a/configs/sandbox_defconfig ++++ b/configs/sandbox_defconfig +@@ -58,6 +58,7 @@ CONFIG_CMD_LSBLK=y + CONFIG_CMD_MUX=y + CONFIG_CMD_OSD=y + CONFIG_CMD_PCI=y ++CONFIG_CMD_PWM=y + CONFIG_CMD_READ=y + CONFIG_CMD_REMOTEPROC=y + CONFIG_CMD_SPI=y +diff --git a/test/cmd/Makefile b/test/cmd/Makefile +index 859dcda..758bc14 100644 +--- a/test/cmd/Makefile ++++ b/test/cmd/Makefile +@@ -4,3 +4,5 @@ + + obj-y += mem.o + obj-$(CONFIG_CMD_MEM_SEARCH) += mem_search.o ++obj-$(CONFIG_CMD_PWM) += pwm.o ++obj-y += setexpr.o +diff --git a/test/cmd/pwm.c b/test/cmd/pwm.c +new file mode 100644 +index 0000000..5343af8 +--- /dev/null ++++ b/test/cmd/pwm.c +@@ -0,0 +1,47 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Test for pwm command ++ * ++ * Copyright 2020 SiFive, Inc ++ * ++ * Authors: ++ * Pragnesh Patel ++ */ ++ ++#include ++#include ++#include ++#include ++ ++/* Basic test of 'pwm' command */ ++static int dm_test_pwm_cmd(struct unit_test_state *uts) ++{ ++ struct udevice *dev; ++ ++ ut_assertok(uclass_get_device(UCLASS_PWM, 0, &dev)); ++ ut_assertnonnull(dev); ++ ++ ut_assertok(console_record_reset_enable()); ++ ++ /* pwm */ ++ ut_assertok(run_command("pwm invert 0 0 1", 0)); ++ ut_assert_console_end(); ++ ++ ut_assertok(run_command("pwm invert 0 0 0", 0)); ++ ut_assert_console_end(); ++ ++ /* pwm */ ++ ut_assertok(run_command("pwm config 0 0 10 50", 0)); ++ ut_assert_console_end(); ++ ++ /* pwm */ ++ ut_assertok(run_command("pwm enable 0 0", 0)); ++ ut_assert_console_end(); ++ ++ ut_assertok(run_command("pwm disable 0 0", 0)); ++ ut_assert_console_end(); ++ ++ return 0; ++} ++ ++DM_TEST(dm_test_pwm_cmd, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT | UT_TESTF_CONSOLE_REC); +-- +2.7.4 + diff -Nru u-boot-2021.01+dfsg/debian/patches/riscv64/0038-cmd-pwm-Rework-argc-sanity-checking.patch u-boot-2021.01+dfsg/debian/patches/riscv64/0038-cmd-pwm-Rework-argc-sanity-checking.patch --- u-boot-2021.01+dfsg/debian/patches/riscv64/0038-cmd-pwm-Rework-argc-sanity-checking.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/riscv64/0038-cmd-pwm-Rework-argc-sanity-checking.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,116 @@ +From 70a5758c9428b2062408feee99931d40c334e351 Mon Sep 17 00:00:00 2001 +From: Tom Rini +Date: Tue, 26 Jan 2021 11:44:37 -0500 +Subject: [PATCH 38/41] cmd: pwm: Rework argc sanity checking + +Currently, we check argc in a number of places to make sure that we have +all of the required arguments for each of the pwm sub-commands. +However, there's at least one place where we've got dead code as we'll +never have argc == 0, due to checking that argc was at least 4 earlier +and having only subtracted 3. Rework things so that when we have +determined our subcommand make sure we have the right number of +arguments for it, or error out. This means we can stop checking against +argc again later. + +Reported-by: Coverity (CID: 316601) +Cc: Pragnesh Patel +Signed-off-by: Tom Rini +(cherry picked from commit da7991b38e1f6d9b172a72650286be2558dc447f) +Signed-off-by: David Abdurachmanov +--- + cmd/pwm.c | 41 +++++++++++++++++++---------------------- + 1 file changed, 19 insertions(+), 22 deletions(-) + +diff --git a/cmd/pwm.c b/cmd/pwm.c +index 5849fc5..e1f97c7 100644 +--- a/cmd/pwm.c ++++ b/cmd/pwm.c +@@ -34,11 +34,9 @@ static int do_pwm(struct cmd_tbl *cmdtp, int flag, int argc, + argc -= 2; + argv += 2; + +- if (argc > 0) { +- str_pwm = *argv; +- argc--; +- argv++; +- } ++ str_pwm = *argv; ++ argc--; ++ argv++; + + if (!str_pwm) + return CMD_RET_USAGE; +@@ -46,15 +44,23 @@ static int do_pwm(struct cmd_tbl *cmdtp, int flag, int argc, + switch (*str_cmd) { + case 'i': + sub_cmd = PWM_SET_INVERT; ++ if (argc != 2) ++ return CMD_RET_USAGE; + break; + case 'c': + sub_cmd = PWM_SET_CONFIG; ++ if (argc != 3) ++ return CMD_RET_USAGE; + break; + case 'e': + sub_cmd = PWM_SET_ENABLE; ++ if (argc != 1) ++ return CMD_RET_USAGE; + break; + case 'd': + sub_cmd = PWM_SET_DISABLE; ++ if (argc != 1) ++ return CMD_RET_USAGE; + break; + default: + return CMD_RET_USAGE; +@@ -67,38 +73,29 @@ static int do_pwm(struct cmd_tbl *cmdtp, int flag, int argc, + return cmd_process_error(cmdtp, ret); + } + +- if (argc > 0) { +- str_channel = *argv; +- channel = simple_strtoul(str_channel, NULL, 10); +- argc--; +- argv++; +- } else { +- return CMD_RET_USAGE; +- } ++ str_channel = *argv; ++ channel = simple_strtoul(str_channel, NULL, 10); ++ argc--; ++ argv++; + +- if (sub_cmd == PWM_SET_INVERT && argc > 0) { ++ if (sub_cmd == PWM_SET_INVERT) { + str_enable = *argv; + pwm_enable = simple_strtoul(str_enable, NULL, 10); + ret = pwm_set_invert(dev, channel, pwm_enable); +- } else if (sub_cmd == PWM_SET_CONFIG && argc == 2) { ++ } else if (sub_cmd == PWM_SET_CONFIG) { + str_period = *argv; + argc--; + argv++; + period_ns = simple_strtoul(str_period, NULL, 10); + +- if (argc > 0) { +- str_duty = *argv; +- duty_ns = simple_strtoul(str_duty, NULL, 10); +- } ++ str_duty = *argv; ++ duty_ns = simple_strtoul(str_duty, NULL, 10); + + ret = pwm_set_config(dev, channel, period_ns, duty_ns); + } else if (sub_cmd == PWM_SET_ENABLE) { + ret = pwm_set_enable(dev, channel, 1); + } else if (sub_cmd == PWM_SET_DISABLE) { + ret = pwm_set_enable(dev, channel, 0); +- } else { +- printf("PWM arguments missing\n"); +- return CMD_RET_FAILURE; + } + + if (ret) { +-- +2.7.4 + diff -Nru u-boot-2021.01+dfsg/debian/patches/riscv64/0039-riscv-sifive-unmatched-enable-PWM.patch u-boot-2021.01+dfsg/debian/patches/riscv64/0039-riscv-sifive-unmatched-enable-PWM.patch --- u-boot-2021.01+dfsg/debian/patches/riscv64/0039-riscv-sifive-unmatched-enable-PWM.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/riscv64/0039-riscv-sifive-unmatched-enable-PWM.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,24 @@ +From 4620fbafb454a858cf88c8a784513788cc11b6f1 Mon Sep 17 00:00:00 2001 +From: David Abdurachmanov +Date: Thu, 11 Mar 2021 05:42:07 -0800 +Subject: [PATCH 39/41] riscv: sifive: unmatched: enable PWM + +Signed-off-by: David Abdurachmanov +--- + configs/sifive_hifive_unmatched_fu740_defconfig | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/configs/sifive_hifive_unmatched_fu740_defconfig b/configs/sifive_hifive_unmatched_fu740_defconfig +index a853177..14fb2f7 100644 +--- a/configs/sifive_hifive_unmatched_fu740_defconfig ++++ b/configs/sifive_hifive_unmatched_fu740_defconfig +@@ -52,3 +52,6 @@ CONFIG_CMD_I2C=y + CONFIG_DM_I2C=y + CONFIG_SYS_I2C_OCORES=y + CONFIG_CLK_SIFIVE_PRCI=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_SIFIVE=y ++CONFIG_CMD_PWM=y +-- +2.7.4 + diff -Nru u-boot-2021.01+dfsg/debian/patches/riscv64/0040-riscv-sifive-unmatched-update-for-rev3-16GB-1866.patch u-boot-2021.01+dfsg/debian/patches/riscv64/0040-riscv-sifive-unmatched-update-for-rev3-16GB-1866.patch --- u-boot-2021.01+dfsg/debian/patches/riscv64/0040-riscv-sifive-unmatched-update-for-rev3-16GB-1866.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/riscv64/0040-riscv-sifive-unmatched-update-for-rev3-16GB-1866.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,3108 @@ +From 1d048519a48540a674817c338f047f96eae6b2f2 Mon Sep 17 00:00:00 2001 +From: David Abdurachmanov +Date: Thu, 11 Mar 2021 05:48:30 -0800 +Subject: [PATCH 40/41] riscv: sifive: unmatched: update for rev3 (16GB, 1866) + +The DDR clock-frequency should be 933 MHz. + +Signed-off-by: Zong Li +Signed-off-by: David Abdurachmanov +--- + arch/riscv/dts/fu740-c000-u-boot.dtsi | 2 +- + arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi | 2962 ++++++++++---------- + arch/riscv/dts/hifive-unmatched-a00.dts | 36 +- + 3 files changed, 1500 insertions(+), 1500 deletions(-) + +diff --git a/arch/riscv/dts/fu740-c000-u-boot.dtsi b/arch/riscv/dts/fu740-c000-u-boot.dtsi +index 2817b6d..b6f7545 100644 +--- a/arch/riscv/dts/fu740-c000-u-boot.dtsi ++++ b/arch/riscv/dts/fu740-c000-u-boot.dtsi +@@ -77,7 +77,7 @@ + 0x0 0x100b2000 0x0 0x2000 + 0x0 0x100b8000 0x0 0x1000>; + clocks = <&prci PRCI_CLK_DDRPLL>; +- clock-frequency = <1066000000>; ++ clock-frequency = <933333324>; + u-boot,dm-spl; + }; + }; +diff --git a/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi b/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi +index 0c4dedd..06559d9 100644 +--- a/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi ++++ b/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi +@@ -1,1489 +1,1489 @@ + // SPDX-License-Identifier: (GPL-2.0 OR MIT) + /* +- * (C) Copyright 2020 SiFive, Inc ++ * (C) Copyright 2021 SiFive, Inc + */ + + &dmc { + sifive,ddr-params = < +- 0x00000a00 /* DENALI_CTL_00_DATA */ +- 0x00000000 /* DENALI_CTL_01_DATA */ +- 0x00000000 /* DENALI_CTL_02_DATA */ +- 0x00000000 /* DENALI_CTL_03_DATA */ +- 0x00000000 /* DENALI_CTL_04_DATA */ +- 0x00000000 /* DENALI_CTL_05_DATA */ +- 0x0000000b /* DENALI_CTL_06_DATA */ +- 0x00033f1e /* DENALI_CTL_07_DATA */ +- 0x00081dcb /* DENALI_CTL_08_DATA */ +- 0x0b200300 /* DENALI_CTL_09_DATA */ +- 0x1c1c0400 /* DENALI_CTL_10_DATA */ +- 0x04049a0d /* DENALI_CTL_11_DATA */ +- 0x32060406 /* DENALI_CTL_12_DATA */ +- 0x100d0823 /* DENALI_CTL_13_DATA */ +- 0x080a0a17 /* DENALI_CTL_14_DATA */ +- 0x0123b818 /* DENALI_CTL_15_DATA */ +- 0x00180b06 /* DENALI_CTL_16_DATA */ +- 0x00a01510 /* DENALI_CTL_17_DATA */ +- 0x01000118 /* DENALI_CTL_18_DATA */ +- 0x10032501 /* DENALI_CTL_19_DATA */ +- 0x00000000 /* DENALI_CTL_20_DATA */ +- 0x00000101 /* DENALI_CTL_21_DATA */ +- 0x00000000 /* DENALI_CTL_22_DATA */ +- 0x0a000000 /* DENALI_CTL_23_DATA */ +- 0x00000000 /* DENALI_CTL_24_DATA */ +- 0x01750100 /* DENALI_CTL_25_DATA */ +- 0x00002069 /* DENALI_CTL_26_DATA */ +- 0x00000005 /* DENALI_CTL_27_DATA */ +- 0x001a0007 /* DENALI_CTL_28_DATA */ +- 0x017f0300 /* DENALI_CTL_29_DATA */ +- 0x03010000 /* DENALI_CTL_30_DATA */ +- 0x000b0f00 /* DENALI_CTL_31_DATA */ +- 0x04030200 /* DENALI_CTL_32_DATA */ +- 0x0000031f /* DENALI_CTL_33_DATA */ +- 0x00070004 /* DENALI_CTL_34_DATA */ +- 0x00000000 /* DENALI_CTL_35_DATA */ +- 0x00000000 /* DENALI_CTL_36_DATA */ +- 0x00000000 /* DENALI_CTL_37_DATA */ +- 0x00000000 /* DENALI_CTL_38_DATA */ +- 0x00000000 /* DENALI_CTL_39_DATA */ +- 0x00000000 /* DENALI_CTL_40_DATA */ +- 0x00000000 /* DENALI_CTL_41_DATA */ +- 0x00000000 /* DENALI_CTL_42_DATA */ +- 0x00000000 /* DENALI_CTL_43_DATA */ +- 0x00000000 /* DENALI_CTL_44_DATA */ +- 0x00000000 /* DENALI_CTL_45_DATA */ +- 0x00000000 /* DENALI_CTL_46_DATA */ +- 0x00000000 /* DENALI_CTL_47_DATA */ +- 0x00000000 /* DENALI_CTL_48_DATA */ +- 0x00000000 /* DENALI_CTL_49_DATA */ +- 0x00000000 /* DENALI_CTL_50_DATA */ +- 0x00000000 /* DENALI_CTL_51_DATA */ +- 0x00000000 /* DENALI_CTL_52_DATA */ +- 0x00000000 /* DENALI_CTL_53_DATA */ +- 0x00000000 /* DENALI_CTL_54_DATA */ +- 0x00000000 /* DENALI_CTL_55_DATA */ +- 0x00000000 /* DENALI_CTL_56_DATA */ +- 0x00000000 /* DENALI_CTL_57_DATA */ +- 0x00000000 /* DENALI_CTL_58_DATA */ +- 0x00000000 /* DENALI_CTL_59_DATA */ +- 0x00000634 /* DENALI_CTL_60_DATA */ +- 0x00000201 /* DENALI_CTL_61_DATA */ +- 0x00001010 /* DENALI_CTL_62_DATA */ +- 0x00000000 /* DENALI_CTL_63_DATA */ +- 0x00000200 /* DENALI_CTL_64_DATA */ +- 0x00000000 /* DENALI_CTL_65_DATA */ +- 0x00000481 /* DENALI_CTL_66_DATA */ +- 0x00000800 /* DENALI_CTL_67_DATA */ +- 0x00000634 /* DENALI_CTL_68_DATA */ +- 0x00000201 /* DENALI_CTL_69_DATA */ +- 0x00001010 /* DENALI_CTL_70_DATA */ +- 0x00000000 /* DENALI_CTL_71_DATA */ +- 0x00000200 /* DENALI_CTL_72_DATA */ +- 0x00000000 /* DENALI_CTL_73_DATA */ +- 0x00000481 /* DENALI_CTL_74_DATA */ +- 0x00000800 /* DENALI_CTL_75_DATA */ +- 0x01010000 /* DENALI_CTL_76_DATA */ +- 0x00000000 /* DENALI_CTL_77_DATA */ +- 0x00000000 /* DENALI_CTL_78_DATA */ +- 0x00000000 /* DENALI_CTL_79_DATA */ +- 0x00000000 /* DENALI_CTL_80_DATA */ +- 0x00000000 /* DENALI_CTL_81_DATA */ +- 0x00000000 /* DENALI_CTL_82_DATA */ +- 0x00000000 /* DENALI_CTL_83_DATA */ +- 0x00000000 /* DENALI_CTL_84_DATA */ +- 0x00000000 /* DENALI_CTL_85_DATA */ +- 0x00000000 /* DENALI_CTL_86_DATA */ +- 0x00000000 /* DENALI_CTL_87_DATA */ +- 0x00000000 /* DENALI_CTL_88_DATA */ +- 0x00000000 /* DENALI_CTL_89_DATA */ +- 0x00000000 /* DENALI_CTL_90_DATA */ +- 0x00000000 /* DENALI_CTL_91_DATA */ +- 0x00000000 /* DENALI_CTL_92_DATA */ +- 0x00000000 /* DENALI_CTL_93_DATA */ +- 0x00000000 /* DENALI_CTL_94_DATA */ +- 0x00000000 /* DENALI_CTL_95_DATA */ +- 0x00000000 /* DENALI_CTL_96_DATA */ +- 0x00000000 /* DENALI_CTL_97_DATA */ +- 0x00000000 /* DENALI_CTL_98_DATA */ +- 0x00000000 /* DENALI_CTL_99_DATA */ +- 0x00000000 /* DENALI_CTL_100_DATA */ +- 0x00000000 /* DENALI_CTL_101_DATA */ +- 0x00000000 /* DENALI_CTL_102_DATA */ +- 0x00000000 /* DENALI_CTL_103_DATA */ +- 0x00000000 /* DENALI_CTL_104_DATA */ +- 0x00000003 /* DENALI_CTL_105_DATA */ +- 0x00000000 /* DENALI_CTL_106_DATA */ +- 0x00000000 /* DENALI_CTL_107_DATA */ +- 0x00000000 /* DENALI_CTL_108_DATA */ +- 0x00000000 /* DENALI_CTL_109_DATA */ +- 0x01000000 /* DENALI_CTL_110_DATA */ +- 0x00040000 /* DENALI_CTL_111_DATA */ +- 0x00800200 /* DENALI_CTL_112_DATA */ +- 0x00000200 /* DENALI_CTL_113_DATA */ +- 0x00000040 /* DENALI_CTL_114_DATA */ +- 0x01000100 /* DENALI_CTL_115_DATA */ +- 0x0a000002 /* DENALI_CTL_116_DATA */ +- 0x0101ffff /* DENALI_CTL_117_DATA */ +- 0x01010101 /* DENALI_CTL_118_DATA */ +- 0x01010101 /* DENALI_CTL_119_DATA */ +- 0x0000010b /* DENALI_CTL_120_DATA */ +- 0x00000c01 /* DENALI_CTL_121_DATA */ +- 0x00000000 /* DENALI_CTL_122_DATA */ +- 0x00000000 /* DENALI_CTL_123_DATA */ +- 0x00000000 /* DENALI_CTL_124_DATA */ +- 0x00000000 /* DENALI_CTL_125_DATA */ +- 0x00030300 /* DENALI_CTL_126_DATA */ +- 0x00000000 /* DENALI_CTL_127_DATA */ +- 0x00010001 /* DENALI_CTL_128_DATA */ +- 0x00000000 /* DENALI_CTL_129_DATA */ +- 0x00000000 /* DENALI_CTL_130_DATA */ +- 0x00000000 /* DENALI_CTL_131_DATA */ +- 0x00000000 /* DENALI_CTL_132_DATA */ +- 0x00000000 /* DENALI_CTL_133_DATA */ +- 0x00000000 /* DENALI_CTL_134_DATA */ +- 0x00000000 /* DENALI_CTL_135_DATA */ +- 0x00000000 /* DENALI_CTL_136_DATA */ +- 0x00000000 /* DENALI_CTL_137_DATA */ +- 0x00000000 /* DENALI_CTL_138_DATA */ +- 0x00000000 /* DENALI_CTL_139_DATA */ +- 0x00000000 /* DENALI_CTL_140_DATA */ +- 0x00000000 /* DENALI_CTL_141_DATA */ +- 0x00000000 /* DENALI_CTL_142_DATA */ +- 0x00000000 /* DENALI_CTL_143_DATA */ +- 0x00000000 /* DENALI_CTL_144_DATA */ +- 0x00000000 /* DENALI_CTL_145_DATA */ +- 0x00000000 /* DENALI_CTL_146_DATA */ +- 0x00000000 /* DENALI_CTL_147_DATA */ +- 0x00000000 /* DENALI_CTL_148_DATA */ +- 0x00000000 /* DENALI_CTL_149_DATA */ +- 0x00000000 /* DENALI_CTL_150_DATA */ +- 0x00000000 /* DENALI_CTL_151_DATA */ +- 0x00000000 /* DENALI_CTL_152_DATA */ +- 0x00000000 /* DENALI_CTL_153_DATA */ +- 0x00000000 /* DENALI_CTL_154_DATA */ +- 0x00000000 /* DENALI_CTL_155_DATA */ +- 0x00000000 /* DENALI_CTL_156_DATA */ +- 0x00000000 /* DENALI_CTL_157_DATA */ +- 0x00000000 /* DENALI_CTL_158_DATA */ +- 0x00000000 /* DENALI_CTL_159_DATA */ +- 0x00000000 /* DENALI_CTL_160_DATA */ +- 0x02010102 /* DENALI_CTL_161_DATA */ +- 0x0107070e /* DENALI_CTL_162_DATA */ +- 0x04040500 /* DENALI_CTL_163_DATA */ +- 0x03000502 /* DENALI_CTL_164_DATA */ +- 0x00000000 /* DENALI_CTL_165_DATA */ +- 0x00000000 /* DENALI_CTL_166_DATA */ +- 0x00000000 /* DENALI_CTL_167_DATA */ +- 0x00000000 /* DENALI_CTL_168_DATA */ +- 0x280d0000 /* DENALI_CTL_169_DATA */ +- 0x01000000 /* DENALI_CTL_170_DATA */ +- 0x00000000 /* DENALI_CTL_171_DATA */ +- 0x00010001 /* DENALI_CTL_172_DATA */ +- 0x00000000 /* DENALI_CTL_173_DATA */ +- 0x00000000 /* DENALI_CTL_174_DATA */ +- 0x00000000 /* DENALI_CTL_175_DATA */ +- 0x00000000 /* DENALI_CTL_176_DATA */ +- 0x00000000 /* DENALI_CTL_177_DATA */ +- 0x00000000 /* DENALI_CTL_178_DATA */ +- 0x00000000 /* DENALI_CTL_179_DATA */ +- 0x00000000 /* DENALI_CTL_180_DATA */ +- 0x01000000 /* DENALI_CTL_181_DATA */ +- 0x00000001 /* DENALI_CTL_182_DATA */ +- 0x00000100 /* DENALI_CTL_183_DATA */ +- 0x00010101 /* DENALI_CTL_184_DATA */ +- 0x67676701 /* DENALI_CTL_185_DATA */ +- 0x67676767 /* DENALI_CTL_186_DATA */ +- 0x67676767 /* DENALI_CTL_187_DATA */ +- 0x67676767 /* DENALI_CTL_188_DATA */ +- 0x67676767 /* DENALI_CTL_189_DATA */ +- 0x67676767 /* DENALI_CTL_190_DATA */ +- 0x67676767 /* DENALI_CTL_191_DATA */ +- 0x67676767 /* DENALI_CTL_192_DATA */ +- 0x67676767 /* DENALI_CTL_193_DATA */ +- 0x01000067 /* DENALI_CTL_194_DATA */ +- 0x00000001 /* DENALI_CTL_195_DATA */ +- 0x00000101 /* DENALI_CTL_196_DATA */ +- 0x00000000 /* DENALI_CTL_197_DATA */ +- 0x00000000 /* DENALI_CTL_198_DATA */ +- 0x00000000 /* DENALI_CTL_199_DATA */ +- 0x00000000 /* DENALI_CTL_200_DATA */ +- 0x00000000 /* DENALI_CTL_201_DATA */ +- 0x00000000 /* DENALI_CTL_202_DATA */ +- 0x00000000 /* DENALI_CTL_203_DATA */ +- 0x00000000 /* DENALI_CTL_204_DATA */ +- 0x00000000 /* DENALI_CTL_205_DATA */ +- 0x00000000 /* DENALI_CTL_206_DATA */ +- 0x00000000 /* DENALI_CTL_207_DATA */ +- 0x00000001 /* DENALI_CTL_208_DATA */ +- 0x00000000 /* DENALI_CTL_209_DATA */ +- 0x007fffff /* DENALI_CTL_210_DATA */ +- 0x00000000 /* DENALI_CTL_211_DATA */ +- 0x007fffff /* DENALI_CTL_212_DATA */ +- 0x00000000 /* DENALI_CTL_213_DATA */ +- 0x007fffff /* DENALI_CTL_214_DATA */ +- 0x00000000 /* DENALI_CTL_215_DATA */ +- 0x007fffff /* DENALI_CTL_216_DATA */ +- 0x00000000 /* DENALI_CTL_217_DATA */ +- 0x007fffff /* DENALI_CTL_218_DATA */ +- 0x00000000 /* DENALI_CTL_219_DATA */ +- 0x007fffff /* DENALI_CTL_220_DATA */ +- 0x00000000 /* DENALI_CTL_221_DATA */ +- 0x007fffff /* DENALI_CTL_222_DATA */ +- 0x00000000 /* DENALI_CTL_223_DATA */ +- 0x037fffff /* DENALI_CTL_224_DATA */ +- 0xffffffff /* DENALI_CTL_225_DATA */ +- 0x000f000f /* DENALI_CTL_226_DATA */ +- 0x00ffff03 /* DENALI_CTL_227_DATA */ +- 0x000fffff /* DENALI_CTL_228_DATA */ +- 0x0003000f /* DENALI_CTL_229_DATA */ +- 0xffffffff /* DENALI_CTL_230_DATA */ +- 0x000f000f /* DENALI_CTL_231_DATA */ +- 0x00ffff03 /* DENALI_CTL_232_DATA */ +- 0x000fffff /* DENALI_CTL_233_DATA */ +- 0x0003000f /* DENALI_CTL_234_DATA */ +- 0xffffffff /* DENALI_CTL_235_DATA */ +- 0x000f000f /* DENALI_CTL_236_DATA */ +- 0x00ffff03 /* DENALI_CTL_237_DATA */ +- 0x000fffff /* DENALI_CTL_238_DATA */ +- 0x0003000f /* DENALI_CTL_239_DATA */ +- 0xffffffff /* DENALI_CTL_240_DATA */ +- 0x000f000f /* DENALI_CTL_241_DATA */ +- 0x00ffff03 /* DENALI_CTL_242_DATA */ +- 0x000fffff /* DENALI_CTL_243_DATA */ +- 0x6407000f /* DENALI_CTL_244_DATA */ +- 0x01640001 /* DENALI_CTL_245_DATA */ +- 0x00000000 /* DENALI_CTL_246_DATA */ +- 0x00000000 /* DENALI_CTL_247_DATA */ +- 0x00001900 /* DENALI_CTL_248_DATA */ +- 0x0040d205 /* DENALI_CTL_249_DATA */ +- 0x02000200 /* DENALI_CTL_250_DATA */ +- 0x02000200 /* DENALI_CTL_251_DATA */ +- 0x000040d2 /* DENALI_CTL_252_DATA */ +- 0x00028834 /* DENALI_CTL_253_DATA */ +- 0x02020e11 /* DENALI_CTL_254_DATA */ +- 0x00140303 /* DENALI_CTL_255_DATA */ +- 0x00000000 /* DENALI_CTL_256_DATA */ +- 0x00000000 /* DENALI_CTL_257_DATA */ +- 0x00001403 /* DENALI_CTL_258_DATA */ +- 0x00000000 /* DENALI_CTL_259_DATA */ +- 0x00000000 /* DENALI_CTL_260_DATA */ +- 0x00000000 /* DENALI_CTL_261_DATA */ +- 0x00000000 /* DENALI_CTL_262_DATA */ +- 0x0f010000 /* DENALI_CTL_263_DATA */ +- 0x00000009 /* DENALI_CTL_264_DATA */ +- 0x01375642 /* DENALI_PHY_00_DATA */ +- 0x0004c008 /* DENALI_PHY_01_DATA */ +- 0x00000120 /* DENALI_PHY_02_DATA */ +- 0x00000000 /* DENALI_PHY_03_DATA */ +- 0x00000000 /* DENALI_PHY_04_DATA */ +- 0x00010000 /* DENALI_PHY_05_DATA */ +- 0x01DDDD90 /* DENALI_PHY_06_DATA */ +- 0x01DDDD90 /* DENALI_PHY_07_DATA */ +- 0x01030000 /* DENALI_PHY_08_DATA */ +- 0x01000000 /* DENALI_PHY_09_DATA */ +- 0x00c00000 /* DENALI_PHY_10_DATA */ +- 0x00000007 /* DENALI_PHY_11_DATA */ +- 0x00000000 /* DENALI_PHY_12_DATA */ +- 0x00000000 /* DENALI_PHY_13_DATA */ +- 0x04000408 /* DENALI_PHY_14_DATA */ +- 0x00000408 /* DENALI_PHY_15_DATA */ +- 0x00e4e400 /* DENALI_PHY_16_DATA */ +- 0x00000000 /* DENALI_PHY_17_DATA */ +- 0x00000000 /* DENALI_PHY_18_DATA */ +- 0x00000000 /* DENALI_PHY_19_DATA */ +- 0x00000000 /* DENALI_PHY_20_DATA */ +- 0x00000000 /* DENALI_PHY_21_DATA */ +- 0x00000000 /* DENALI_PHY_22_DATA */ +- 0x00000000 /* DENALI_PHY_23_DATA */ +- 0x00000000 /* DENALI_PHY_24_DATA */ +- 0x00000000 /* DENALI_PHY_25_DATA */ +- 0x00000000 /* DENALI_PHY_26_DATA */ +- 0x00000000 /* DENALI_PHY_27_DATA */ +- 0x00000000 /* DENALI_PHY_28_DATA */ +- 0x00000000 /* DENALI_PHY_29_DATA */ +- 0x00000000 /* DENALI_PHY_30_DATA */ +- 0x00000000 /* DENALI_PHY_31_DATA */ +- 0x00000000 /* DENALI_PHY_32_DATA */ +- 0x00200000 /* DENALI_PHY_33_DATA */ +- 0x00000000 /* DENALI_PHY_34_DATA */ +- 0x00000000 /* DENALI_PHY_35_DATA */ +- 0x00000000 /* DENALI_PHY_36_DATA */ +- 0x00000000 /* DENALI_PHY_37_DATA */ +- 0x00000000 /* DENALI_PHY_38_DATA */ +- 0x00000000 /* DENALI_PHY_39_DATA */ +- 0x02800280 /* DENALI_PHY_40_DATA */ +- 0x02800280 /* DENALI_PHY_41_DATA */ +- 0x02800280 /* DENALI_PHY_42_DATA */ +- 0x02800280 /* DENALI_PHY_43_DATA */ +- 0x00000280 /* DENALI_PHY_44_DATA */ +- 0x00000000 /* DENALI_PHY_45_DATA */ +- 0x00000000 /* DENALI_PHY_46_DATA */ +- 0x00000000 /* DENALI_PHY_47_DATA */ +- 0x00000000 /* DENALI_PHY_48_DATA */ +- 0x00000000 /* DENALI_PHY_49_DATA */ +- 0x00800080 /* DENALI_PHY_50_DATA */ +- 0x00800080 /* DENALI_PHY_51_DATA */ +- 0x00800080 /* DENALI_PHY_52_DATA */ +- 0x00800080 /* DENALI_PHY_53_DATA */ +- 0x00800080 /* DENALI_PHY_54_DATA */ +- 0x00800080 /* DENALI_PHY_55_DATA */ +- 0x00800080 /* DENALI_PHY_56_DATA */ +- 0x00800080 /* DENALI_PHY_57_DATA */ +- 0x00800080 /* DENALI_PHY_58_DATA */ +- 0x00010120 /* DENALI_PHY_59_DATA */ +- 0x000001d0 /* DENALI_PHY_60_DATA */ +- 0x01000000 /* DENALI_PHY_61_DATA */ +- 0x00000000 /* DENALI_PHY_62_DATA */ +- 0x00000002 /* DENALI_PHY_63_DATA */ +- 0x51313152 /* DENALI_PHY_64_DATA */ +- 0x80013130 /* DENALI_PHY_65_DATA */ +- 0x03000080 /* DENALI_PHY_66_DATA */ +- 0x00100002 /* DENALI_PHY_67_DATA */ +- 0x0c064208 /* DENALI_PHY_68_DATA */ +- 0x000f0c0f /* DENALI_PHY_69_DATA */ +- 0x01000140 /* DENALI_PHY_70_DATA */ +- 0x0000000c /* DENALI_PHY_71_DATA */ +- 0x00000000 /* DENALI_PHY_72_DATA */ +- 0x00000000 /* DENALI_PHY_73_DATA */ +- 0x00000000 /* DENALI_PHY_74_DATA */ +- 0x00000000 /* DENALI_PHY_75_DATA */ +- 0x00000000 /* DENALI_PHY_76_DATA */ +- 0x00000000 /* DENALI_PHY_77_DATA */ +- 0x00000000 /* DENALI_PHY_78_DATA */ +- 0x00000000 /* DENALI_PHY_79_DATA */ +- 0x00000000 /* DENALI_PHY_80_DATA */ +- 0x00000000 /* DENALI_PHY_81_DATA */ +- 0x00000000 /* DENALI_PHY_82_DATA */ +- 0x00000000 /* DENALI_PHY_83_DATA */ +- 0x00000000 /* DENALI_PHY_84_DATA */ +- 0x00000000 /* DENALI_PHY_85_DATA */ +- 0x00000000 /* DENALI_PHY_86_DATA */ +- 0x00000000 /* DENALI_PHY_87_DATA */ +- 0x00000000 /* DENALI_PHY_88_DATA */ +- 0x00000000 /* DENALI_PHY_89_DATA */ +- 0x00000000 /* DENALI_PHY_90_DATA */ +- 0x00000000 /* DENALI_PHY_91_DATA */ +- 0x00000000 /* DENALI_PHY_92_DATA */ +- 0x00000000 /* DENALI_PHY_93_DATA */ +- 0x00000000 /* DENALI_PHY_94_DATA */ +- 0x00000000 /* DENALI_PHY_95_DATA */ +- 0x00000000 /* DENALI_PHY_96_DATA */ +- 0x00000000 /* DENALI_PHY_97_DATA */ +- 0x00000000 /* DENALI_PHY_98_DATA */ +- 0x00000000 /* DENALI_PHY_99_DATA */ +- 0x00000000 /* DENALI_PHY_100_DATA */ +- 0x00000000 /* DENALI_PHY_101_DATA */ +- 0x00000000 /* DENALI_PHY_102_DATA */ +- 0x00000000 /* DENALI_PHY_103_DATA */ +- 0x00000000 /* DENALI_PHY_104_DATA */ +- 0x00000000 /* DENALI_PHY_105_DATA */ +- 0x00000000 /* DENALI_PHY_106_DATA */ +- 0x00000000 /* DENALI_PHY_107_DATA */ +- 0x00000000 /* DENALI_PHY_108_DATA */ +- 0x00000000 /* DENALI_PHY_109_DATA */ +- 0x00000000 /* DENALI_PHY_110_DATA */ +- 0x00000000 /* DENALI_PHY_111_DATA */ +- 0x00000000 /* DENALI_PHY_112_DATA */ +- 0x00000000 /* DENALI_PHY_113_DATA */ +- 0x00000000 /* DENALI_PHY_114_DATA */ +- 0x00000000 /* DENALI_PHY_115_DATA */ +- 0x00000000 /* DENALI_PHY_116_DATA */ +- 0x00000000 /* DENALI_PHY_117_DATA */ +- 0x00000000 /* DENALI_PHY_118_DATA */ +- 0x00000000 /* DENALI_PHY_119_DATA */ +- 0x00000000 /* DENALI_PHY_120_DATA */ +- 0x00000000 /* DENALI_PHY_121_DATA */ +- 0x00000000 /* DENALI_PHY_122_DATA */ +- 0x00000000 /* DENALI_PHY_123_DATA */ +- 0x00000000 /* DENALI_PHY_124_DATA */ +- 0x00000000 /* DENALI_PHY_125_DATA */ +- 0x00000000 /* DENALI_PHY_126_DATA */ +- 0x00000000 /* DENALI_PHY_127_DATA */ +- 0x40263571 /* DENALI_PHY_128_DATA */ +- 0x0004c008 /* DENALI_PHY_129_DATA */ +- 0x00000120 /* DENALI_PHY_130_DATA */ +- 0x00000000 /* DENALI_PHY_131_DATA */ +- 0x00000000 /* DENALI_PHY_132_DATA */ +- 0x00010000 /* DENALI_PHY_133_DATA */ +- 0x01DDDD90 /* DENALI_PHY_134_DATA */ +- 0x01DDDD90 /* DENALI_PHY_135_DATA */ +- 0x01030000 /* DENALI_PHY_136_DATA */ +- 0x01000000 /* DENALI_PHY_137_DATA */ +- 0x00c00000 /* DENALI_PHY_138_DATA */ +- 0x00000007 /* DENALI_PHY_139_DATA */ +- 0x00000000 /* DENALI_PHY_140_DATA */ +- 0x00000000 /* DENALI_PHY_141_DATA */ +- 0x04000408 /* DENALI_PHY_142_DATA */ +- 0x00000408 /* DENALI_PHY_143_DATA */ +- 0x00e4e400 /* DENALI_PHY_144_DATA */ +- 0x00000000 /* DENALI_PHY_145_DATA */ +- 0x00000000 /* DENALI_PHY_146_DATA */ +- 0x00000000 /* DENALI_PHY_147_DATA */ +- 0x00000000 /* DENALI_PHY_148_DATA */ +- 0x00000000 /* DENALI_PHY_149_DATA */ +- 0x00000000 /* DENALI_PHY_150_DATA */ +- 0x00000000 /* DENALI_PHY_151_DATA */ +- 0x00000000 /* DENALI_PHY_152_DATA */ +- 0x00000000 /* DENALI_PHY_153_DATA */ +- 0x00000000 /* DENALI_PHY_154_DATA */ +- 0x00000000 /* DENALI_PHY_155_DATA */ +- 0x00000000 /* DENALI_PHY_156_DATA */ +- 0x00000000 /* DENALI_PHY_157_DATA */ +- 0x00000000 /* DENALI_PHY_158_DATA */ +- 0x00000000 /* DENALI_PHY_159_DATA */ +- 0x00000000 /* DENALI_PHY_160_DATA */ +- 0x00200000 /* DENALI_PHY_161_DATA */ +- 0x00000000 /* DENALI_PHY_162_DATA */ +- 0x00000000 /* DENALI_PHY_163_DATA */ +- 0x00000000 /* DENALI_PHY_164_DATA */ +- 0x00000000 /* DENALI_PHY_165_DATA */ +- 0x00000000 /* DENALI_PHY_166_DATA */ +- 0x00000000 /* DENALI_PHY_167_DATA */ +- 0x02800280 /* DENALI_PHY_168_DATA */ +- 0x02800280 /* DENALI_PHY_169_DATA */ +- 0x02800280 /* DENALI_PHY_170_DATA */ +- 0x02800280 /* DENALI_PHY_171_DATA */ +- 0x00000280 /* DENALI_PHY_172_DATA */ +- 0x00000000 /* DENALI_PHY_173_DATA */ +- 0x00000000 /* DENALI_PHY_174_DATA */ +- 0x00000000 /* DENALI_PHY_175_DATA */ +- 0x00000000 /* DENALI_PHY_176_DATA */ +- 0x00000000 /* DENALI_PHY_177_DATA */ +- 0x00800080 /* DENALI_PHY_178_DATA */ +- 0x00800080 /* DENALI_PHY_179_DATA */ +- 0x00800080 /* DENALI_PHY_180_DATA */ +- 0x00800080 /* DENALI_PHY_181_DATA */ +- 0x00800080 /* DENALI_PHY_182_DATA */ +- 0x00800080 /* DENALI_PHY_183_DATA */ +- 0x00800080 /* DENALI_PHY_184_DATA */ +- 0x00800080 /* DENALI_PHY_185_DATA */ +- 0x00800080 /* DENALI_PHY_186_DATA */ +- 0x00010120 /* DENALI_PHY_187_DATA */ +- 0x000001d0 /* DENALI_PHY_188_DATA */ +- 0x01000000 /* DENALI_PHY_189_DATA */ +- 0x00000000 /* DENALI_PHY_190_DATA */ +- 0x00000002 /* DENALI_PHY_191_DATA */ +- 0x51313152 /* DENALI_PHY_192_DATA */ +- 0x80013130 /* DENALI_PHY_193_DATA */ +- 0x03000080 /* DENALI_PHY_194_DATA */ +- 0x00100002 /* DENALI_PHY_195_DATA */ +- 0x0c064208 /* DENALI_PHY_196_DATA */ +- 0x000f0c0f /* DENALI_PHY_197_DATA */ +- 0x01000140 /* DENALI_PHY_198_DATA */ +- 0x0000000c /* DENALI_PHY_199_DATA */ +- 0x00000000 /* DENALI_PHY_200_DATA */ +- 0x00000000 /* DENALI_PHY_201_DATA */ +- 0x00000000 /* DENALI_PHY_202_DATA */ +- 0x00000000 /* DENALI_PHY_203_DATA */ +- 0x00000000 /* DENALI_PHY_204_DATA */ +- 0x00000000 /* DENALI_PHY_205_DATA */ +- 0x00000000 /* DENALI_PHY_206_DATA */ +- 0x00000000 /* DENALI_PHY_207_DATA */ +- 0x00000000 /* DENALI_PHY_208_DATA */ +- 0x00000000 /* DENALI_PHY_209_DATA */ +- 0x00000000 /* DENALI_PHY_210_DATA */ +- 0x00000000 /* DENALI_PHY_211_DATA */ +- 0x00000000 /* DENALI_PHY_212_DATA */ +- 0x00000000 /* DENALI_PHY_213_DATA */ +- 0x00000000 /* DENALI_PHY_214_DATA */ +- 0x00000000 /* DENALI_PHY_215_DATA */ +- 0x00000000 /* DENALI_PHY_216_DATA */ +- 0x00000000 /* DENALI_PHY_217_DATA */ +- 0x00000000 /* DENALI_PHY_218_DATA */ +- 0x00000000 /* DENALI_PHY_219_DATA */ +- 0x00000000 /* DENALI_PHY_220_DATA */ +- 0x00000000 /* DENALI_PHY_221_DATA */ +- 0x00000000 /* DENALI_PHY_222_DATA */ +- 0x00000000 /* DENALI_PHY_223_DATA */ +- 0x00000000 /* DENALI_PHY_224_DATA */ +- 0x00000000 /* DENALI_PHY_225_DATA */ +- 0x00000000 /* DENALI_PHY_226_DATA */ +- 0x00000000 /* DENALI_PHY_227_DATA */ +- 0x00000000 /* DENALI_PHY_228_DATA */ +- 0x00000000 /* DENALI_PHY_229_DATA */ +- 0x00000000 /* DENALI_PHY_230_DATA */ +- 0x00000000 /* DENALI_PHY_231_DATA */ +- 0x00000000 /* DENALI_PHY_232_DATA */ +- 0x00000000 /* DENALI_PHY_233_DATA */ +- 0x00000000 /* DENALI_PHY_234_DATA */ +- 0x00000000 /* DENALI_PHY_235_DATA */ +- 0x00000000 /* DENALI_PHY_236_DATA */ +- 0x00000000 /* DENALI_PHY_237_DATA */ +- 0x00000000 /* DENALI_PHY_238_DATA */ +- 0x00000000 /* DENALI_PHY_239_DATA */ +- 0x00000000 /* DENALI_PHY_240_DATA */ +- 0x00000000 /* DENALI_PHY_241_DATA */ +- 0x00000000 /* DENALI_PHY_242_DATA */ +- 0x00000000 /* DENALI_PHY_243_DATA */ +- 0x00000000 /* DENALI_PHY_244_DATA */ +- 0x00000000 /* DENALI_PHY_245_DATA */ +- 0x00000000 /* DENALI_PHY_246_DATA */ +- 0x00000000 /* DENALI_PHY_247_DATA */ +- 0x00000000 /* DENALI_PHY_248_DATA */ +- 0x00000000 /* DENALI_PHY_249_DATA */ +- 0x00000000 /* DENALI_PHY_250_DATA */ +- 0x00000000 /* DENALI_PHY_251_DATA */ +- 0x00000000 /* DENALI_PHY_252_DATA */ +- 0x00000000 /* DENALI_PHY_253_DATA */ +- 0x00000000 /* DENALI_PHY_254_DATA */ +- 0x00000000 /* DENALI_PHY_255_DATA */ +- 0x46052371 /* DENALI_PHY_256_DATA */ +- 0x0004c008 /* DENALI_PHY_257_DATA */ +- 0x00000120 /* DENALI_PHY_258_DATA */ +- 0x00000000 /* DENALI_PHY_259_DATA */ +- 0x00000000 /* DENALI_PHY_260_DATA */ +- 0x00010000 /* DENALI_PHY_261_DATA */ +- 0x01DDDD90 /* DENALI_PHY_262_DATA */ +- 0x01DDDD90 /* DENALI_PHY_263_DATA */ +- 0x01030000 /* DENALI_PHY_264_DATA */ +- 0x01000000 /* DENALI_PHY_265_DATA */ +- 0x00c00000 /* DENALI_PHY_266_DATA */ +- 0x00000007 /* DENALI_PHY_267_DATA */ +- 0x00000000 /* DENALI_PHY_268_DATA */ +- 0x00000000 /* DENALI_PHY_269_DATA */ +- 0x04000408 /* DENALI_PHY_270_DATA */ +- 0x00000408 /* DENALI_PHY_271_DATA */ +- 0x00e4e400 /* DENALI_PHY_272_DATA */ +- 0x00000000 /* DENALI_PHY_273_DATA */ +- 0x00000000 /* DENALI_PHY_274_DATA */ +- 0x00000000 /* DENALI_PHY_275_DATA */ +- 0x00000000 /* DENALI_PHY_276_DATA */ +- 0x00000000 /* DENALI_PHY_277_DATA */ +- 0x00000000 /* DENALI_PHY_278_DATA */ +- 0x00000000 /* DENALI_PHY_279_DATA */ +- 0x00000000 /* DENALI_PHY_280_DATA */ +- 0x00000000 /* DENALI_PHY_281_DATA */ +- 0x00000000 /* DENALI_PHY_282_DATA */ +- 0x00000000 /* DENALI_PHY_283_DATA */ +- 0x00000000 /* DENALI_PHY_284_DATA */ +- 0x00000000 /* DENALI_PHY_285_DATA */ +- 0x00000000 /* DENALI_PHY_286_DATA */ +- 0x00000000 /* DENALI_PHY_287_DATA */ +- 0x00000000 /* DENALI_PHY_288_DATA */ +- 0x00200000 /* DENALI_PHY_289_DATA */ +- 0x00000000 /* DENALI_PHY_290_DATA */ +- 0x00000000 /* DENALI_PHY_291_DATA */ +- 0x00000000 /* DENALI_PHY_292_DATA */ +- 0x00000000 /* DENALI_PHY_293_DATA */ +- 0x00000000 /* DENALI_PHY_294_DATA */ +- 0x00000000 /* DENALI_PHY_295_DATA */ +- 0x02800280 /* DENALI_PHY_296_DATA */ +- 0x02800280 /* DENALI_PHY_297_DATA */ +- 0x02800280 /* DENALI_PHY_298_DATA */ +- 0x02800280 /* DENALI_PHY_299_DATA */ +- 0x00000280 /* DENALI_PHY_300_DATA */ +- 0x00000000 /* DENALI_PHY_301_DATA */ +- 0x00000000 /* DENALI_PHY_302_DATA */ +- 0x00000000 /* DENALI_PHY_303_DATA */ +- 0x00000000 /* DENALI_PHY_304_DATA */ +- 0x00000000 /* DENALI_PHY_305_DATA */ +- 0x00800080 /* DENALI_PHY_306_DATA */ +- 0x00800080 /* DENALI_PHY_307_DATA */ +- 0x00800080 /* DENALI_PHY_308_DATA */ +- 0x00800080 /* DENALI_PHY_309_DATA */ +- 0x00800080 /* DENALI_PHY_310_DATA */ +- 0x00800080 /* DENALI_PHY_311_DATA */ +- 0x00800080 /* DENALI_PHY_312_DATA */ +- 0x00800080 /* DENALI_PHY_313_DATA */ +- 0x00800080 /* DENALI_PHY_314_DATA */ +- 0x00010120 /* DENALI_PHY_315_DATA */ +- 0x000001d0 /* DENALI_PHY_316_DATA */ +- 0x01000000 /* DENALI_PHY_317_DATA */ +- 0x00000000 /* DENALI_PHY_318_DATA */ +- 0x00000002 /* DENALI_PHY_319_DATA */ +- 0x51313152 /* DENALI_PHY_320_DATA */ +- 0x80013130 /* DENALI_PHY_321_DATA */ +- 0x03000080 /* DENALI_PHY_322_DATA */ +- 0x00100002 /* DENALI_PHY_323_DATA */ +- 0x0c064208 /* DENALI_PHY_324_DATA */ +- 0x000f0c0f /* DENALI_PHY_325_DATA */ +- 0x01000140 /* DENALI_PHY_326_DATA */ +- 0x0000000c /* DENALI_PHY_327_DATA */ +- 0x00000000 /* DENALI_PHY_328_DATA */ +- 0x00000000 /* DENALI_PHY_329_DATA */ +- 0x00000000 /* DENALI_PHY_330_DATA */ +- 0x00000000 /* DENALI_PHY_331_DATA */ +- 0x00000000 /* DENALI_PHY_332_DATA */ +- 0x00000000 /* DENALI_PHY_333_DATA */ +- 0x00000000 /* DENALI_PHY_334_DATA */ +- 0x00000000 /* DENALI_PHY_335_DATA */ +- 0x00000000 /* DENALI_PHY_336_DATA */ +- 0x00000000 /* DENALI_PHY_337_DATA */ +- 0x00000000 /* DENALI_PHY_338_DATA */ +- 0x00000000 /* DENALI_PHY_339_DATA */ +- 0x00000000 /* DENALI_PHY_340_DATA */ +- 0x00000000 /* DENALI_PHY_341_DATA */ +- 0x00000000 /* DENALI_PHY_342_DATA */ +- 0x00000000 /* DENALI_PHY_343_DATA */ +- 0x00000000 /* DENALI_PHY_344_DATA */ +- 0x00000000 /* DENALI_PHY_345_DATA */ +- 0x00000000 /* DENALI_PHY_346_DATA */ +- 0x00000000 /* DENALI_PHY_347_DATA */ +- 0x00000000 /* DENALI_PHY_348_DATA */ +- 0x00000000 /* DENALI_PHY_349_DATA */ +- 0x00000000 /* DENALI_PHY_350_DATA */ +- 0x00000000 /* DENALI_PHY_351_DATA */ +- 0x00000000 /* DENALI_PHY_352_DATA */ +- 0x00000000 /* DENALI_PHY_353_DATA */ +- 0x00000000 /* DENALI_PHY_354_DATA */ +- 0x00000000 /* DENALI_PHY_355_DATA */ +- 0x00000000 /* DENALI_PHY_356_DATA */ +- 0x00000000 /* DENALI_PHY_357_DATA */ +- 0x00000000 /* DENALI_PHY_358_DATA */ +- 0x00000000 /* DENALI_PHY_359_DATA */ +- 0x00000000 /* DENALI_PHY_360_DATA */ +- 0x00000000 /* DENALI_PHY_361_DATA */ +- 0x00000000 /* DENALI_PHY_362_DATA */ +- 0x00000000 /* DENALI_PHY_363_DATA */ +- 0x00000000 /* DENALI_PHY_364_DATA */ +- 0x00000000 /* DENALI_PHY_365_DATA */ +- 0x00000000 /* DENALI_PHY_366_DATA */ +- 0x00000000 /* DENALI_PHY_367_DATA */ +- 0x00000000 /* DENALI_PHY_368_DATA */ +- 0x00000000 /* DENALI_PHY_369_DATA */ +- 0x00000000 /* DENALI_PHY_370_DATA */ +- 0x00000000 /* DENALI_PHY_371_DATA */ +- 0x00000000 /* DENALI_PHY_372_DATA */ +- 0x00000000 /* DENALI_PHY_373_DATA */ +- 0x00000000 /* DENALI_PHY_374_DATA */ +- 0x00000000 /* DENALI_PHY_375_DATA */ +- 0x00000000 /* DENALI_PHY_376_DATA */ +- 0x00000000 /* DENALI_PHY_377_DATA */ +- 0x00000000 /* DENALI_PHY_378_DATA */ +- 0x00000000 /* DENALI_PHY_379_DATA */ +- 0x00000000 /* DENALI_PHY_380_DATA */ +- 0x00000000 /* DENALI_PHY_381_DATA */ +- 0x00000000 /* DENALI_PHY_382_DATA */ +- 0x00000000 /* DENALI_PHY_383_DATA */ +- 0x37651240 /* DENALI_PHY_384_DATA */ +- 0x0004c008 /* DENALI_PHY_385_DATA */ +- 0x00000120 /* DENALI_PHY_386_DATA */ +- 0x00000000 /* DENALI_PHY_387_DATA */ +- 0x00000000 /* DENALI_PHY_388_DATA */ +- 0x00010000 /* DENALI_PHY_389_DATA */ +- 0x01DDDD90 /* DENALI_PHY_390_DATA */ +- 0x01DDDD90 /* DENALI_PHY_391_DATA */ +- 0x01030000 /* DENALI_PHY_392_DATA */ +- 0x01000000 /* DENALI_PHY_393_DATA */ +- 0x00c00000 /* DENALI_PHY_394_DATA */ +- 0x00000007 /* DENALI_PHY_395_DATA */ +- 0x00000000 /* DENALI_PHY_396_DATA */ +- 0x00000000 /* DENALI_PHY_397_DATA */ +- 0x04000408 /* DENALI_PHY_398_DATA */ +- 0x00000408 /* DENALI_PHY_399_DATA */ +- 0x00e4e400 /* DENALI_PHY_400_DATA */ +- 0x00000000 /* DENALI_PHY_401_DATA */ +- 0x00000000 /* DENALI_PHY_402_DATA */ +- 0x00000000 /* DENALI_PHY_403_DATA */ +- 0x00000000 /* DENALI_PHY_404_DATA */ +- 0x00000000 /* DENALI_PHY_405_DATA */ +- 0x00000000 /* DENALI_PHY_406_DATA */ +- 0x00000000 /* DENALI_PHY_407_DATA */ +- 0x00000000 /* DENALI_PHY_408_DATA */ +- 0x00000000 /* DENALI_PHY_409_DATA */ +- 0x00000000 /* DENALI_PHY_410_DATA */ +- 0x00000000 /* DENALI_PHY_411_DATA */ +- 0x00000000 /* DENALI_PHY_412_DATA */ +- 0x00000000 /* DENALI_PHY_413_DATA */ +- 0x00000000 /* DENALI_PHY_414_DATA */ +- 0x00000000 /* DENALI_PHY_415_DATA */ +- 0x00000000 /* DENALI_PHY_416_DATA */ +- 0x00200000 /* DENALI_PHY_417_DATA */ +- 0x00000000 /* DENALI_PHY_418_DATA */ +- 0x00000000 /* DENALI_PHY_419_DATA */ +- 0x00000000 /* DENALI_PHY_420_DATA */ +- 0x00000000 /* DENALI_PHY_421_DATA */ +- 0x00000000 /* DENALI_PHY_422_DATA */ +- 0x00000000 /* DENALI_PHY_423_DATA */ +- 0x02800280 /* DENALI_PHY_424_DATA */ +- 0x02800280 /* DENALI_PHY_425_DATA */ +- 0x02800280 /* DENALI_PHY_426_DATA */ +- 0x02800280 /* DENALI_PHY_427_DATA */ +- 0x00000280 /* DENALI_PHY_428_DATA */ +- 0x00000000 /* DENALI_PHY_429_DATA */ +- 0x00000000 /* DENALI_PHY_430_DATA */ +- 0x00000000 /* DENALI_PHY_431_DATA */ +- 0x00000000 /* DENALI_PHY_432_DATA */ +- 0x00000000 /* DENALI_PHY_433_DATA */ +- 0x00800080 /* DENALI_PHY_434_DATA */ +- 0x00800080 /* DENALI_PHY_435_DATA */ +- 0x00800080 /* DENALI_PHY_436_DATA */ +- 0x00800080 /* DENALI_PHY_437_DATA */ +- 0x00800080 /* DENALI_PHY_438_DATA */ +- 0x00800080 /* DENALI_PHY_439_DATA */ +- 0x00800080 /* DENALI_PHY_440_DATA */ +- 0x00800080 /* DENALI_PHY_441_DATA */ +- 0x00800080 /* DENALI_PHY_442_DATA */ +- 0x00010120 /* DENALI_PHY_443_DATA */ +- 0x000001d0 /* DENALI_PHY_444_DATA */ +- 0x01000000 /* DENALI_PHY_445_DATA */ +- 0x00000000 /* DENALI_PHY_446_DATA */ +- 0x00000002 /* DENALI_PHY_447_DATA */ +- 0x51313152 /* DENALI_PHY_448_DATA */ +- 0x80013130 /* DENALI_PHY_449_DATA */ +- 0x03000080 /* DENALI_PHY_450_DATA */ +- 0x00100002 /* DENALI_PHY_451_DATA */ +- 0x0c064208 /* DENALI_PHY_452_DATA */ +- 0x000f0c0f /* DENALI_PHY_453_DATA */ +- 0x01000140 /* DENALI_PHY_454_DATA */ +- 0x0000000c /* DENALI_PHY_455_DATA */ +- 0x00000000 /* DENALI_PHY_456_DATA */ +- 0x00000000 /* DENALI_PHY_457_DATA */ +- 0x00000000 /* DENALI_PHY_458_DATA */ +- 0x00000000 /* DENALI_PHY_459_DATA */ +- 0x00000000 /* DENALI_PHY_460_DATA */ +- 0x00000000 /* DENALI_PHY_461_DATA */ +- 0x00000000 /* DENALI_PHY_462_DATA */ +- 0x00000000 /* DENALI_PHY_463_DATA */ +- 0x00000000 /* DENALI_PHY_464_DATA */ +- 0x00000000 /* DENALI_PHY_465_DATA */ +- 0x00000000 /* DENALI_PHY_466_DATA */ +- 0x00000000 /* DENALI_PHY_467_DATA */ +- 0x00000000 /* DENALI_PHY_468_DATA */ +- 0x00000000 /* DENALI_PHY_469_DATA */ +- 0x00000000 /* DENALI_PHY_470_DATA */ +- 0x00000000 /* DENALI_PHY_471_DATA */ +- 0x00000000 /* DENALI_PHY_472_DATA */ +- 0x00000000 /* DENALI_PHY_473_DATA */ +- 0x00000000 /* DENALI_PHY_474_DATA */ +- 0x00000000 /* DENALI_PHY_475_DATA */ +- 0x00000000 /* DENALI_PHY_476_DATA */ +- 0x00000000 /* DENALI_PHY_477_DATA */ +- 0x00000000 /* DENALI_PHY_478_DATA */ +- 0x00000000 /* DENALI_PHY_479_DATA */ +- 0x00000000 /* DENALI_PHY_480_DATA */ +- 0x00000000 /* DENALI_PHY_481_DATA */ +- 0x00000000 /* DENALI_PHY_482_DATA */ +- 0x00000000 /* DENALI_PHY_483_DATA */ +- 0x00000000 /* DENALI_PHY_484_DATA */ +- 0x00000000 /* DENALI_PHY_485_DATA */ +- 0x00000000 /* DENALI_PHY_486_DATA */ +- 0x00000000 /* DENALI_PHY_487_DATA */ +- 0x00000000 /* DENALI_PHY_488_DATA */ +- 0x00000000 /* DENALI_PHY_489_DATA */ +- 0x00000000 /* DENALI_PHY_490_DATA */ +- 0x00000000 /* DENALI_PHY_491_DATA */ +- 0x00000000 /* DENALI_PHY_492_DATA */ +- 0x00000000 /* DENALI_PHY_493_DATA */ +- 0x00000000 /* DENALI_PHY_494_DATA */ +- 0x00000000 /* DENALI_PHY_495_DATA */ +- 0x00000000 /* DENALI_PHY_496_DATA */ +- 0x00000000 /* DENALI_PHY_497_DATA */ +- 0x00000000 /* DENALI_PHY_498_DATA */ +- 0x00000000 /* DENALI_PHY_499_DATA */ +- 0x00000000 /* DENALI_PHY_500_DATA */ +- 0x00000000 /* DENALI_PHY_501_DATA */ +- 0x00000000 /* DENALI_PHY_502_DATA */ +- 0x00000000 /* DENALI_PHY_503_DATA */ +- 0x00000000 /* DENALI_PHY_504_DATA */ +- 0x00000000 /* DENALI_PHY_505_DATA */ +- 0x00000000 /* DENALI_PHY_506_DATA */ +- 0x00000000 /* DENALI_PHY_507_DATA */ +- 0x00000000 /* DENALI_PHY_508_DATA */ +- 0x00000000 /* DENALI_PHY_509_DATA */ +- 0x00000000 /* DENALI_PHY_510_DATA */ +- 0x00000000 /* DENALI_PHY_511_DATA */ +- 0x34216750 /* DENALI_PHY_512_DATA */ +- 0x0004c008 /* DENALI_PHY_513_DATA */ +- 0x00000120 /* DENALI_PHY_514_DATA */ +- 0x00000000 /* DENALI_PHY_515_DATA */ +- 0x00000000 /* DENALI_PHY_516_DATA */ +- 0x00010000 /* DENALI_PHY_517_DATA */ +- 0x01DDDD90 /* DENALI_PHY_518_DATA */ +- 0x01DDDD90 /* DENALI_PHY_519_DATA */ +- 0x01030000 /* DENALI_PHY_520_DATA */ +- 0x01000000 /* DENALI_PHY_521_DATA */ +- 0x00c00000 /* DENALI_PHY_522_DATA */ +- 0x00000007 /* DENALI_PHY_523_DATA */ +- 0x00000000 /* DENALI_PHY_524_DATA */ +- 0x00000000 /* DENALI_PHY_525_DATA */ +- 0x04000408 /* DENALI_PHY_526_DATA */ +- 0x00000408 /* DENALI_PHY_527_DATA */ +- 0x00e4e400 /* DENALI_PHY_528_DATA */ +- 0x00000000 /* DENALI_PHY_529_DATA */ +- 0x00000000 /* DENALI_PHY_530_DATA */ +- 0x00000000 /* DENALI_PHY_531_DATA */ +- 0x00000000 /* DENALI_PHY_532_DATA */ +- 0x00000000 /* DENALI_PHY_533_DATA */ +- 0x00000000 /* DENALI_PHY_534_DATA */ +- 0x00000000 /* DENALI_PHY_535_DATA */ +- 0x00000000 /* DENALI_PHY_536_DATA */ +- 0x00000000 /* DENALI_PHY_537_DATA */ +- 0x00000000 /* DENALI_PHY_538_DATA */ +- 0x00000000 /* DENALI_PHY_539_DATA */ +- 0x00000000 /* DENALI_PHY_540_DATA */ +- 0x00000000 /* DENALI_PHY_541_DATA */ +- 0x00000000 /* DENALI_PHY_542_DATA */ +- 0x00000000 /* DENALI_PHY_543_DATA */ +- 0x00000000 /* DENALI_PHY_544_DATA */ +- 0x00200000 /* DENALI_PHY_545_DATA */ +- 0x00000000 /* DENALI_PHY_546_DATA */ +- 0x00000000 /* DENALI_PHY_547_DATA */ +- 0x00000000 /* DENALI_PHY_548_DATA */ +- 0x00000000 /* DENALI_PHY_549_DATA */ +- 0x00000000 /* DENALI_PHY_550_DATA */ +- 0x00000000 /* DENALI_PHY_551_DATA */ +- 0x02800280 /* DENALI_PHY_552_DATA */ +- 0x02800280 /* DENALI_PHY_553_DATA */ +- 0x02800280 /* DENALI_PHY_554_DATA */ +- 0x02800280 /* DENALI_PHY_555_DATA */ +- 0x00000280 /* DENALI_PHY_556_DATA */ +- 0x00000000 /* DENALI_PHY_557_DATA */ +- 0x00000000 /* DENALI_PHY_558_DATA */ +- 0x00000000 /* DENALI_PHY_559_DATA */ +- 0x00000000 /* DENALI_PHY_560_DATA */ +- 0x00000000 /* DENALI_PHY_561_DATA */ +- 0x00800080 /* DENALI_PHY_562_DATA */ +- 0x00800080 /* DENALI_PHY_563_DATA */ +- 0x00800080 /* DENALI_PHY_564_DATA */ +- 0x00800080 /* DENALI_PHY_565_DATA */ +- 0x00800080 /* DENALI_PHY_566_DATA */ +- 0x00800080 /* DENALI_PHY_567_DATA */ +- 0x00800080 /* DENALI_PHY_568_DATA */ +- 0x00800080 /* DENALI_PHY_569_DATA */ +- 0x00800080 /* DENALI_PHY_570_DATA */ +- 0x00010120 /* DENALI_PHY_571_DATA */ +- 0x000001d0 /* DENALI_PHY_572_DATA */ +- 0x01000000 /* DENALI_PHY_573_DATA */ +- 0x00000000 /* DENALI_PHY_574_DATA */ +- 0x00000002 /* DENALI_PHY_575_DATA */ +- 0x51313152 /* DENALI_PHY_576_DATA */ +- 0x80013130 /* DENALI_PHY_577_DATA */ +- 0x03000080 /* DENALI_PHY_578_DATA */ +- 0x00100002 /* DENALI_PHY_579_DATA */ +- 0x0c064208 /* DENALI_PHY_580_DATA */ +- 0x000f0c0f /* DENALI_PHY_581_DATA */ +- 0x01000140 /* DENALI_PHY_582_DATA */ +- 0x0000000c /* DENALI_PHY_583_DATA */ +- 0x00000000 /* DENALI_PHY_584_DATA */ +- 0x00000000 /* DENALI_PHY_585_DATA */ +- 0x00000000 /* DENALI_PHY_586_DATA */ +- 0x00000000 /* DENALI_PHY_587_DATA */ +- 0x00000000 /* DENALI_PHY_588_DATA */ +- 0x00000000 /* DENALI_PHY_589_DATA */ +- 0x00000000 /* DENALI_PHY_590_DATA */ +- 0x00000000 /* DENALI_PHY_591_DATA */ +- 0x00000000 /* DENALI_PHY_592_DATA */ +- 0x00000000 /* DENALI_PHY_593_DATA */ +- 0x00000000 /* DENALI_PHY_594_DATA */ +- 0x00000000 /* DENALI_PHY_595_DATA */ +- 0x00000000 /* DENALI_PHY_596_DATA */ +- 0x00000000 /* DENALI_PHY_597_DATA */ +- 0x00000000 /* DENALI_PHY_598_DATA */ +- 0x00000000 /* DENALI_PHY_599_DATA */ +- 0x00000000 /* DENALI_PHY_600_DATA */ +- 0x00000000 /* DENALI_PHY_601_DATA */ +- 0x00000000 /* DENALI_PHY_602_DATA */ +- 0x00000000 /* DENALI_PHY_603_DATA */ +- 0x00000000 /* DENALI_PHY_604_DATA */ +- 0x00000000 /* DENALI_PHY_605_DATA */ +- 0x00000000 /* DENALI_PHY_606_DATA */ +- 0x00000000 /* DENALI_PHY_607_DATA */ +- 0x00000000 /* DENALI_PHY_608_DATA */ +- 0x00000000 /* DENALI_PHY_609_DATA */ +- 0x00000000 /* DENALI_PHY_610_DATA */ +- 0x00000000 /* DENALI_PHY_611_DATA */ +- 0x00000000 /* DENALI_PHY_612_DATA */ +- 0x00000000 /* DENALI_PHY_613_DATA */ +- 0x00000000 /* DENALI_PHY_614_DATA */ +- 0x00000000 /* DENALI_PHY_615_DATA */ +- 0x00000000 /* DENALI_PHY_616_DATA */ +- 0x00000000 /* DENALI_PHY_617_DATA */ +- 0x00000000 /* DENALI_PHY_618_DATA */ +- 0x00000000 /* DENALI_PHY_619_DATA */ +- 0x00000000 /* DENALI_PHY_620_DATA */ +- 0x00000000 /* DENALI_PHY_621_DATA */ +- 0x00000000 /* DENALI_PHY_622_DATA */ +- 0x00000000 /* DENALI_PHY_623_DATA */ +- 0x00000000 /* DENALI_PHY_624_DATA */ +- 0x00000000 /* DENALI_PHY_625_DATA */ +- 0x00000000 /* DENALI_PHY_626_DATA */ +- 0x00000000 /* DENALI_PHY_627_DATA */ +- 0x00000000 /* DENALI_PHY_628_DATA */ +- 0x00000000 /* DENALI_PHY_629_DATA */ +- 0x00000000 /* DENALI_PHY_630_DATA */ +- 0x00000000 /* DENALI_PHY_631_DATA */ +- 0x00000000 /* DENALI_PHY_632_DATA */ +- 0x00000000 /* DENALI_PHY_633_DATA */ +- 0x00000000 /* DENALI_PHY_634_DATA */ +- 0x00000000 /* DENALI_PHY_635_DATA */ +- 0x00000000 /* DENALI_PHY_636_DATA */ +- 0x00000000 /* DENALI_PHY_637_DATA */ +- 0x00000000 /* DENALI_PHY_638_DATA */ +- 0x00000000 /* DENALI_PHY_639_DATA */ +- 0x35176402 /* DENALI_PHY_640_DATA */ +- 0x0004c008 /* DENALI_PHY_641_DATA */ +- 0x00000120 /* DENALI_PHY_642_DATA */ +- 0x00000000 /* DENALI_PHY_643_DATA */ +- 0x00000000 /* DENALI_PHY_644_DATA */ +- 0x00010000 /* DENALI_PHY_645_DATA */ +- 0x01DDDD90 /* DENALI_PHY_646_DATA */ +- 0x01DDDD90 /* DENALI_PHY_647_DATA */ +- 0x01030000 /* DENALI_PHY_648_DATA */ +- 0x01000000 /* DENALI_PHY_649_DATA */ +- 0x00c00000 /* DENALI_PHY_650_DATA */ +- 0x00000007 /* DENALI_PHY_651_DATA */ +- 0x00000000 /* DENALI_PHY_652_DATA */ +- 0x00000000 /* DENALI_PHY_653_DATA */ +- 0x04000408 /* DENALI_PHY_654_DATA */ +- 0x00000408 /* DENALI_PHY_655_DATA */ +- 0x00e4e400 /* DENALI_PHY_656_DATA */ +- 0x00000000 /* DENALI_PHY_657_DATA */ +- 0x00000000 /* DENALI_PHY_658_DATA */ +- 0x00000000 /* DENALI_PHY_659_DATA */ +- 0x00000000 /* DENALI_PHY_660_DATA */ +- 0x00000000 /* DENALI_PHY_661_DATA */ +- 0x00000000 /* DENALI_PHY_662_DATA */ +- 0x00000000 /* DENALI_PHY_663_DATA */ +- 0x00000000 /* DENALI_PHY_664_DATA */ +- 0x00000000 /* DENALI_PHY_665_DATA */ +- 0x00000000 /* DENALI_PHY_666_DATA */ +- 0x00000000 /* DENALI_PHY_667_DATA */ +- 0x00000000 /* DENALI_PHY_668_DATA */ +- 0x00000000 /* DENALI_PHY_669_DATA */ +- 0x00000000 /* DENALI_PHY_670_DATA */ +- 0x00000000 /* DENALI_PHY_671_DATA */ +- 0x00000000 /* DENALI_PHY_672_DATA */ +- 0x00200000 /* DENALI_PHY_673_DATA */ +- 0x00000000 /* DENALI_PHY_674_DATA */ +- 0x00000000 /* DENALI_PHY_675_DATA */ +- 0x00000000 /* DENALI_PHY_676_DATA */ +- 0x00000000 /* DENALI_PHY_677_DATA */ +- 0x00000000 /* DENALI_PHY_678_DATA */ +- 0x00000000 /* DENALI_PHY_679_DATA */ +- 0x02800280 /* DENALI_PHY_680_DATA */ +- 0x02800280 /* DENALI_PHY_681_DATA */ +- 0x02800280 /* DENALI_PHY_682_DATA */ +- 0x02800280 /* DENALI_PHY_683_DATA */ +- 0x00000280 /* DENALI_PHY_684_DATA */ +- 0x00000000 /* DENALI_PHY_685_DATA */ +- 0x00000000 /* DENALI_PHY_686_DATA */ +- 0x00000000 /* DENALI_PHY_687_DATA */ +- 0x00000000 /* DENALI_PHY_688_DATA */ +- 0x00000000 /* DENALI_PHY_689_DATA */ +- 0x00800080 /* DENALI_PHY_690_DATA */ +- 0x00800080 /* DENALI_PHY_691_DATA */ +- 0x00800080 /* DENALI_PHY_692_DATA */ +- 0x00800080 /* DENALI_PHY_693_DATA */ +- 0x00800080 /* DENALI_PHY_694_DATA */ +- 0x00800080 /* DENALI_PHY_695_DATA */ +- 0x00800080 /* DENALI_PHY_696_DATA */ +- 0x00800080 /* DENALI_PHY_697_DATA */ +- 0x00800080 /* DENALI_PHY_698_DATA */ +- 0x00010120 /* DENALI_PHY_699_DATA */ +- 0x000001d0 /* DENALI_PHY_700_DATA */ +- 0x01000000 /* DENALI_PHY_701_DATA */ +- 0x00000000 /* DENALI_PHY_702_DATA */ +- 0x00000002 /* DENALI_PHY_703_DATA */ +- 0x51313152 /* DENALI_PHY_704_DATA */ +- 0x80013130 /* DENALI_PHY_705_DATA */ +- 0x03000080 /* DENALI_PHY_706_DATA */ +- 0x00100002 /* DENALI_PHY_707_DATA */ +- 0x0c064208 /* DENALI_PHY_708_DATA */ +- 0x000f0c0f /* DENALI_PHY_709_DATA */ +- 0x01000140 /* DENALI_PHY_710_DATA */ +- 0x0000000c /* DENALI_PHY_711_DATA */ +- 0x00000000 /* DENALI_PHY_712_DATA */ +- 0x00000000 /* DENALI_PHY_713_DATA */ +- 0x00000000 /* DENALI_PHY_714_DATA */ +- 0x00000000 /* DENALI_PHY_715_DATA */ +- 0x00000000 /* DENALI_PHY_716_DATA */ +- 0x00000000 /* DENALI_PHY_717_DATA */ +- 0x00000000 /* DENALI_PHY_718_DATA */ +- 0x00000000 /* DENALI_PHY_719_DATA */ +- 0x00000000 /* DENALI_PHY_720_DATA */ +- 0x00000000 /* DENALI_PHY_721_DATA */ +- 0x00000000 /* DENALI_PHY_722_DATA */ +- 0x00000000 /* DENALI_PHY_723_DATA */ +- 0x00000000 /* DENALI_PHY_724_DATA */ +- 0x00000000 /* DENALI_PHY_725_DATA */ +- 0x00000000 /* DENALI_PHY_726_DATA */ +- 0x00000000 /* DENALI_PHY_727_DATA */ +- 0x00000000 /* DENALI_PHY_728_DATA */ +- 0x00000000 /* DENALI_PHY_729_DATA */ +- 0x00000000 /* DENALI_PHY_730_DATA */ +- 0x00000000 /* DENALI_PHY_731_DATA */ +- 0x00000000 /* DENALI_PHY_732_DATA */ +- 0x00000000 /* DENALI_PHY_733_DATA */ +- 0x00000000 /* DENALI_PHY_734_DATA */ +- 0x00000000 /* DENALI_PHY_735_DATA */ +- 0x00000000 /* DENALI_PHY_736_DATA */ +- 0x00000000 /* DENALI_PHY_737_DATA */ +- 0x00000000 /* DENALI_PHY_738_DATA */ +- 0x00000000 /* DENALI_PHY_739_DATA */ +- 0x00000000 /* DENALI_PHY_740_DATA */ +- 0x00000000 /* DENALI_PHY_741_DATA */ +- 0x00000000 /* DENALI_PHY_742_DATA */ +- 0x00000000 /* DENALI_PHY_743_DATA */ +- 0x00000000 /* DENALI_PHY_744_DATA */ +- 0x00000000 /* DENALI_PHY_745_DATA */ +- 0x00000000 /* DENALI_PHY_746_DATA */ +- 0x00000000 /* DENALI_PHY_747_DATA */ +- 0x00000000 /* DENALI_PHY_748_DATA */ +- 0x00000000 /* DENALI_PHY_749_DATA */ +- 0x00000000 /* DENALI_PHY_750_DATA */ +- 0x00000000 /* DENALI_PHY_751_DATA */ +- 0x00000000 /* DENALI_PHY_752_DATA */ +- 0x00000000 /* DENALI_PHY_753_DATA */ +- 0x00000000 /* DENALI_PHY_754_DATA */ +- 0x00000000 /* DENALI_PHY_755_DATA */ +- 0x00000000 /* DENALI_PHY_756_DATA */ +- 0x00000000 /* DENALI_PHY_757_DATA */ +- 0x00000000 /* DENALI_PHY_758_DATA */ +- 0x00000000 /* DENALI_PHY_759_DATA */ +- 0x00000000 /* DENALI_PHY_760_DATA */ +- 0x00000000 /* DENALI_PHY_761_DATA */ +- 0x00000000 /* DENALI_PHY_762_DATA */ +- 0x00000000 /* DENALI_PHY_763_DATA */ +- 0x00000000 /* DENALI_PHY_764_DATA */ +- 0x00000000 /* DENALI_PHY_765_DATA */ +- 0x00000000 /* DENALI_PHY_766_DATA */ +- 0x00000000 /* DENALI_PHY_767_DATA */ +- 0x10526347 /* DENALI_PHY_768_DATA */ +- 0x0004c008 /* DENALI_PHY_769_DATA */ +- 0x00000120 /* DENALI_PHY_770_DATA */ +- 0x00000000 /* DENALI_PHY_771_DATA */ +- 0x00000000 /* DENALI_PHY_772_DATA */ +- 0x00010000 /* DENALI_PHY_773_DATA */ +- 0x01DDDD90 /* DENALI_PHY_774_DATA */ +- 0x01DDDD90 /* DENALI_PHY_775_DATA */ +- 0x01030000 /* DENALI_PHY_776_DATA */ +- 0x01000000 /* DENALI_PHY_777_DATA */ +- 0x00c00000 /* DENALI_PHY_778_DATA */ +- 0x00000007 /* DENALI_PHY_779_DATA */ +- 0x00000000 /* DENALI_PHY_780_DATA */ +- 0x00000000 /* DENALI_PHY_781_DATA */ +- 0x04000408 /* DENALI_PHY_782_DATA */ +- 0x00000408 /* DENALI_PHY_783_DATA */ +- 0x00e4e400 /* DENALI_PHY_784_DATA */ +- 0x00000000 /* DENALI_PHY_785_DATA */ +- 0x00000000 /* DENALI_PHY_786_DATA */ +- 0x00000000 /* DENALI_PHY_787_DATA */ +- 0x00000000 /* DENALI_PHY_788_DATA */ +- 0x00000000 /* DENALI_PHY_789_DATA */ +- 0x00000000 /* DENALI_PHY_790_DATA */ +- 0x00000000 /* DENALI_PHY_791_DATA */ +- 0x00000000 /* DENALI_PHY_792_DATA */ +- 0x00000000 /* DENALI_PHY_793_DATA */ +- 0x00000000 /* DENALI_PHY_794_DATA */ +- 0x00000000 /* DENALI_PHY_795_DATA */ +- 0x00000000 /* DENALI_PHY_796_DATA */ +- 0x00000000 /* DENALI_PHY_797_DATA */ +- 0x00000000 /* DENALI_PHY_798_DATA */ +- 0x00000000 /* DENALI_PHY_799_DATA */ +- 0x00000000 /* DENALI_PHY_800_DATA */ +- 0x00200000 /* DENALI_PHY_801_DATA */ +- 0x00000000 /* DENALI_PHY_802_DATA */ +- 0x00000000 /* DENALI_PHY_803_DATA */ +- 0x00000000 /* DENALI_PHY_804_DATA */ +- 0x00000000 /* DENALI_PHY_805_DATA */ +- 0x00000000 /* DENALI_PHY_806_DATA */ +- 0x00000000 /* DENALI_PHY_807_DATA */ +- 0x02800280 /* DENALI_PHY_808_DATA */ +- 0x02800280 /* DENALI_PHY_809_DATA */ +- 0x02800280 /* DENALI_PHY_810_DATA */ +- 0x02800280 /* DENALI_PHY_811_DATA */ +- 0x00000280 /* DENALI_PHY_812_DATA */ +- 0x00000000 /* DENALI_PHY_813_DATA */ +- 0x00000000 /* DENALI_PHY_814_DATA */ +- 0x00000000 /* DENALI_PHY_815_DATA */ +- 0x00000000 /* DENALI_PHY_816_DATA */ +- 0x00000000 /* DENALI_PHY_817_DATA */ +- 0x00800080 /* DENALI_PHY_818_DATA */ +- 0x00800080 /* DENALI_PHY_819_DATA */ +- 0x00800080 /* DENALI_PHY_820_DATA */ +- 0x00800080 /* DENALI_PHY_821_DATA */ +- 0x00800080 /* DENALI_PHY_822_DATA */ +- 0x00800080 /* DENALI_PHY_823_DATA */ +- 0x00800080 /* DENALI_PHY_824_DATA */ +- 0x00800080 /* DENALI_PHY_825_DATA */ +- 0x00800080 /* DENALI_PHY_826_DATA */ +- 0x00010120 /* DENALI_PHY_827_DATA */ +- 0x000001d0 /* DENALI_PHY_828_DATA */ +- 0x01000000 /* DENALI_PHY_829_DATA */ +- 0x00000000 /* DENALI_PHY_830_DATA */ +- 0x00000002 /* DENALI_PHY_831_DATA */ +- 0x51313152 /* DENALI_PHY_832_DATA */ +- 0x80013130 /* DENALI_PHY_833_DATA */ +- 0x03000080 /* DENALI_PHY_834_DATA */ +- 0x00100002 /* DENALI_PHY_835_DATA */ +- 0x0c064208 /* DENALI_PHY_836_DATA */ +- 0x000f0c0f /* DENALI_PHY_837_DATA */ +- 0x01000140 /* DENALI_PHY_838_DATA */ +- 0x0000000c /* DENALI_PHY_839_DATA */ +- 0x00000000 /* DENALI_PHY_840_DATA */ +- 0x00000000 /* DENALI_PHY_841_DATA */ +- 0x00000000 /* DENALI_PHY_842_DATA */ +- 0x00000000 /* DENALI_PHY_843_DATA */ +- 0x00000000 /* DENALI_PHY_844_DATA */ +- 0x00000000 /* DENALI_PHY_845_DATA */ +- 0x00000000 /* DENALI_PHY_846_DATA */ +- 0x00000000 /* DENALI_PHY_847_DATA */ +- 0x00000000 /* DENALI_PHY_848_DATA */ +- 0x00000000 /* DENALI_PHY_849_DATA */ +- 0x00000000 /* DENALI_PHY_850_DATA */ +- 0x00000000 /* DENALI_PHY_851_DATA */ +- 0x00000000 /* DENALI_PHY_852_DATA */ +- 0x00000000 /* DENALI_PHY_853_DATA */ +- 0x00000000 /* DENALI_PHY_854_DATA */ +- 0x00000000 /* DENALI_PHY_855_DATA */ +- 0x00000000 /* DENALI_PHY_856_DATA */ +- 0x00000000 /* DENALI_PHY_857_DATA */ +- 0x00000000 /* DENALI_PHY_858_DATA */ +- 0x00000000 /* DENALI_PHY_859_DATA */ +- 0x00000000 /* DENALI_PHY_860_DATA */ +- 0x00000000 /* DENALI_PHY_861_DATA */ +- 0x00000000 /* DENALI_PHY_862_DATA */ +- 0x00000000 /* DENALI_PHY_863_DATA */ +- 0x00000000 /* DENALI_PHY_864_DATA */ +- 0x00000000 /* DENALI_PHY_865_DATA */ +- 0x00000000 /* DENALI_PHY_866_DATA */ +- 0x00000000 /* DENALI_PHY_867_DATA */ +- 0x00000000 /* DENALI_PHY_868_DATA */ +- 0x00000000 /* DENALI_PHY_869_DATA */ +- 0x00000000 /* DENALI_PHY_870_DATA */ +- 0x00000000 /* DENALI_PHY_871_DATA */ +- 0x00000000 /* DENALI_PHY_872_DATA */ +- 0x00000000 /* DENALI_PHY_873_DATA */ +- 0x00000000 /* DENALI_PHY_874_DATA */ +- 0x00000000 /* DENALI_PHY_875_DATA */ +- 0x00000000 /* DENALI_PHY_876_DATA */ +- 0x00000000 /* DENALI_PHY_877_DATA */ +- 0x00000000 /* DENALI_PHY_878_DATA */ +- 0x00000000 /* DENALI_PHY_879_DATA */ +- 0x00000000 /* DENALI_PHY_880_DATA */ +- 0x00000000 /* DENALI_PHY_881_DATA */ +- 0x00000000 /* DENALI_PHY_882_DATA */ +- 0x00000000 /* DENALI_PHY_883_DATA */ +- 0x00000000 /* DENALI_PHY_884_DATA */ +- 0x00000000 /* DENALI_PHY_885_DATA */ +- 0x00000000 /* DENALI_PHY_886_DATA */ +- 0x00000000 /* DENALI_PHY_887_DATA */ +- 0x00000000 /* DENALI_PHY_888_DATA */ +- 0x00000000 /* DENALI_PHY_889_DATA */ +- 0x00000000 /* DENALI_PHY_890_DATA */ +- 0x00000000 /* DENALI_PHY_891_DATA */ +- 0x00000000 /* DENALI_PHY_892_DATA */ +- 0x00000000 /* DENALI_PHY_893_DATA */ +- 0x00000000 /* DENALI_PHY_894_DATA */ +- 0x00000000 /* DENALI_PHY_895_DATA */ +- 0x41753260 /* DENALI_PHY_896_DATA */ +- 0x0004c008 /* DENALI_PHY_897_DATA */ +- 0x00000120 /* DENALI_PHY_898_DATA */ +- 0x00000000 /* DENALI_PHY_899_DATA */ +- 0x00000000 /* DENALI_PHY_900_DATA */ +- 0x00010000 /* DENALI_PHY_901_DATA */ +- 0x01DDDD90 /* DENALI_PHY_902_DATA */ +- 0x01DDDD90 /* DENALI_PHY_903_DATA */ +- 0x01030000 /* DENALI_PHY_904_DATA */ +- 0x01000000 /* DENALI_PHY_905_DATA */ +- 0x00c00000 /* DENALI_PHY_906_DATA */ +- 0x00000007 /* DENALI_PHY_907_DATA */ +- 0x00000000 /* DENALI_PHY_908_DATA */ +- 0x00000000 /* DENALI_PHY_909_DATA */ +- 0x04000408 /* DENALI_PHY_910_DATA */ +- 0x00000408 /* DENALI_PHY_911_DATA */ +- 0x00e4e400 /* DENALI_PHY_912_DATA */ +- 0x00000000 /* DENALI_PHY_913_DATA */ +- 0x00000000 /* DENALI_PHY_914_DATA */ +- 0x00000000 /* DENALI_PHY_915_DATA */ +- 0x00000000 /* DENALI_PHY_916_DATA */ +- 0x00000000 /* DENALI_PHY_917_DATA */ +- 0x00000000 /* DENALI_PHY_918_DATA */ +- 0x00000000 /* DENALI_PHY_919_DATA */ +- 0x00000000 /* DENALI_PHY_920_DATA */ +- 0x00000000 /* DENALI_PHY_921_DATA */ +- 0x00000000 /* DENALI_PHY_922_DATA */ +- 0x00000000 /* DENALI_PHY_923_DATA */ +- 0x00000000 /* DENALI_PHY_924_DATA */ +- 0x00000000 /* DENALI_PHY_925_DATA */ +- 0x00000000 /* DENALI_PHY_926_DATA */ +- 0x00000000 /* DENALI_PHY_927_DATA */ +- 0x00000000 /* DENALI_PHY_928_DATA */ +- 0x00200000 /* DENALI_PHY_929_DATA */ +- 0x00000000 /* DENALI_PHY_930_DATA */ +- 0x00000000 /* DENALI_PHY_931_DATA */ +- 0x00000000 /* DENALI_PHY_932_DATA */ +- 0x00000000 /* DENALI_PHY_933_DATA */ +- 0x00000000 /* DENALI_PHY_934_DATA */ +- 0x00000000 /* DENALI_PHY_935_DATA */ +- 0x02800280 /* DENALI_PHY_936_DATA */ +- 0x02800280 /* DENALI_PHY_937_DATA */ +- 0x02800280 /* DENALI_PHY_938_DATA */ +- 0x02800280 /* DENALI_PHY_939_DATA */ +- 0x00000280 /* DENALI_PHY_940_DATA */ +- 0x00000000 /* DENALI_PHY_941_DATA */ +- 0x00000000 /* DENALI_PHY_942_DATA */ +- 0x00000000 /* DENALI_PHY_943_DATA */ +- 0x00000000 /* DENALI_PHY_944_DATA */ +- 0x00000000 /* DENALI_PHY_945_DATA */ +- 0x00800080 /* DENALI_PHY_946_DATA */ +- 0x00800080 /* DENALI_PHY_947_DATA */ +- 0x00800080 /* DENALI_PHY_948_DATA */ +- 0x00800080 /* DENALI_PHY_949_DATA */ +- 0x00800080 /* DENALI_PHY_950_DATA */ +- 0x00800080 /* DENALI_PHY_951_DATA */ +- 0x00800080 /* DENALI_PHY_952_DATA */ +- 0x00800080 /* DENALI_PHY_953_DATA */ +- 0x00800080 /* DENALI_PHY_954_DATA */ +- 0x00010120 /* DENALI_PHY_955_DATA */ +- 0x000001d0 /* DENALI_PHY_956_DATA */ +- 0x01000000 /* DENALI_PHY_957_DATA */ +- 0x00000000 /* DENALI_PHY_958_DATA */ +- 0x00000002 /* DENALI_PHY_959_DATA */ +- 0x51313152 /* DENALI_PHY_960_DATA */ +- 0x80013130 /* DENALI_PHY_961_DATA */ +- 0x03000080 /* DENALI_PHY_962_DATA */ +- 0x00100002 /* DENALI_PHY_963_DATA */ +- 0x0c064208 /* DENALI_PHY_964_DATA */ +- 0x000f0c0f /* DENALI_PHY_965_DATA */ +- 0x01000140 /* DENALI_PHY_966_DATA */ +- 0x0000000c /* DENALI_PHY_967_DATA */ +- 0x00000000 /* DENALI_PHY_968_DATA */ +- 0x00000000 /* DENALI_PHY_969_DATA */ +- 0x00000000 /* DENALI_PHY_970_DATA */ +- 0x00000000 /* DENALI_PHY_971_DATA */ +- 0x00000000 /* DENALI_PHY_972_DATA */ +- 0x00000000 /* DENALI_PHY_973_DATA */ +- 0x00000000 /* DENALI_PHY_974_DATA */ +- 0x00000000 /* DENALI_PHY_975_DATA */ +- 0x00000000 /* DENALI_PHY_976_DATA */ +- 0x00000000 /* DENALI_PHY_977_DATA */ +- 0x00000000 /* DENALI_PHY_978_DATA */ +- 0x00000000 /* DENALI_PHY_979_DATA */ +- 0x00000000 /* DENALI_PHY_980_DATA */ +- 0x00000000 /* DENALI_PHY_981_DATA */ +- 0x00000000 /* DENALI_PHY_982_DATA */ +- 0x00000000 /* DENALI_PHY_983_DATA */ +- 0x00000000 /* DENALI_PHY_984_DATA */ +- 0x00000000 /* DENALI_PHY_985_DATA */ +- 0x00000000 /* DENALI_PHY_986_DATA */ +- 0x00000000 /* DENALI_PHY_987_DATA */ +- 0x00000000 /* DENALI_PHY_988_DATA */ +- 0x00000000 /* DENALI_PHY_989_DATA */ +- 0x00000000 /* DENALI_PHY_990_DATA */ +- 0x00000000 /* DENALI_PHY_991_DATA */ +- 0x00000000 /* DENALI_PHY_992_DATA */ +- 0x00000000 /* DENALI_PHY_993_DATA */ +- 0x00000000 /* DENALI_PHY_994_DATA */ +- 0x00000000 /* DENALI_PHY_995_DATA */ +- 0x00000000 /* DENALI_PHY_996_DATA */ +- 0x00000000 /* DENALI_PHY_997_DATA */ +- 0x00000000 /* DENALI_PHY_998_DATA */ +- 0x00000000 /* DENALI_PHY_999_DATA */ +- 0x00000000 /* DENALI_PHY_1000_DATA */ +- 0x00000000 /* DENALI_PHY_1001_DATA */ +- 0x00000000 /* DENALI_PHY_1002_DATA */ +- 0x00000000 /* DENALI_PHY_1003_DATA */ +- 0x00000000 /* DENALI_PHY_1004_DATA */ +- 0x00000000 /* DENALI_PHY_1005_DATA */ +- 0x00000000 /* DENALI_PHY_1006_DATA */ +- 0x00000000 /* DENALI_PHY_1007_DATA */ +- 0x00000000 /* DENALI_PHY_1008_DATA */ +- 0x00000000 /* DENALI_PHY_1009_DATA */ +- 0x00000000 /* DENALI_PHY_1010_DATA */ +- 0x00000000 /* DENALI_PHY_1011_DATA */ +- 0x00000000 /* DENALI_PHY_1012_DATA */ +- 0x00000000 /* DENALI_PHY_1013_DATA */ +- 0x00000000 /* DENALI_PHY_1014_DATA */ +- 0x00000000 /* DENALI_PHY_1015_DATA */ +- 0x00000000 /* DENALI_PHY_1016_DATA */ +- 0x00000000 /* DENALI_PHY_1017_DATA */ +- 0x00000000 /* DENALI_PHY_1018_DATA */ +- 0x00000000 /* DENALI_PHY_1019_DATA */ +- 0x00000000 /* DENALI_PHY_1020_DATA */ +- 0x00000000 /* DENALI_PHY_1021_DATA */ +- 0x00000000 /* DENALI_PHY_1022_DATA */ +- 0x00000000 /* DENALI_PHY_1023_DATA */ +- 0x76543210 /* DENALI_PHY_1024_DATA */ +- 0x0004c008 /* DENALI_PHY_1025_DATA */ +- 0x00000120 /* DENALI_PHY_1026_DATA */ +- 0x00000000 /* DENALI_PHY_1027_DATA */ +- 0x00000000 /* DENALI_PHY_1028_DATA */ +- 0x00010000 /* DENALI_PHY_1029_DATA */ +- 0x01DDDD90 /* DENALI_PHY_1030_DATA */ +- 0x01DDDD90 /* DENALI_PHY_1031_DATA */ +- 0x01030000 /* DENALI_PHY_1032_DATA */ +- 0x01000000 /* DENALI_PHY_1033_DATA */ +- 0x00c00000 /* DENALI_PHY_1034_DATA */ +- 0x00000007 /* DENALI_PHY_1035_DATA */ +- 0x00000000 /* DENALI_PHY_1036_DATA */ +- 0x00000000 /* DENALI_PHY_1037_DATA */ +- 0x04000408 /* DENALI_PHY_1038_DATA */ +- 0x00000408 /* DENALI_PHY_1039_DATA */ +- 0x00e4e400 /* DENALI_PHY_1040_DATA */ +- 0x00000000 /* DENALI_PHY_1041_DATA */ +- 0x00000000 /* DENALI_PHY_1042_DATA */ +- 0x00000000 /* DENALI_PHY_1043_DATA */ +- 0x00000000 /* DENALI_PHY_1044_DATA */ +- 0x00000000 /* DENALI_PHY_1045_DATA */ +- 0x00000000 /* DENALI_PHY_1046_DATA */ +- 0x00000000 /* DENALI_PHY_1047_DATA */ +- 0x00000000 /* DENALI_PHY_1048_DATA */ +- 0x00000000 /* DENALI_PHY_1049_DATA */ +- 0x00000000 /* DENALI_PHY_1050_DATA */ +- 0x00000000 /* DENALI_PHY_1051_DATA */ +- 0x00000000 /* DENALI_PHY_1052_DATA */ +- 0x00000000 /* DENALI_PHY_1053_DATA */ +- 0x00000000 /* DENALI_PHY_1054_DATA */ +- 0x00000000 /* DENALI_PHY_1055_DATA */ +- 0x00000000 /* DENALI_PHY_1056_DATA */ +- 0x00200000 /* DENALI_PHY_1057_DATA */ +- 0x00000000 /* DENALI_PHY_1058_DATA */ +- 0x00000000 /* DENALI_PHY_1059_DATA */ +- 0x00000000 /* DENALI_PHY_1060_DATA */ +- 0x00000000 /* DENALI_PHY_1061_DATA */ +- 0x00000000 /* DENALI_PHY_1062_DATA */ +- 0x00000000 /* DENALI_PHY_1063_DATA */ +- 0x02800280 /* DENALI_PHY_1064_DATA */ +- 0x02800280 /* DENALI_PHY_1065_DATA */ +- 0x02800280 /* DENALI_PHY_1066_DATA */ +- 0x02800280 /* DENALI_PHY_1067_DATA */ +- 0x00000280 /* DENALI_PHY_1068_DATA */ +- 0x00000000 /* DENALI_PHY_1069_DATA */ +- 0x00000000 /* DENALI_PHY_1070_DATA */ +- 0x00000000 /* DENALI_PHY_1071_DATA */ +- 0x00000000 /* DENALI_PHY_1072_DATA */ +- 0x00000000 /* DENALI_PHY_1073_DATA */ +- 0x00800080 /* DENALI_PHY_1074_DATA */ +- 0x00800080 /* DENALI_PHY_1075_DATA */ +- 0x00800080 /* DENALI_PHY_1076_DATA */ +- 0x00800080 /* DENALI_PHY_1077_DATA */ +- 0x00800080 /* DENALI_PHY_1078_DATA */ +- 0x00800080 /* DENALI_PHY_1079_DATA */ +- 0x00800080 /* DENALI_PHY_1080_DATA */ +- 0x00800080 /* DENALI_PHY_1081_DATA */ +- 0x00800080 /* DENALI_PHY_1082_DATA */ +- 0x00010120 /* DENALI_PHY_1083_DATA */ +- 0x000001d0 /* DENALI_PHY_1084_DATA */ +- 0x01000000 /* DENALI_PHY_1085_DATA */ +- 0x00000000 /* DENALI_PHY_1086_DATA */ +- 0x00000002 /* DENALI_PHY_1087_DATA */ +- 0x51313152 /* DENALI_PHY_1088_DATA */ +- 0x80013130 /* DENALI_PHY_1089_DATA */ +- 0x03000080 /* DENALI_PHY_1090_DATA */ +- 0x00100002 /* DENALI_PHY_1091_DATA */ +- 0x0c064208 /* DENALI_PHY_1092_DATA */ +- 0x000f0c0f /* DENALI_PHY_1093_DATA */ +- 0x01000140 /* DENALI_PHY_1094_DATA */ +- 0x0000000c /* DENALI_PHY_1095_DATA */ +- 0x00000000 /* DENALI_PHY_1096_DATA */ +- 0x00000000 /* DENALI_PHY_1097_DATA */ +- 0x00000000 /* DENALI_PHY_1098_DATA */ +- 0x00000000 /* DENALI_PHY_1099_DATA */ +- 0x00000000 /* DENALI_PHY_1100_DATA */ +- 0x00000000 /* DENALI_PHY_1101_DATA */ +- 0x00000000 /* DENALI_PHY_1102_DATA */ +- 0x00000000 /* DENALI_PHY_1103_DATA */ +- 0x00000000 /* DENALI_PHY_1104_DATA */ +- 0x00000000 /* DENALI_PHY_1105_DATA */ +- 0x00000000 /* DENALI_PHY_1106_DATA */ +- 0x00000000 /* DENALI_PHY_1107_DATA */ +- 0x00000000 /* DENALI_PHY_1108_DATA */ +- 0x00000000 /* DENALI_PHY_1109_DATA */ +- 0x00000000 /* DENALI_PHY_1110_DATA */ +- 0x00000000 /* DENALI_PHY_1111_DATA */ +- 0x00000000 /* DENALI_PHY_1112_DATA */ +- 0x00000000 /* DENALI_PHY_1113_DATA */ +- 0x00000000 /* DENALI_PHY_1114_DATA */ +- 0x00000000 /* DENALI_PHY_1115_DATA */ +- 0x00000000 /* DENALI_PHY_1116_DATA */ +- 0x00000000 /* DENALI_PHY_1117_DATA */ +- 0x00000000 /* DENALI_PHY_1118_DATA */ +- 0x00000000 /* DENALI_PHY_1119_DATA */ +- 0x00000000 /* DENALI_PHY_1120_DATA */ +- 0x00000000 /* DENALI_PHY_1121_DATA */ +- 0x00000000 /* DENALI_PHY_1122_DATA */ +- 0x00000000 /* DENALI_PHY_1123_DATA */ +- 0x00000000 /* DENALI_PHY_1124_DATA */ +- 0x00000000 /* DENALI_PHY_1125_DATA */ +- 0x00000000 /* DENALI_PHY_1126_DATA */ +- 0x00000000 /* DENALI_PHY_1127_DATA */ +- 0x00000000 /* DENALI_PHY_1128_DATA */ +- 0x00000000 /* DENALI_PHY_1129_DATA */ +- 0x00000000 /* DENALI_PHY_1130_DATA */ +- 0x00000000 /* DENALI_PHY_1131_DATA */ +- 0x00000000 /* DENALI_PHY_1132_DATA */ +- 0x00000000 /* DENALI_PHY_1133_DATA */ +- 0x00000000 /* DENALI_PHY_1134_DATA */ +- 0x00000000 /* DENALI_PHY_1135_DATA */ +- 0x00000000 /* DENALI_PHY_1136_DATA */ +- 0x00000000 /* DENALI_PHY_1137_DATA */ +- 0x00000000 /* DENALI_PHY_1138_DATA */ +- 0x00000000 /* DENALI_PHY_1139_DATA */ +- 0x00000000 /* DENALI_PHY_1140_DATA */ +- 0x00000000 /* DENALI_PHY_1141_DATA */ +- 0x00000000 /* DENALI_PHY_1142_DATA */ +- 0x00000000 /* DENALI_PHY_1143_DATA */ +- 0x00000000 /* DENALI_PHY_1144_DATA */ +- 0x00000000 /* DENALI_PHY_1145_DATA */ +- 0x00000000 /* DENALI_PHY_1146_DATA */ +- 0x00000000 /* DENALI_PHY_1147_DATA */ +- 0x00000000 /* DENALI_PHY_1148_DATA */ +- 0x00000000 /* DENALI_PHY_1149_DATA */ +- 0x00000000 /* DENALI_PHY_1150_DATA */ +- 0x00000000 /* DENALI_PHY_1151_DATA */ +- 0x00000000 /* DENALI_PHY_1152_DATA */ +- 0x00000000 /* DENALI_PHY_1153_DATA */ +- 0x00050000 /* DENALI_PHY_1154_DATA */ +- 0x00000000 /* DENALI_PHY_1155_DATA */ +- 0x00000000 /* DENALI_PHY_1156_DATA */ +- 0x00000000 /* DENALI_PHY_1157_DATA */ +- 0x00000100 /* DENALI_PHY_1158_DATA */ +- 0x00000000 /* DENALI_PHY_1159_DATA */ +- 0x00000000 /* DENALI_PHY_1160_DATA */ +- 0x00506401 /* DENALI_PHY_1161_DATA */ +- 0x01221102 /* DENALI_PHY_1162_DATA */ +- 0x00000122 /* DENALI_PHY_1163_DATA */ +- 0x00000000 /* DENALI_PHY_1164_DATA */ +- 0x000B1F00 /* DENALI_PHY_1165_DATA */ +- 0x0B1F0B1F /* DENALI_PHY_1166_DATA */ +- 0x0B1F0B1F /* DENALI_PHY_1167_DATA */ +- 0x0B1F0B1F /* DENALI_PHY_1168_DATA */ +- 0x0B1F0B1F /* DENALI_PHY_1169_DATA */ +- 0x00000B00 /* DENALI_PHY_1170_DATA */ +- 0x42080010 /* DENALI_PHY_1171_DATA */ +- 0x01000100 /* DENALI_PHY_1172_DATA */ +- 0x01000100 /* DENALI_PHY_1173_DATA */ +- 0x01000100 /* DENALI_PHY_1174_DATA */ +- 0x01000100 /* DENALI_PHY_1175_DATA */ +- 0x00000000 /* DENALI_PHY_1176_DATA */ +- 0x00000000 /* DENALI_PHY_1177_DATA */ +- 0x00000000 /* DENALI_PHY_1178_DATA */ +- 0x00000000 /* DENALI_PHY_1179_DATA */ +- 0x00000000 /* DENALI_PHY_1180_DATA */ +- 0x00000903 /* DENALI_PHY_1181_DATA */ +- 0x223FFF00 /* DENALI_PHY_1182_DATA */ +- 0x000008FF /* DENALI_PHY_1183_DATA */ +- 0x0000057F /* DENALI_PHY_1184_DATA */ +- 0x0000057F /* DENALI_PHY_1185_DATA */ +- 0x00037FFF /* DENALI_PHY_1186_DATA */ +- 0x00037FFF /* DENALI_PHY_1187_DATA */ +- 0x00004410 /* DENALI_PHY_1188_DATA */ +- 0x00004410 /* DENALI_PHY_1189_DATA */ +- 0x00004410 /* DENALI_PHY_1190_DATA */ +- 0x00004410 /* DENALI_PHY_1191_DATA */ +- 0x00004410 /* DENALI_PHY_1192_DATA */ +- 0x00000111 /* DENALI_PHY_1193_DATA */ +- 0x00000111 /* DENALI_PHY_1194_DATA */ +- 0x00000000 /* DENALI_PHY_1195_DATA */ +- 0x00000000 /* DENALI_PHY_1196_DATA */ +- 0x00000000 /* DENALI_PHY_1197_DATA */ +- 0x04000000 /* DENALI_PHY_1198_DATA */ +- 0x00000000 /* DENALI_PHY_1199_DATA */ +- 0x00000000 /* DENALI_PHY_1200_DATA */ +- 0x00000108 /* DENALI_PHY_1201_DATA */ +- 0x00000000 /* DENALI_PHY_1202_DATA */ +- 0x00000000 /* DENALI_PHY_1203_DATA */ +- 0x00000000 /* DENALI_PHY_1204_DATA */ +- 0x00000001 /* DENALI_PHY_1205_DATA */ +- 0x00000000 /* DENALI_PHY_1206_DATA */ +- 0x00000000 /* DENALI_PHY_1207_DATA */ +- 0x00000000 /* DENALI_PHY_1208_DATA */ +- 0x00000000 /* DENALI_PHY_1209_DATA */ +- 0x00000000 /* DENALI_PHY_1210_DATA */ +- 0x00000000 /* DENALI_PHY_1211_DATA */ +- 0x00020100 /* DENALI_PHY_1212_DATA */ +- 0x00000000 /* DENALI_PHY_1213_DATA */ +- 0x00000000 /* DENALI_PHY_1214_DATA */ ++ 0x00000a00 /*DENALI_CTL_00_DATA*/ ++ 0x00000000 /*DENALI_CTL_01_DATA*/ ++ 0x00000000 /*DENALI_CTL_02_DATA*/ ++ 0x00000000 /*DENALI_CTL_03_DATA*/ ++ 0x00000000 /*DENALI_CTL_04_DATA*/ ++ 0x00000000 /*DENALI_CTL_05_DATA*/ ++ 0x0000000a /*DENALI_CTL_06_DATA*/ ++ 0x0002d362 /*DENALI_CTL_07_DATA*/ ++ 0x00071073 /*DENALI_CTL_08_DATA*/ ++ 0x0a1c0255 /*DENALI_CTL_09_DATA*/ ++ 0x1c1c0400 /*DENALI_CTL_10_DATA*/ ++ 0x0404c90b /*DENALI_CTL_11_DATA*/ ++ 0x2b050405 /*DENALI_CTL_12_DATA*/ ++ 0x0d0c081e /*DENALI_CTL_13_DATA*/ ++ 0x08090914 /*DENALI_CTL_14_DATA*/ ++ 0x00fde718 /*DENALI_CTL_15_DATA*/ ++ 0x00180a05 /*DENALI_CTL_16_DATA*/ ++ 0x008b130d /*DENALI_CTL_17_DATA*/ ++ 0x01000118 /*DENALI_CTL_18_DATA*/ ++ 0x0d032001 /*DENALI_CTL_19_DATA*/ ++ 0x00000000 /*DENALI_CTL_20_DATA*/ ++ 0x00000101 /*DENALI_CTL_21_DATA*/ ++ 0x00000000 /*DENALI_CTL_22_DATA*/ ++ 0x0a000000 /*DENALI_CTL_23_DATA*/ ++ 0x00000000 /*DENALI_CTL_24_DATA*/ ++ 0x01450100 /*DENALI_CTL_25_DATA*/ ++ 0x00001c36 /*DENALI_CTL_26_DATA*/ ++ 0x00000005 /*DENALI_CTL_27_DATA*/ ++ 0x00170006 /*DENALI_CTL_28_DATA*/ ++ 0x014e0400 /*DENALI_CTL_29_DATA*/ ++ 0x03010000 /*DENALI_CTL_30_DATA*/ ++ 0x000a0e00 /*DENALI_CTL_31_DATA*/ ++ 0x04030200 /*DENALI_CTL_32_DATA*/ ++ 0x0000031f /*DENALI_CTL_33_DATA*/ ++ 0x00070004 /*DENALI_CTL_34_DATA*/ ++ 0x00000000 /*DENALI_CTL_35_DATA*/ ++ 0x00000000 /*DENALI_CTL_36_DATA*/ ++ 0x00000000 /*DENALI_CTL_37_DATA*/ ++ 0x00000000 /*DENALI_CTL_38_DATA*/ ++ 0x00000000 /*DENALI_CTL_39_DATA*/ ++ 0x00000000 /*DENALI_CTL_40_DATA*/ ++ 0x00000000 /*DENALI_CTL_41_DATA*/ ++ 0x00000000 /*DENALI_CTL_42_DATA*/ ++ 0x00000000 /*DENALI_CTL_43_DATA*/ ++ 0x00000000 /*DENALI_CTL_44_DATA*/ ++ 0x00000000 /*DENALI_CTL_45_DATA*/ ++ 0x00000000 /*DENALI_CTL_46_DATA*/ ++ 0x00000000 /*DENALI_CTL_47_DATA*/ ++ 0x00000000 /*DENALI_CTL_48_DATA*/ ++ 0x00000000 /*DENALI_CTL_49_DATA*/ ++ 0x00000000 /*DENALI_CTL_50_DATA*/ ++ 0x00000000 /*DENALI_CTL_51_DATA*/ ++ 0x00000000 /*DENALI_CTL_52_DATA*/ ++ 0x00000000 /*DENALI_CTL_53_DATA*/ ++ 0x00000000 /*DENALI_CTL_54_DATA*/ ++ 0x00000000 /*DENALI_CTL_55_DATA*/ ++ 0x00000000 /*DENALI_CTL_56_DATA*/ ++ 0x00000000 /*DENALI_CTL_57_DATA*/ ++ 0x00000000 /*DENALI_CTL_58_DATA*/ ++ 0x00000000 /*DENALI_CTL_59_DATA*/ ++ 0x00000424 /*DENALI_CTL_60_DATA*/ ++ 0x00000201 /*DENALI_CTL_61_DATA*/ ++ 0x00001008 /*DENALI_CTL_62_DATA*/ ++ 0x00000000 /*DENALI_CTL_63_DATA*/ ++ 0x00000200 /*DENALI_CTL_64_DATA*/ ++ 0x00000800 /*DENALI_CTL_65_DATA*/ ++ 0x00000481 /*DENALI_CTL_66_DATA*/ ++ 0x00000400 /*DENALI_CTL_67_DATA*/ ++ 0x00000424 /*DENALI_CTL_68_DATA*/ ++ 0x00000201 /*DENALI_CTL_69_DATA*/ ++ 0x00001008 /*DENALI_CTL_70_DATA*/ ++ 0x00000000 /*DENALI_CTL_71_DATA*/ ++ 0x00000200 /*DENALI_CTL_72_DATA*/ ++ 0x00000800 /*DENALI_CTL_73_DATA*/ ++ 0x00000481 /*DENALI_CTL_74_DATA*/ ++ 0x00000400 /*DENALI_CTL_75_DATA*/ ++ 0x01010000 /*DENALI_CTL_76_DATA*/ ++ 0x00000000 /*DENALI_CTL_77_DATA*/ ++ 0x00000000 /*DENALI_CTL_78_DATA*/ ++ 0x00000000 /*DENALI_CTL_79_DATA*/ ++ 0x00000000 /*DENALI_CTL_80_DATA*/ ++ 0x00000000 /*DENALI_CTL_81_DATA*/ ++ 0x00000000 /*DENALI_CTL_82_DATA*/ ++ 0x00000000 /*DENALI_CTL_83_DATA*/ ++ 0x00000000 /*DENALI_CTL_84_DATA*/ ++ 0x00000000 /*DENALI_CTL_85_DATA*/ ++ 0x00000000 /*DENALI_CTL_86_DATA*/ ++ 0x00000000 /*DENALI_CTL_87_DATA*/ ++ 0x00000000 /*DENALI_CTL_88_DATA*/ ++ 0x00000000 /*DENALI_CTL_89_DATA*/ ++ 0x00000000 /*DENALI_CTL_90_DATA*/ ++ 0x00000000 /*DENALI_CTL_91_DATA*/ ++ 0x00000000 /*DENALI_CTL_92_DATA*/ ++ 0x00000000 /*DENALI_CTL_93_DATA*/ ++ 0x00000000 /*DENALI_CTL_94_DATA*/ ++ 0x00000000 /*DENALI_CTL_95_DATA*/ ++ 0x00000000 /*DENALI_CTL_96_DATA*/ ++ 0x00000000 /*DENALI_CTL_97_DATA*/ ++ 0x00000000 /*DENALI_CTL_98_DATA*/ ++ 0x00000000 /*DENALI_CTL_99_DATA*/ ++ 0x00000000 /*DENALI_CTL_100_DATA*/ ++ 0x00000000 /*DENALI_CTL_101_DATA*/ ++ 0x00000000 /*DENALI_CTL_102_DATA*/ ++ 0x00000000 /*DENALI_CTL_103_DATA*/ ++ 0x00000000 /*DENALI_CTL_104_DATA*/ ++ 0x00000003 /*DENALI_CTL_105_DATA*/ ++ 0x00000000 /*DENALI_CTL_106_DATA*/ ++ 0x00000000 /*DENALI_CTL_107_DATA*/ ++ 0x00000000 /*DENALI_CTL_108_DATA*/ ++ 0x00000000 /*DENALI_CTL_109_DATA*/ ++ 0x01000000 /*DENALI_CTL_110_DATA*/ ++ 0x00040000 /*DENALI_CTL_111_DATA*/ ++ 0x00800200 /*DENALI_CTL_112_DATA*/ ++ 0x00000200 /*DENALI_CTL_113_DATA*/ ++ 0x00000040 /*DENALI_CTL_114_DATA*/ ++ 0x01000100 /*DENALI_CTL_115_DATA*/ ++ 0x0a000002 /*DENALI_CTL_116_DATA*/ ++ 0x0101ffff /*DENALI_CTL_117_DATA*/ ++ 0x01010101 /*DENALI_CTL_118_DATA*/ ++ 0x01010101 /*DENALI_CTL_119_DATA*/ ++ 0x0000010b /*DENALI_CTL_120_DATA*/ ++ 0x00000c03 /*DENALI_CTL_121_DATA*/ ++ 0x00000000 /*DENALI_CTL_122_DATA*/ ++ 0x00000000 /*DENALI_CTL_123_DATA*/ ++ 0x00000000 /*DENALI_CTL_124_DATA*/ ++ 0x00000000 /*DENALI_CTL_125_DATA*/ ++ 0x00030300 /*DENALI_CTL_126_DATA*/ ++ 0x00000000 /*DENALI_CTL_127_DATA*/ ++ 0x00010101 /*DENALI_CTL_128_DATA*/ ++ 0x00000000 /*DENALI_CTL_129_DATA*/ ++ 0x00000000 /*DENALI_CTL_130_DATA*/ ++ 0x00000000 /*DENALI_CTL_131_DATA*/ ++ 0x00000000 /*DENALI_CTL_132_DATA*/ ++ 0x00000000 /*DENALI_CTL_133_DATA*/ ++ 0x00000000 /*DENALI_CTL_134_DATA*/ ++ 0x00000000 /*DENALI_CTL_135_DATA*/ ++ 0x00000000 /*DENALI_CTL_136_DATA*/ ++ 0x00000000 /*DENALI_CTL_137_DATA*/ ++ 0x00000000 /*DENALI_CTL_138_DATA*/ ++ 0x00000000 /*DENALI_CTL_139_DATA*/ ++ 0x00000000 /*DENALI_CTL_140_DATA*/ ++ 0x00000000 /*DENALI_CTL_141_DATA*/ ++ 0x00000000 /*DENALI_CTL_142_DATA*/ ++ 0x00000000 /*DENALI_CTL_143_DATA*/ ++ 0x00000000 /*DENALI_CTL_144_DATA*/ ++ 0x00000000 /*DENALI_CTL_145_DATA*/ ++ 0x00000000 /*DENALI_CTL_146_DATA*/ ++ 0x00000000 /*DENALI_CTL_147_DATA*/ ++ 0x00000000 /*DENALI_CTL_148_DATA*/ ++ 0x00000000 /*DENALI_CTL_149_DATA*/ ++ 0x00000000 /*DENALI_CTL_150_DATA*/ ++ 0x00000000 /*DENALI_CTL_151_DATA*/ ++ 0x00000000 /*DENALI_CTL_152_DATA*/ ++ 0x00000000 /*DENALI_CTL_153_DATA*/ ++ 0x00000000 /*DENALI_CTL_154_DATA*/ ++ 0x00000000 /*DENALI_CTL_155_DATA*/ ++ 0x00000000 /*DENALI_CTL_156_DATA*/ ++ 0x00000000 /*DENALI_CTL_157_DATA*/ ++ 0x00000000 /*DENALI_CTL_158_DATA*/ ++ 0x00000000 /*DENALI_CTL_159_DATA*/ ++ 0x00000000 /*DENALI_CTL_160_DATA*/ ++ 0x02010102 /*DENALI_CTL_161_DATA*/ ++ 0x0108070d /*DENALI_CTL_162_DATA*/ ++ 0x05050300 /*DENALI_CTL_163_DATA*/ ++ 0x04000503 /*DENALI_CTL_164_DATA*/ ++ 0x00000000 /*DENALI_CTL_165_DATA*/ ++ 0x00000000 /*DENALI_CTL_166_DATA*/ ++ 0x00000000 /*DENALI_CTL_167_DATA*/ ++ 0x00000000 /*DENALI_CTL_168_DATA*/ ++ 0x280d0000 /*DENALI_CTL_169_DATA*/ ++ 0x01000000 /*DENALI_CTL_170_DATA*/ ++ 0x00000000 /*DENALI_CTL_171_DATA*/ ++ 0x00030001 /*DENALI_CTL_172_DATA*/ ++ 0x00000000 /*DENALI_CTL_173_DATA*/ ++ 0x00000000 /*DENALI_CTL_174_DATA*/ ++ 0x00000000 /*DENALI_CTL_175_DATA*/ ++ 0x00000000 /*DENALI_CTL_176_DATA*/ ++ 0x00000000 /*DENALI_CTL_177_DATA*/ ++ 0x00000000 /*DENALI_CTL_178_DATA*/ ++ 0x00000000 /*DENALI_CTL_179_DATA*/ ++ 0x00000000 /*DENALI_CTL_180_DATA*/ ++ 0x01000000 /*DENALI_CTL_181_DATA*/ ++ 0x00000001 /*DENALI_CTL_182_DATA*/ ++ 0x00000100 /*DENALI_CTL_183_DATA*/ ++ 0x00010303 /*DENALI_CTL_184_DATA*/ ++ 0x67676701 /*DENALI_CTL_185_DATA*/ ++ 0x67676767 /*DENALI_CTL_186_DATA*/ ++ 0x67676767 /*DENALI_CTL_187_DATA*/ ++ 0x67676767 /*DENALI_CTL_188_DATA*/ ++ 0x67676767 /*DENALI_CTL_189_DATA*/ ++ 0x67676767 /*DENALI_CTL_190_DATA*/ ++ 0x67676767 /*DENALI_CTL_191_DATA*/ ++ 0x67676767 /*DENALI_CTL_192_DATA*/ ++ 0x67676767 /*DENALI_CTL_193_DATA*/ ++ 0x01000067 /*DENALI_CTL_194_DATA*/ ++ 0x00000001 /*DENALI_CTL_195_DATA*/ ++ 0x00000101 /*DENALI_CTL_196_DATA*/ ++ 0x00000000 /*DENALI_CTL_197_DATA*/ ++ 0x00000000 /*DENALI_CTL_198_DATA*/ ++ 0x00000000 /*DENALI_CTL_199_DATA*/ ++ 0x00000000 /*DENALI_CTL_200_DATA*/ ++ 0x00000000 /*DENALI_CTL_201_DATA*/ ++ 0x00000000 /*DENALI_CTL_202_DATA*/ ++ 0x00000000 /*DENALI_CTL_203_DATA*/ ++ 0x00000000 /*DENALI_CTL_204_DATA*/ ++ 0x00000000 /*DENALI_CTL_205_DATA*/ ++ 0x00000000 /*DENALI_CTL_206_DATA*/ ++ 0x00000000 /*DENALI_CTL_207_DATA*/ ++ 0x00000001 /*DENALI_CTL_208_DATA*/ ++ 0x00000000 /*DENALI_CTL_209_DATA*/ ++ 0x007fffff /*DENALI_CTL_210_DATA*/ ++ 0x00000000 /*DENALI_CTL_211_DATA*/ ++ 0x007fffff /*DENALI_CTL_212_DATA*/ ++ 0x00000000 /*DENALI_CTL_213_DATA*/ ++ 0x007fffff /*DENALI_CTL_214_DATA*/ ++ 0x00000000 /*DENALI_CTL_215_DATA*/ ++ 0x007fffff /*DENALI_CTL_216_DATA*/ ++ 0x00000000 /*DENALI_CTL_217_DATA*/ ++ 0x007fffff /*DENALI_CTL_218_DATA*/ ++ 0x00000000 /*DENALI_CTL_219_DATA*/ ++ 0x007fffff /*DENALI_CTL_220_DATA*/ ++ 0x00000000 /*DENALI_CTL_221_DATA*/ ++ 0x007fffff /*DENALI_CTL_222_DATA*/ ++ 0x00000000 /*DENALI_CTL_223_DATA*/ ++ 0x037fffff /*DENALI_CTL_224_DATA*/ ++ 0xffffffff /*DENALI_CTL_225_DATA*/ ++ 0x000f000f /*DENALI_CTL_226_DATA*/ ++ 0x00ffff03 /*DENALI_CTL_227_DATA*/ ++ 0x000fffff /*DENALI_CTL_228_DATA*/ ++ 0x0003000f /*DENALI_CTL_229_DATA*/ ++ 0xffffffff /*DENALI_CTL_230_DATA*/ ++ 0x000f000f /*DENALI_CTL_231_DATA*/ ++ 0x00ffff03 /*DENALI_CTL_232_DATA*/ ++ 0x000fffff /*DENALI_CTL_233_DATA*/ ++ 0x0003000f /*DENALI_CTL_234_DATA*/ ++ 0xffffffff /*DENALI_CTL_235_DATA*/ ++ 0x000f000f /*DENALI_CTL_236_DATA*/ ++ 0x00ffff03 /*DENALI_CTL_237_DATA*/ ++ 0x000fffff /*DENALI_CTL_238_DATA*/ ++ 0x0003000f /*DENALI_CTL_239_DATA*/ ++ 0xffffffff /*DENALI_CTL_240_DATA*/ ++ 0x000f000f /*DENALI_CTL_241_DATA*/ ++ 0x00ffff03 /*DENALI_CTL_242_DATA*/ ++ 0x000fffff /*DENALI_CTL_243_DATA*/ ++ 0x6407000f /*DENALI_CTL_244_DATA*/ ++ 0x01640001 /*DENALI_CTL_245_DATA*/ ++ 0x00000000 /*DENALI_CTL_246_DATA*/ ++ 0x00000000 /*DENALI_CTL_247_DATA*/ ++ 0x00001800 /*DENALI_CTL_248_DATA*/ ++ 0x00386c05 /*DENALI_CTL_249_DATA*/ ++ 0x02000200 /*DENALI_CTL_250_DATA*/ ++ 0x02000200 /*DENALI_CTL_251_DATA*/ ++ 0x0000386c /*DENALI_CTL_252_DATA*/ ++ 0x00023438 /*DENALI_CTL_253_DATA*/ ++ 0x02020d0f /*DENALI_CTL_254_DATA*/ ++ 0x00140303 /*DENALI_CTL_255_DATA*/ ++ 0x00000000 /*DENALI_CTL_256_DATA*/ ++ 0x00000000 /*DENALI_CTL_257_DATA*/ ++ 0x00001403 /*DENALI_CTL_258_DATA*/ ++ 0x00000000 /*DENALI_CTL_259_DATA*/ ++ 0x00000000 /*DENALI_CTL_260_DATA*/ ++ 0x00000000 /*DENALI_CTL_261_DATA*/ ++ 0x00000000 /*DENALI_CTL_262_DATA*/ ++ 0x0c010000 /*DENALI_CTL_263_DATA*/ ++ 0x00000008 /*DENALI_CTL_264_DATA*/ ++ 0x01375642 /*DENALI_PHY_00_DATA*/ ++ 0x0004c008 /*DENALI_PHY_01_DATA*/ ++ 0x000000da /*DENALI_PHY_02_DATA*/ ++ 0x00000000 /*DENALI_PHY_03_DATA*/ ++ 0x00000000 /*DENALI_PHY_04_DATA*/ ++ 0x00010000 /*DENALI_PHY_05_DATA*/ ++ 0x01DDDD90 /*DENALI_PHY_06_DATA*/ ++ 0x01DDDD90 /*DENALI_PHY_07_DATA*/ ++ 0x01030001 /*DENALI_PHY_08_DATA*/ ++ 0x01000000 /*DENALI_PHY_09_DATA*/ ++ 0x00c00000 /*DENALI_PHY_10_DATA*/ ++ 0x00000007 /*DENALI_PHY_11_DATA*/ ++ 0x00000000 /*DENALI_PHY_12_DATA*/ ++ 0x00000000 /*DENALI_PHY_13_DATA*/ ++ 0x04000408 /*DENALI_PHY_14_DATA*/ ++ 0x00000408 /*DENALI_PHY_15_DATA*/ ++ 0x00e4e400 /*DENALI_PHY_16_DATA*/ ++ 0x00000000 /*DENALI_PHY_17_DATA*/ ++ 0x00000000 /*DENALI_PHY_18_DATA*/ ++ 0x00000000 /*DENALI_PHY_19_DATA*/ ++ 0x00000000 /*DENALI_PHY_20_DATA*/ ++ 0x00000000 /*DENALI_PHY_21_DATA*/ ++ 0x00000000 /*DENALI_PHY_22_DATA*/ ++ 0x00000000 /*DENALI_PHY_23_DATA*/ ++ 0x00000000 /*DENALI_PHY_24_DATA*/ ++ 0x00000000 /*DENALI_PHY_25_DATA*/ ++ 0x00000000 /*DENALI_PHY_26_DATA*/ ++ 0x00000000 /*DENALI_PHY_27_DATA*/ ++ 0x00000000 /*DENALI_PHY_28_DATA*/ ++ 0x00000000 /*DENALI_PHY_29_DATA*/ ++ 0x00000000 /*DENALI_PHY_30_DATA*/ ++ 0x00000000 /*DENALI_PHY_31_DATA*/ ++ 0x00000000 /*DENALI_PHY_32_DATA*/ ++ 0x00200000 /*DENALI_PHY_33_DATA*/ ++ 0x00000000 /*DENALI_PHY_34_DATA*/ ++ 0x00000000 /*DENALI_PHY_35_DATA*/ ++ 0x00000000 /*DENALI_PHY_36_DATA*/ ++ 0x00000000 /*DENALI_PHY_37_DATA*/ ++ 0x00000000 /*DENALI_PHY_38_DATA*/ ++ 0x00000000 /*DENALI_PHY_39_DATA*/ ++ 0x02800280 /*DENALI_PHY_40_DATA*/ ++ 0x02800280 /*DENALI_PHY_41_DATA*/ ++ 0x02800280 /*DENALI_PHY_42_DATA*/ ++ 0x02800280 /*DENALI_PHY_43_DATA*/ ++ 0x00000280 /*DENALI_PHY_44_DATA*/ ++ 0x00000000 /*DENALI_PHY_45_DATA*/ ++ 0x00000000 /*DENALI_PHY_46_DATA*/ ++ 0x00000000 /*DENALI_PHY_47_DATA*/ ++ 0x00000000 /*DENALI_PHY_48_DATA*/ ++ 0x00000000 /*DENALI_PHY_49_DATA*/ ++ 0x00800080 /*DENALI_PHY_50_DATA*/ ++ 0x00800080 /*DENALI_PHY_51_DATA*/ ++ 0x00800080 /*DENALI_PHY_52_DATA*/ ++ 0x00800080 /*DENALI_PHY_53_DATA*/ ++ 0x00800080 /*DENALI_PHY_54_DATA*/ ++ 0x00800080 /*DENALI_PHY_55_DATA*/ ++ 0x00800080 /*DENALI_PHY_56_DATA*/ ++ 0x00800080 /*DENALI_PHY_57_DATA*/ ++ 0x00800080 /*DENALI_PHY_58_DATA*/ ++ 0x000100da /*DENALI_PHY_59_DATA*/ ++ 0x01ff0010 /*DENALI_PHY_60_DATA*/ ++ 0x00000000 /*DENALI_PHY_61_DATA*/ ++ 0x00000000 /*DENALI_PHY_62_DATA*/ ++ 0x00000002 /*DENALI_PHY_63_DATA*/ ++ 0x51313152 /*DENALI_PHY_64_DATA*/ ++ 0x80013130 /*DENALI_PHY_65_DATA*/ ++ 0x02000080 /*DENALI_PHY_66_DATA*/ ++ 0x00100001 /*DENALI_PHY_67_DATA*/ ++ 0x0c064208 /*DENALI_PHY_68_DATA*/ ++ 0x000f0c0f /*DENALI_PHY_69_DATA*/ ++ 0x01000140 /*DENALI_PHY_70_DATA*/ ++ 0x0000000c /*DENALI_PHY_71_DATA*/ ++ 0x00000000 /*DENALI_PHY_72_DATA*/ ++ 0x00000000 /*DENALI_PHY_73_DATA*/ ++ 0x00000000 /*DENALI_PHY_74_DATA*/ ++ 0x00000000 /*DENALI_PHY_75_DATA*/ ++ 0x00000000 /*DENALI_PHY_76_DATA*/ ++ 0x00000000 /*DENALI_PHY_77_DATA*/ ++ 0x00000000 /*DENALI_PHY_78_DATA*/ ++ 0x00000000 /*DENALI_PHY_79_DATA*/ ++ 0x00000000 /*DENALI_PHY_80_DATA*/ ++ 0x00000000 /*DENALI_PHY_81_DATA*/ ++ 0x00000000 /*DENALI_PHY_82_DATA*/ ++ 0x00000000 /*DENALI_PHY_83_DATA*/ ++ 0x00000000 /*DENALI_PHY_84_DATA*/ ++ 0x00000000 /*DENALI_PHY_85_DATA*/ ++ 0x00000000 /*DENALI_PHY_86_DATA*/ ++ 0x00000000 /*DENALI_PHY_87_DATA*/ ++ 0x00000000 /*DENALI_PHY_88_DATA*/ ++ 0x00000000 /*DENALI_PHY_89_DATA*/ ++ 0x00000000 /*DENALI_PHY_90_DATA*/ ++ 0x00000000 /*DENALI_PHY_91_DATA*/ ++ 0x00000000 /*DENALI_PHY_92_DATA*/ ++ 0x00000000 /*DENALI_PHY_93_DATA*/ ++ 0x00000000 /*DENALI_PHY_94_DATA*/ ++ 0x00000000 /*DENALI_PHY_95_DATA*/ ++ 0x00000000 /*DENALI_PHY_96_DATA*/ ++ 0x00000000 /*DENALI_PHY_97_DATA*/ ++ 0x00000000 /*DENALI_PHY_98_DATA*/ ++ 0x00000000 /*DENALI_PHY_99_DATA*/ ++ 0x00000000 /*DENALI_PHY_100_DATA*/ ++ 0x00000000 /*DENALI_PHY_101_DATA*/ ++ 0x00000000 /*DENALI_PHY_102_DATA*/ ++ 0x00000000 /*DENALI_PHY_103_DATA*/ ++ 0x00000000 /*DENALI_PHY_104_DATA*/ ++ 0x00000000 /*DENALI_PHY_105_DATA*/ ++ 0x00000000 /*DENALI_PHY_106_DATA*/ ++ 0x00000000 /*DENALI_PHY_107_DATA*/ ++ 0x00000000 /*DENALI_PHY_108_DATA*/ ++ 0x00000000 /*DENALI_PHY_109_DATA*/ ++ 0x00000000 /*DENALI_PHY_110_DATA*/ ++ 0x00000000 /*DENALI_PHY_111_DATA*/ ++ 0x00000000 /*DENALI_PHY_112_DATA*/ ++ 0x00000000 /*DENALI_PHY_113_DATA*/ ++ 0x00000000 /*DENALI_PHY_114_DATA*/ ++ 0x00000000 /*DENALI_PHY_115_DATA*/ ++ 0x00000000 /*DENALI_PHY_116_DATA*/ ++ 0x00000000 /*DENALI_PHY_117_DATA*/ ++ 0x00000000 /*DENALI_PHY_118_DATA*/ ++ 0x00000000 /*DENALI_PHY_119_DATA*/ ++ 0x00000000 /*DENALI_PHY_120_DATA*/ ++ 0x00000000 /*DENALI_PHY_121_DATA*/ ++ 0x00000000 /*DENALI_PHY_122_DATA*/ ++ 0x00000000 /*DENALI_PHY_123_DATA*/ ++ 0x00000000 /*DENALI_PHY_124_DATA*/ ++ 0x00000000 /*DENALI_PHY_125_DATA*/ ++ 0x00000000 /*DENALI_PHY_126_DATA*/ ++ 0x00000000 /*DENALI_PHY_127_DATA*/ ++ 0x40263571 /*DENALI_PHY_128_DATA*/ ++ 0x0004c008 /*DENALI_PHY_129_DATA*/ ++ 0x000000da /*DENALI_PHY_130_DATA*/ ++ 0x00000000 /*DENALI_PHY_131_DATA*/ ++ 0x00000000 /*DENALI_PHY_132_DATA*/ ++ 0x00010000 /*DENALI_PHY_133_DATA*/ ++ 0x01DDDD90 /*DENALI_PHY_134_DATA*/ ++ 0x01DDDD90 /*DENALI_PHY_135_DATA*/ ++ 0x01030001 /*DENALI_PHY_136_DATA*/ ++ 0x01000000 /*DENALI_PHY_137_DATA*/ ++ 0x00c00000 /*DENALI_PHY_138_DATA*/ ++ 0x00000007 /*DENALI_PHY_139_DATA*/ ++ 0x00000000 /*DENALI_PHY_140_DATA*/ ++ 0x00000000 /*DENALI_PHY_141_DATA*/ ++ 0x04000408 /*DENALI_PHY_142_DATA*/ ++ 0x00000408 /*DENALI_PHY_143_DATA*/ ++ 0x00e4e400 /*DENALI_PHY_144_DATA*/ ++ 0x00000000 /*DENALI_PHY_145_DATA*/ ++ 0x00000000 /*DENALI_PHY_146_DATA*/ ++ 0x00000000 /*DENALI_PHY_147_DATA*/ ++ 0x00000000 /*DENALI_PHY_148_DATA*/ ++ 0x00000000 /*DENALI_PHY_149_DATA*/ ++ 0x00000000 /*DENALI_PHY_150_DATA*/ ++ 0x00000000 /*DENALI_PHY_151_DATA*/ ++ 0x00000000 /*DENALI_PHY_152_DATA*/ ++ 0x00000000 /*DENALI_PHY_153_DATA*/ ++ 0x00000000 /*DENALI_PHY_154_DATA*/ ++ 0x00000000 /*DENALI_PHY_155_DATA*/ ++ 0x00000000 /*DENALI_PHY_156_DATA*/ ++ 0x00000000 /*DENALI_PHY_157_DATA*/ ++ 0x00000000 /*DENALI_PHY_158_DATA*/ ++ 0x00000000 /*DENALI_PHY_159_DATA*/ ++ 0x00000000 /*DENALI_PHY_160_DATA*/ ++ 0x00200000 /*DENALI_PHY_161_DATA*/ ++ 0x00000000 /*DENALI_PHY_162_DATA*/ ++ 0x00000000 /*DENALI_PHY_163_DATA*/ ++ 0x00000000 /*DENALI_PHY_164_DATA*/ ++ 0x00000000 /*DENALI_PHY_165_DATA*/ ++ 0x00000000 /*DENALI_PHY_166_DATA*/ ++ 0x00000000 /*DENALI_PHY_167_DATA*/ ++ 0x02800280 /*DENALI_PHY_168_DATA*/ ++ 0x02800280 /*DENALI_PHY_169_DATA*/ ++ 0x02800280 /*DENALI_PHY_170_DATA*/ ++ 0x02800280 /*DENALI_PHY_171_DATA*/ ++ 0x00000280 /*DENALI_PHY_172_DATA*/ ++ 0x00000000 /*DENALI_PHY_173_DATA*/ ++ 0x00000000 /*DENALI_PHY_174_DATA*/ ++ 0x00000000 /*DENALI_PHY_175_DATA*/ ++ 0x00000000 /*DENALI_PHY_176_DATA*/ ++ 0x00000000 /*DENALI_PHY_177_DATA*/ ++ 0x00800080 /*DENALI_PHY_178_DATA*/ ++ 0x00800080 /*DENALI_PHY_179_DATA*/ ++ 0x00800080 /*DENALI_PHY_180_DATA*/ ++ 0x00800080 /*DENALI_PHY_181_DATA*/ ++ 0x00800080 /*DENALI_PHY_182_DATA*/ ++ 0x00800080 /*DENALI_PHY_183_DATA*/ ++ 0x00800080 /*DENALI_PHY_184_DATA*/ ++ 0x00800080 /*DENALI_PHY_185_DATA*/ ++ 0x00800080 /*DENALI_PHY_186_DATA*/ ++ 0x000100da /*DENALI_PHY_187_DATA*/ ++ 0x01ff0010 /*DENALI_PHY_188_DATA*/ ++ 0x00000000 /*DENALI_PHY_189_DATA*/ ++ 0x00000000 /*DENALI_PHY_190_DATA*/ ++ 0x00000002 /*DENALI_PHY_191_DATA*/ ++ 0x51313152 /*DENALI_PHY_192_DATA*/ ++ 0x80013130 /*DENALI_PHY_193_DATA*/ ++ 0x02000080 /*DENALI_PHY_194_DATA*/ ++ 0x00100001 /*DENALI_PHY_195_DATA*/ ++ 0x0c064208 /*DENALI_PHY_196_DATA*/ ++ 0x000f0c0f /*DENALI_PHY_197_DATA*/ ++ 0x01000140 /*DENALI_PHY_198_DATA*/ ++ 0x0000000c /*DENALI_PHY_199_DATA*/ ++ 0x00000000 /*DENALI_PHY_200_DATA*/ ++ 0x00000000 /*DENALI_PHY_201_DATA*/ ++ 0x00000000 /*DENALI_PHY_202_DATA*/ ++ 0x00000000 /*DENALI_PHY_203_DATA*/ ++ 0x00000000 /*DENALI_PHY_204_DATA*/ ++ 0x00000000 /*DENALI_PHY_205_DATA*/ ++ 0x00000000 /*DENALI_PHY_206_DATA*/ ++ 0x00000000 /*DENALI_PHY_207_DATA*/ ++ 0x00000000 /*DENALI_PHY_208_DATA*/ ++ 0x00000000 /*DENALI_PHY_209_DATA*/ ++ 0x00000000 /*DENALI_PHY_210_DATA*/ ++ 0x00000000 /*DENALI_PHY_211_DATA*/ ++ 0x00000000 /*DENALI_PHY_212_DATA*/ ++ 0x00000000 /*DENALI_PHY_213_DATA*/ ++ 0x00000000 /*DENALI_PHY_214_DATA*/ ++ 0x00000000 /*DENALI_PHY_215_DATA*/ ++ 0x00000000 /*DENALI_PHY_216_DATA*/ ++ 0x00000000 /*DENALI_PHY_217_DATA*/ ++ 0x00000000 /*DENALI_PHY_218_DATA*/ ++ 0x00000000 /*DENALI_PHY_219_DATA*/ ++ 0x00000000 /*DENALI_PHY_220_DATA*/ ++ 0x00000000 /*DENALI_PHY_221_DATA*/ ++ 0x00000000 /*DENALI_PHY_222_DATA*/ ++ 0x00000000 /*DENALI_PHY_223_DATA*/ ++ 0x00000000 /*DENALI_PHY_224_DATA*/ ++ 0x00000000 /*DENALI_PHY_225_DATA*/ ++ 0x00000000 /*DENALI_PHY_226_DATA*/ ++ 0x00000000 /*DENALI_PHY_227_DATA*/ ++ 0x00000000 /*DENALI_PHY_228_DATA*/ ++ 0x00000000 /*DENALI_PHY_229_DATA*/ ++ 0x00000000 /*DENALI_PHY_230_DATA*/ ++ 0x00000000 /*DENALI_PHY_231_DATA*/ ++ 0x00000000 /*DENALI_PHY_232_DATA*/ ++ 0x00000000 /*DENALI_PHY_233_DATA*/ ++ 0x00000000 /*DENALI_PHY_234_DATA*/ ++ 0x00000000 /*DENALI_PHY_235_DATA*/ ++ 0x00000000 /*DENALI_PHY_236_DATA*/ ++ 0x00000000 /*DENALI_PHY_237_DATA*/ ++ 0x00000000 /*DENALI_PHY_238_DATA*/ ++ 0x00000000 /*DENALI_PHY_239_DATA*/ ++ 0x00000000 /*DENALI_PHY_240_DATA*/ ++ 0x00000000 /*DENALI_PHY_241_DATA*/ ++ 0x00000000 /*DENALI_PHY_242_DATA*/ ++ 0x00000000 /*DENALI_PHY_243_DATA*/ ++ 0x00000000 /*DENALI_PHY_244_DATA*/ ++ 0x00000000 /*DENALI_PHY_245_DATA*/ ++ 0x00000000 /*DENALI_PHY_246_DATA*/ ++ 0x00000000 /*DENALI_PHY_247_DATA*/ ++ 0x00000000 /*DENALI_PHY_248_DATA*/ ++ 0x00000000 /*DENALI_PHY_249_DATA*/ ++ 0x00000000 /*DENALI_PHY_250_DATA*/ ++ 0x00000000 /*DENALI_PHY_251_DATA*/ ++ 0x00000000 /*DENALI_PHY_252_DATA*/ ++ 0x00000000 /*DENALI_PHY_253_DATA*/ ++ 0x00000000 /*DENALI_PHY_254_DATA*/ ++ 0x00000000 /*DENALI_PHY_255_DATA*/ ++ 0x46052371 /*DENALI_PHY_256_DATA*/ ++ 0x0004c008 /*DENALI_PHY_257_DATA*/ ++ 0x000000da /*DENALI_PHY_258_DATA*/ ++ 0x00000000 /*DENALI_PHY_259_DATA*/ ++ 0x00000000 /*DENALI_PHY_260_DATA*/ ++ 0x00010000 /*DENALI_PHY_261_DATA*/ ++ 0x01DDDD90 /*DENALI_PHY_262_DATA*/ ++ 0x01DDDD90 /*DENALI_PHY_263_DATA*/ ++ 0x01030001 /*DENALI_PHY_264_DATA*/ ++ 0x01000000 /*DENALI_PHY_265_DATA*/ ++ 0x00c00000 /*DENALI_PHY_266_DATA*/ ++ 0x00000007 /*DENALI_PHY_267_DATA*/ ++ 0x00000000 /*DENALI_PHY_268_DATA*/ ++ 0x00000000 /*DENALI_PHY_269_DATA*/ ++ 0x04000408 /*DENALI_PHY_270_DATA*/ ++ 0x00000408 /*DENALI_PHY_271_DATA*/ ++ 0x00e4e400 /*DENALI_PHY_272_DATA*/ ++ 0x00000000 /*DENALI_PHY_273_DATA*/ ++ 0x00000000 /*DENALI_PHY_274_DATA*/ ++ 0x00000000 /*DENALI_PHY_275_DATA*/ ++ 0x00000000 /*DENALI_PHY_276_DATA*/ ++ 0x00000000 /*DENALI_PHY_277_DATA*/ ++ 0x00000000 /*DENALI_PHY_278_DATA*/ ++ 0x00000000 /*DENALI_PHY_279_DATA*/ ++ 0x00000000 /*DENALI_PHY_280_DATA*/ ++ 0x00000000 /*DENALI_PHY_281_DATA*/ ++ 0x00000000 /*DENALI_PHY_282_DATA*/ ++ 0x00000000 /*DENALI_PHY_283_DATA*/ ++ 0x00000000 /*DENALI_PHY_284_DATA*/ ++ 0x00000000 /*DENALI_PHY_285_DATA*/ ++ 0x00000000 /*DENALI_PHY_286_DATA*/ ++ 0x00000000 /*DENALI_PHY_287_DATA*/ ++ 0x00000000 /*DENALI_PHY_288_DATA*/ ++ 0x00200000 /*DENALI_PHY_289_DATA*/ ++ 0x00000000 /*DENALI_PHY_290_DATA*/ ++ 0x00000000 /*DENALI_PHY_291_DATA*/ ++ 0x00000000 /*DENALI_PHY_292_DATA*/ ++ 0x00000000 /*DENALI_PHY_293_DATA*/ ++ 0x00000000 /*DENALI_PHY_294_DATA*/ ++ 0x00000000 /*DENALI_PHY_295_DATA*/ ++ 0x02800280 /*DENALI_PHY_296_DATA*/ ++ 0x02800280 /*DENALI_PHY_297_DATA*/ ++ 0x02800280 /*DENALI_PHY_298_DATA*/ ++ 0x02800280 /*DENALI_PHY_299_DATA*/ ++ 0x00000280 /*DENALI_PHY_300_DATA*/ ++ 0x00000000 /*DENALI_PHY_301_DATA*/ ++ 0x00000000 /*DENALI_PHY_302_DATA*/ ++ 0x00000000 /*DENALI_PHY_303_DATA*/ ++ 0x00000000 /*DENALI_PHY_304_DATA*/ ++ 0x00000000 /*DENALI_PHY_305_DATA*/ ++ 0x00800080 /*DENALI_PHY_306_DATA*/ ++ 0x00800080 /*DENALI_PHY_307_DATA*/ ++ 0x00800080 /*DENALI_PHY_308_DATA*/ ++ 0x00800080 /*DENALI_PHY_309_DATA*/ ++ 0x00800080 /*DENALI_PHY_310_DATA*/ ++ 0x00800080 /*DENALI_PHY_311_DATA*/ ++ 0x00800080 /*DENALI_PHY_312_DATA*/ ++ 0x00800080 /*DENALI_PHY_313_DATA*/ ++ 0x00800080 /*DENALI_PHY_314_DATA*/ ++ 0x000100da /*DENALI_PHY_315_DATA*/ ++ 0x01ff0010 /*DENALI_PHY_316_DATA*/ ++ 0x00000000 /*DENALI_PHY_317_DATA*/ ++ 0x00000000 /*DENALI_PHY_318_DATA*/ ++ 0x00000002 /*DENALI_PHY_319_DATA*/ ++ 0x51313152 /*DENALI_PHY_320_DATA*/ ++ 0x80013130 /*DENALI_PHY_321_DATA*/ ++ 0x02000080 /*DENALI_PHY_322_DATA*/ ++ 0x00100001 /*DENALI_PHY_323_DATA*/ ++ 0x0c064208 /*DENALI_PHY_324_DATA*/ ++ 0x000f0c0f /*DENALI_PHY_325_DATA*/ ++ 0x01000140 /*DENALI_PHY_326_DATA*/ ++ 0x0000000c /*DENALI_PHY_327_DATA*/ ++ 0x00000000 /*DENALI_PHY_328_DATA*/ ++ 0x00000000 /*DENALI_PHY_329_DATA*/ ++ 0x00000000 /*DENALI_PHY_330_DATA*/ ++ 0x00000000 /*DENALI_PHY_331_DATA*/ ++ 0x00000000 /*DENALI_PHY_332_DATA*/ ++ 0x00000000 /*DENALI_PHY_333_DATA*/ ++ 0x00000000 /*DENALI_PHY_334_DATA*/ ++ 0x00000000 /*DENALI_PHY_335_DATA*/ ++ 0x00000000 /*DENALI_PHY_336_DATA*/ ++ 0x00000000 /*DENALI_PHY_337_DATA*/ ++ 0x00000000 /*DENALI_PHY_338_DATA*/ ++ 0x00000000 /*DENALI_PHY_339_DATA*/ ++ 0x00000000 /*DENALI_PHY_340_DATA*/ ++ 0x00000000 /*DENALI_PHY_341_DATA*/ ++ 0x00000000 /*DENALI_PHY_342_DATA*/ ++ 0x00000000 /*DENALI_PHY_343_DATA*/ ++ 0x00000000 /*DENALI_PHY_344_DATA*/ ++ 0x00000000 /*DENALI_PHY_345_DATA*/ ++ 0x00000000 /*DENALI_PHY_346_DATA*/ ++ 0x00000000 /*DENALI_PHY_347_DATA*/ ++ 0x00000000 /*DENALI_PHY_348_DATA*/ ++ 0x00000000 /*DENALI_PHY_349_DATA*/ ++ 0x00000000 /*DENALI_PHY_350_DATA*/ ++ 0x00000000 /*DENALI_PHY_351_DATA*/ ++ 0x00000000 /*DENALI_PHY_352_DATA*/ ++ 0x00000000 /*DENALI_PHY_353_DATA*/ ++ 0x00000000 /*DENALI_PHY_354_DATA*/ ++ 0x00000000 /*DENALI_PHY_355_DATA*/ ++ 0x00000000 /*DENALI_PHY_356_DATA*/ ++ 0x00000000 /*DENALI_PHY_357_DATA*/ ++ 0x00000000 /*DENALI_PHY_358_DATA*/ ++ 0x00000000 /*DENALI_PHY_359_DATA*/ ++ 0x00000000 /*DENALI_PHY_360_DATA*/ ++ 0x00000000 /*DENALI_PHY_361_DATA*/ ++ 0x00000000 /*DENALI_PHY_362_DATA*/ ++ 0x00000000 /*DENALI_PHY_363_DATA*/ ++ 0x00000000 /*DENALI_PHY_364_DATA*/ ++ 0x00000000 /*DENALI_PHY_365_DATA*/ ++ 0x00000000 /*DENALI_PHY_366_DATA*/ ++ 0x00000000 /*DENALI_PHY_367_DATA*/ ++ 0x00000000 /*DENALI_PHY_368_DATA*/ ++ 0x00000000 /*DENALI_PHY_369_DATA*/ ++ 0x00000000 /*DENALI_PHY_370_DATA*/ ++ 0x00000000 /*DENALI_PHY_371_DATA*/ ++ 0x00000000 /*DENALI_PHY_372_DATA*/ ++ 0x00000000 /*DENALI_PHY_373_DATA*/ ++ 0x00000000 /*DENALI_PHY_374_DATA*/ ++ 0x00000000 /*DENALI_PHY_375_DATA*/ ++ 0x00000000 /*DENALI_PHY_376_DATA*/ ++ 0x00000000 /*DENALI_PHY_377_DATA*/ ++ 0x00000000 /*DENALI_PHY_378_DATA*/ ++ 0x00000000 /*DENALI_PHY_379_DATA*/ ++ 0x00000000 /*DENALI_PHY_380_DATA*/ ++ 0x00000000 /*DENALI_PHY_381_DATA*/ ++ 0x00000000 /*DENALI_PHY_382_DATA*/ ++ 0x00000000 /*DENALI_PHY_383_DATA*/ ++ 0x37651240 /*DENALI_PHY_384_DATA*/ ++ 0x0004c008 /*DENALI_PHY_385_DATA*/ ++ 0x000000da /*DENALI_PHY_386_DATA*/ ++ 0x00000000 /*DENALI_PHY_387_DATA*/ ++ 0x00000000 /*DENALI_PHY_388_DATA*/ ++ 0x00010000 /*DENALI_PHY_389_DATA*/ ++ 0x01DDDD90 /*DENALI_PHY_390_DATA*/ ++ 0x01DDDD90 /*DENALI_PHY_391_DATA*/ ++ 0x01030001 /*DENALI_PHY_392_DATA*/ ++ 0x01000000 /*DENALI_PHY_393_DATA*/ ++ 0x00c00000 /*DENALI_PHY_394_DATA*/ ++ 0x00000007 /*DENALI_PHY_395_DATA*/ ++ 0x00000000 /*DENALI_PHY_396_DATA*/ ++ 0x00000000 /*DENALI_PHY_397_DATA*/ ++ 0x04000408 /*DENALI_PHY_398_DATA*/ ++ 0x00000408 /*DENALI_PHY_399_DATA*/ ++ 0x00e4e400 /*DENALI_PHY_400_DATA*/ ++ 0x00000000 /*DENALI_PHY_401_DATA*/ ++ 0x00000000 /*DENALI_PHY_402_DATA*/ ++ 0x00000000 /*DENALI_PHY_403_DATA*/ ++ 0x00000000 /*DENALI_PHY_404_DATA*/ ++ 0x00000000 /*DENALI_PHY_405_DATA*/ ++ 0x00000000 /*DENALI_PHY_406_DATA*/ ++ 0x00000000 /*DENALI_PHY_407_DATA*/ ++ 0x00000000 /*DENALI_PHY_408_DATA*/ ++ 0x00000000 /*DENALI_PHY_409_DATA*/ ++ 0x00000000 /*DENALI_PHY_410_DATA*/ ++ 0x00000000 /*DENALI_PHY_411_DATA*/ ++ 0x00000000 /*DENALI_PHY_412_DATA*/ ++ 0x00000000 /*DENALI_PHY_413_DATA*/ ++ 0x00000000 /*DENALI_PHY_414_DATA*/ ++ 0x00000000 /*DENALI_PHY_415_DATA*/ ++ 0x00000000 /*DENALI_PHY_416_DATA*/ ++ 0x00200000 /*DENALI_PHY_417_DATA*/ ++ 0x00000000 /*DENALI_PHY_418_DATA*/ ++ 0x00000000 /*DENALI_PHY_419_DATA*/ ++ 0x00000000 /*DENALI_PHY_420_DATA*/ ++ 0x00000000 /*DENALI_PHY_421_DATA*/ ++ 0x00000000 /*DENALI_PHY_422_DATA*/ ++ 0x00000000 /*DENALI_PHY_423_DATA*/ ++ 0x02800280 /*DENALI_PHY_424_DATA*/ ++ 0x02800280 /*DENALI_PHY_425_DATA*/ ++ 0x02800280 /*DENALI_PHY_426_DATA*/ ++ 0x02800280 /*DENALI_PHY_427_DATA*/ ++ 0x00000280 /*DENALI_PHY_428_DATA*/ ++ 0x00000000 /*DENALI_PHY_429_DATA*/ ++ 0x00000000 /*DENALI_PHY_430_DATA*/ ++ 0x00000000 /*DENALI_PHY_431_DATA*/ ++ 0x00000000 /*DENALI_PHY_432_DATA*/ ++ 0x00000000 /*DENALI_PHY_433_DATA*/ ++ 0x00800080 /*DENALI_PHY_434_DATA*/ ++ 0x00800080 /*DENALI_PHY_435_DATA*/ ++ 0x00800080 /*DENALI_PHY_436_DATA*/ ++ 0x00800080 /*DENALI_PHY_437_DATA*/ ++ 0x00800080 /*DENALI_PHY_438_DATA*/ ++ 0x00800080 /*DENALI_PHY_439_DATA*/ ++ 0x00800080 /*DENALI_PHY_440_DATA*/ ++ 0x00800080 /*DENALI_PHY_441_DATA*/ ++ 0x00800080 /*DENALI_PHY_442_DATA*/ ++ 0x000100da /*DENALI_PHY_443_DATA*/ ++ 0x01ff0010 /*DENALI_PHY_444_DATA*/ ++ 0x00000000 /*DENALI_PHY_445_DATA*/ ++ 0x00000000 /*DENALI_PHY_446_DATA*/ ++ 0x00000002 /*DENALI_PHY_447_DATA*/ ++ 0x51313152 /*DENALI_PHY_448_DATA*/ ++ 0x80013130 /*DENALI_PHY_449_DATA*/ ++ 0x02000080 /*DENALI_PHY_450_DATA*/ ++ 0x00100001 /*DENALI_PHY_451_DATA*/ ++ 0x0c064208 /*DENALI_PHY_452_DATA*/ ++ 0x000f0c0f /*DENALI_PHY_453_DATA*/ ++ 0x01000140 /*DENALI_PHY_454_DATA*/ ++ 0x0000000c /*DENALI_PHY_455_DATA*/ ++ 0x00000000 /*DENALI_PHY_456_DATA*/ ++ 0x00000000 /*DENALI_PHY_457_DATA*/ ++ 0x00000000 /*DENALI_PHY_458_DATA*/ ++ 0x00000000 /*DENALI_PHY_459_DATA*/ ++ 0x00000000 /*DENALI_PHY_460_DATA*/ ++ 0x00000000 /*DENALI_PHY_461_DATA*/ ++ 0x00000000 /*DENALI_PHY_462_DATA*/ ++ 0x00000000 /*DENALI_PHY_463_DATA*/ ++ 0x00000000 /*DENALI_PHY_464_DATA*/ ++ 0x00000000 /*DENALI_PHY_465_DATA*/ ++ 0x00000000 /*DENALI_PHY_466_DATA*/ ++ 0x00000000 /*DENALI_PHY_467_DATA*/ ++ 0x00000000 /*DENALI_PHY_468_DATA*/ ++ 0x00000000 /*DENALI_PHY_469_DATA*/ ++ 0x00000000 /*DENALI_PHY_470_DATA*/ ++ 0x00000000 /*DENALI_PHY_471_DATA*/ ++ 0x00000000 /*DENALI_PHY_472_DATA*/ ++ 0x00000000 /*DENALI_PHY_473_DATA*/ ++ 0x00000000 /*DENALI_PHY_474_DATA*/ ++ 0x00000000 /*DENALI_PHY_475_DATA*/ ++ 0x00000000 /*DENALI_PHY_476_DATA*/ ++ 0x00000000 /*DENALI_PHY_477_DATA*/ ++ 0x00000000 /*DENALI_PHY_478_DATA*/ ++ 0x00000000 /*DENALI_PHY_479_DATA*/ ++ 0x00000000 /*DENALI_PHY_480_DATA*/ ++ 0x00000000 /*DENALI_PHY_481_DATA*/ ++ 0x00000000 /*DENALI_PHY_482_DATA*/ ++ 0x00000000 /*DENALI_PHY_483_DATA*/ ++ 0x00000000 /*DENALI_PHY_484_DATA*/ ++ 0x00000000 /*DENALI_PHY_485_DATA*/ ++ 0x00000000 /*DENALI_PHY_486_DATA*/ ++ 0x00000000 /*DENALI_PHY_487_DATA*/ ++ 0x00000000 /*DENALI_PHY_488_DATA*/ ++ 0x00000000 /*DENALI_PHY_489_DATA*/ ++ 0x00000000 /*DENALI_PHY_490_DATA*/ ++ 0x00000000 /*DENALI_PHY_491_DATA*/ ++ 0x00000000 /*DENALI_PHY_492_DATA*/ ++ 0x00000000 /*DENALI_PHY_493_DATA*/ ++ 0x00000000 /*DENALI_PHY_494_DATA*/ ++ 0x00000000 /*DENALI_PHY_495_DATA*/ ++ 0x00000000 /*DENALI_PHY_496_DATA*/ ++ 0x00000000 /*DENALI_PHY_497_DATA*/ ++ 0x00000000 /*DENALI_PHY_498_DATA*/ ++ 0x00000000 /*DENALI_PHY_499_DATA*/ ++ 0x00000000 /*DENALI_PHY_500_DATA*/ ++ 0x00000000 /*DENALI_PHY_501_DATA*/ ++ 0x00000000 /*DENALI_PHY_502_DATA*/ ++ 0x00000000 /*DENALI_PHY_503_DATA*/ ++ 0x00000000 /*DENALI_PHY_504_DATA*/ ++ 0x00000000 /*DENALI_PHY_505_DATA*/ ++ 0x00000000 /*DENALI_PHY_506_DATA*/ ++ 0x00000000 /*DENALI_PHY_507_DATA*/ ++ 0x00000000 /*DENALI_PHY_508_DATA*/ ++ 0x00000000 /*DENALI_PHY_509_DATA*/ ++ 0x00000000 /*DENALI_PHY_510_DATA*/ ++ 0x00000000 /*DENALI_PHY_511_DATA*/ ++ 0x34216750 /*DENALI_PHY_512_DATA*/ ++ 0x0004c008 /*DENALI_PHY_513_DATA*/ ++ 0x000000da /*DENALI_PHY_514_DATA*/ ++ 0x00000000 /*DENALI_PHY_515_DATA*/ ++ 0x00000000 /*DENALI_PHY_516_DATA*/ ++ 0x00010000 /*DENALI_PHY_517_DATA*/ ++ 0x01DDDD90 /*DENALI_PHY_518_DATA*/ ++ 0x01DDDD90 /*DENALI_PHY_519_DATA*/ ++ 0x01030001 /*DENALI_PHY_520_DATA*/ ++ 0x01000000 /*DENALI_PHY_521_DATA*/ ++ 0x00c00000 /*DENALI_PHY_522_DATA*/ ++ 0x00000007 /*DENALI_PHY_523_DATA*/ ++ 0x00000000 /*DENALI_PHY_524_DATA*/ ++ 0x00000000 /*DENALI_PHY_525_DATA*/ ++ 0x04000408 /*DENALI_PHY_526_DATA*/ ++ 0x00000408 /*DENALI_PHY_527_DATA*/ ++ 0x00e4e400 /*DENALI_PHY_528_DATA*/ ++ 0x00000000 /*DENALI_PHY_529_DATA*/ ++ 0x00000000 /*DENALI_PHY_530_DATA*/ ++ 0x00000000 /*DENALI_PHY_531_DATA*/ ++ 0x00000000 /*DENALI_PHY_532_DATA*/ ++ 0x00000000 /*DENALI_PHY_533_DATA*/ ++ 0x00000000 /*DENALI_PHY_534_DATA*/ ++ 0x00000000 /*DENALI_PHY_535_DATA*/ ++ 0x00000000 /*DENALI_PHY_536_DATA*/ ++ 0x00000000 /*DENALI_PHY_537_DATA*/ ++ 0x00000000 /*DENALI_PHY_538_DATA*/ ++ 0x00000000 /*DENALI_PHY_539_DATA*/ ++ 0x00000000 /*DENALI_PHY_540_DATA*/ ++ 0x00000000 /*DENALI_PHY_541_DATA*/ ++ 0x00000000 /*DENALI_PHY_542_DATA*/ ++ 0x00000000 /*DENALI_PHY_543_DATA*/ ++ 0x00000000 /*DENALI_PHY_544_DATA*/ ++ 0x00200000 /*DENALI_PHY_545_DATA*/ ++ 0x00000000 /*DENALI_PHY_546_DATA*/ ++ 0x00000000 /*DENALI_PHY_547_DATA*/ ++ 0x00000000 /*DENALI_PHY_548_DATA*/ ++ 0x00000000 /*DENALI_PHY_549_DATA*/ ++ 0x00000000 /*DENALI_PHY_550_DATA*/ ++ 0x00000000 /*DENALI_PHY_551_DATA*/ ++ 0x02800280 /*DENALI_PHY_552_DATA*/ ++ 0x02800280 /*DENALI_PHY_553_DATA*/ ++ 0x02800280 /*DENALI_PHY_554_DATA*/ ++ 0x02800280 /*DENALI_PHY_555_DATA*/ ++ 0x00000280 /*DENALI_PHY_556_DATA*/ ++ 0x00000000 /*DENALI_PHY_557_DATA*/ ++ 0x00000000 /*DENALI_PHY_558_DATA*/ ++ 0x00000000 /*DENALI_PHY_559_DATA*/ ++ 0x00000000 /*DENALI_PHY_560_DATA*/ ++ 0x00000000 /*DENALI_PHY_561_DATA*/ ++ 0x00800080 /*DENALI_PHY_562_DATA*/ ++ 0x00800080 /*DENALI_PHY_563_DATA*/ ++ 0x00800080 /*DENALI_PHY_564_DATA*/ ++ 0x00800080 /*DENALI_PHY_565_DATA*/ ++ 0x00800080 /*DENALI_PHY_566_DATA*/ ++ 0x00800080 /*DENALI_PHY_567_DATA*/ ++ 0x00800080 /*DENALI_PHY_568_DATA*/ ++ 0x00800080 /*DENALI_PHY_569_DATA*/ ++ 0x00800080 /*DENALI_PHY_570_DATA*/ ++ 0x000100da /*DENALI_PHY_571_DATA*/ ++ 0x01ff0010 /*DENALI_PHY_572_DATA*/ ++ 0x00000000 /*DENALI_PHY_573_DATA*/ ++ 0x00000000 /*DENALI_PHY_574_DATA*/ ++ 0x00000002 /*DENALI_PHY_575_DATA*/ ++ 0x51313152 /*DENALI_PHY_576_DATA*/ ++ 0x80013130 /*DENALI_PHY_577_DATA*/ ++ 0x02000080 /*DENALI_PHY_578_DATA*/ ++ 0x00100001 /*DENALI_PHY_579_DATA*/ ++ 0x0c064208 /*DENALI_PHY_580_DATA*/ ++ 0x000f0c0f /*DENALI_PHY_581_DATA*/ ++ 0x01000140 /*DENALI_PHY_582_DATA*/ ++ 0x0000000c /*DENALI_PHY_583_DATA*/ ++ 0x00000000 /*DENALI_PHY_584_DATA*/ ++ 0x00000000 /*DENALI_PHY_585_DATA*/ ++ 0x00000000 /*DENALI_PHY_586_DATA*/ ++ 0x00000000 /*DENALI_PHY_587_DATA*/ ++ 0x00000000 /*DENALI_PHY_588_DATA*/ ++ 0x00000000 /*DENALI_PHY_589_DATA*/ ++ 0x00000000 /*DENALI_PHY_590_DATA*/ ++ 0x00000000 /*DENALI_PHY_591_DATA*/ ++ 0x00000000 /*DENALI_PHY_592_DATA*/ ++ 0x00000000 /*DENALI_PHY_593_DATA*/ ++ 0x00000000 /*DENALI_PHY_594_DATA*/ ++ 0x00000000 /*DENALI_PHY_595_DATA*/ ++ 0x00000000 /*DENALI_PHY_596_DATA*/ ++ 0x00000000 /*DENALI_PHY_597_DATA*/ ++ 0x00000000 /*DENALI_PHY_598_DATA*/ ++ 0x00000000 /*DENALI_PHY_599_DATA*/ ++ 0x00000000 /*DENALI_PHY_600_DATA*/ ++ 0x00000000 /*DENALI_PHY_601_DATA*/ ++ 0x00000000 /*DENALI_PHY_602_DATA*/ ++ 0x00000000 /*DENALI_PHY_603_DATA*/ ++ 0x00000000 /*DENALI_PHY_604_DATA*/ ++ 0x00000000 /*DENALI_PHY_605_DATA*/ ++ 0x00000000 /*DENALI_PHY_606_DATA*/ ++ 0x00000000 /*DENALI_PHY_607_DATA*/ ++ 0x00000000 /*DENALI_PHY_608_DATA*/ ++ 0x00000000 /*DENALI_PHY_609_DATA*/ ++ 0x00000000 /*DENALI_PHY_610_DATA*/ ++ 0x00000000 /*DENALI_PHY_611_DATA*/ ++ 0x00000000 /*DENALI_PHY_612_DATA*/ ++ 0x00000000 /*DENALI_PHY_613_DATA*/ ++ 0x00000000 /*DENALI_PHY_614_DATA*/ ++ 0x00000000 /*DENALI_PHY_615_DATA*/ ++ 0x00000000 /*DENALI_PHY_616_DATA*/ ++ 0x00000000 /*DENALI_PHY_617_DATA*/ ++ 0x00000000 /*DENALI_PHY_618_DATA*/ ++ 0x00000000 /*DENALI_PHY_619_DATA*/ ++ 0x00000000 /*DENALI_PHY_620_DATA*/ ++ 0x00000000 /*DENALI_PHY_621_DATA*/ ++ 0x00000000 /*DENALI_PHY_622_DATA*/ ++ 0x00000000 /*DENALI_PHY_623_DATA*/ ++ 0x00000000 /*DENALI_PHY_624_DATA*/ ++ 0x00000000 /*DENALI_PHY_625_DATA*/ ++ 0x00000000 /*DENALI_PHY_626_DATA*/ ++ 0x00000000 /*DENALI_PHY_627_DATA*/ ++ 0x00000000 /*DENALI_PHY_628_DATA*/ ++ 0x00000000 /*DENALI_PHY_629_DATA*/ ++ 0x00000000 /*DENALI_PHY_630_DATA*/ ++ 0x00000000 /*DENALI_PHY_631_DATA*/ ++ 0x00000000 /*DENALI_PHY_632_DATA*/ ++ 0x00000000 /*DENALI_PHY_633_DATA*/ ++ 0x00000000 /*DENALI_PHY_634_DATA*/ ++ 0x00000000 /*DENALI_PHY_635_DATA*/ ++ 0x00000000 /*DENALI_PHY_636_DATA*/ ++ 0x00000000 /*DENALI_PHY_637_DATA*/ ++ 0x00000000 /*DENALI_PHY_638_DATA*/ ++ 0x00000000 /*DENALI_PHY_639_DATA*/ ++ 0x35176402 /*DENALI_PHY_640_DATA*/ ++ 0x0004c008 /*DENALI_PHY_641_DATA*/ ++ 0x000000da /*DENALI_PHY_642_DATA*/ ++ 0x00000000 /*DENALI_PHY_643_DATA*/ ++ 0x00000000 /*DENALI_PHY_644_DATA*/ ++ 0x00010000 /*DENALI_PHY_645_DATA*/ ++ 0x01DDDD90 /*DENALI_PHY_646_DATA*/ ++ 0x01DDDD90 /*DENALI_PHY_647_DATA*/ ++ 0x01030001 /*DENALI_PHY_648_DATA*/ ++ 0x01000000 /*DENALI_PHY_649_DATA*/ ++ 0x00c00000 /*DENALI_PHY_650_DATA*/ ++ 0x00000007 /*DENALI_PHY_651_DATA*/ ++ 0x00000000 /*DENALI_PHY_652_DATA*/ ++ 0x00000000 /*DENALI_PHY_653_DATA*/ ++ 0x04000408 /*DENALI_PHY_654_DATA*/ ++ 0x00000408 /*DENALI_PHY_655_DATA*/ ++ 0x00e4e400 /*DENALI_PHY_656_DATA*/ ++ 0x00000000 /*DENALI_PHY_657_DATA*/ ++ 0x00000000 /*DENALI_PHY_658_DATA*/ ++ 0x00000000 /*DENALI_PHY_659_DATA*/ ++ 0x00000000 /*DENALI_PHY_660_DATA*/ ++ 0x00000000 /*DENALI_PHY_661_DATA*/ ++ 0x00000000 /*DENALI_PHY_662_DATA*/ ++ 0x00000000 /*DENALI_PHY_663_DATA*/ ++ 0x00000000 /*DENALI_PHY_664_DATA*/ ++ 0x00000000 /*DENALI_PHY_665_DATA*/ ++ 0x00000000 /*DENALI_PHY_666_DATA*/ ++ 0x00000000 /*DENALI_PHY_667_DATA*/ ++ 0x00000000 /*DENALI_PHY_668_DATA*/ ++ 0x00000000 /*DENALI_PHY_669_DATA*/ ++ 0x00000000 /*DENALI_PHY_670_DATA*/ ++ 0x00000000 /*DENALI_PHY_671_DATA*/ ++ 0x00000000 /*DENALI_PHY_672_DATA*/ ++ 0x00200000 /*DENALI_PHY_673_DATA*/ ++ 0x00000000 /*DENALI_PHY_674_DATA*/ ++ 0x00000000 /*DENALI_PHY_675_DATA*/ ++ 0x00000000 /*DENALI_PHY_676_DATA*/ ++ 0x00000000 /*DENALI_PHY_677_DATA*/ ++ 0x00000000 /*DENALI_PHY_678_DATA*/ ++ 0x00000000 /*DENALI_PHY_679_DATA*/ ++ 0x02800280 /*DENALI_PHY_680_DATA*/ ++ 0x02800280 /*DENALI_PHY_681_DATA*/ ++ 0x02800280 /*DENALI_PHY_682_DATA*/ ++ 0x02800280 /*DENALI_PHY_683_DATA*/ ++ 0x00000280 /*DENALI_PHY_684_DATA*/ ++ 0x00000000 /*DENALI_PHY_685_DATA*/ ++ 0x00000000 /*DENALI_PHY_686_DATA*/ ++ 0x00000000 /*DENALI_PHY_687_DATA*/ ++ 0x00000000 /*DENALI_PHY_688_DATA*/ ++ 0x00000000 /*DENALI_PHY_689_DATA*/ ++ 0x00800080 /*DENALI_PHY_690_DATA*/ ++ 0x00800080 /*DENALI_PHY_691_DATA*/ ++ 0x00800080 /*DENALI_PHY_692_DATA*/ ++ 0x00800080 /*DENALI_PHY_693_DATA*/ ++ 0x00800080 /*DENALI_PHY_694_DATA*/ ++ 0x00800080 /*DENALI_PHY_695_DATA*/ ++ 0x00800080 /*DENALI_PHY_696_DATA*/ ++ 0x00800080 /*DENALI_PHY_697_DATA*/ ++ 0x00800080 /*DENALI_PHY_698_DATA*/ ++ 0x000100da /*DENALI_PHY_699_DATA*/ ++ 0x01ff0010 /*DENALI_PHY_700_DATA*/ ++ 0x00000000 /*DENALI_PHY_701_DATA*/ ++ 0x00000000 /*DENALI_PHY_702_DATA*/ ++ 0x00000002 /*DENALI_PHY_703_DATA*/ ++ 0x51313152 /*DENALI_PHY_704_DATA*/ ++ 0x80013130 /*DENALI_PHY_705_DATA*/ ++ 0x02000080 /*DENALI_PHY_706_DATA*/ ++ 0x00100001 /*DENALI_PHY_707_DATA*/ ++ 0x0c064208 /*DENALI_PHY_708_DATA*/ ++ 0x000f0c0f /*DENALI_PHY_709_DATA*/ ++ 0x01000140 /*DENALI_PHY_710_DATA*/ ++ 0x0000000c /*DENALI_PHY_711_DATA*/ ++ 0x00000000 /*DENALI_PHY_712_DATA*/ ++ 0x00000000 /*DENALI_PHY_713_DATA*/ ++ 0x00000000 /*DENALI_PHY_714_DATA*/ ++ 0x00000000 /*DENALI_PHY_715_DATA*/ ++ 0x00000000 /*DENALI_PHY_716_DATA*/ ++ 0x00000000 /*DENALI_PHY_717_DATA*/ ++ 0x00000000 /*DENALI_PHY_718_DATA*/ ++ 0x00000000 /*DENALI_PHY_719_DATA*/ ++ 0x00000000 /*DENALI_PHY_720_DATA*/ ++ 0x00000000 /*DENALI_PHY_721_DATA*/ ++ 0x00000000 /*DENALI_PHY_722_DATA*/ ++ 0x00000000 /*DENALI_PHY_723_DATA*/ ++ 0x00000000 /*DENALI_PHY_724_DATA*/ ++ 0x00000000 /*DENALI_PHY_725_DATA*/ ++ 0x00000000 /*DENALI_PHY_726_DATA*/ ++ 0x00000000 /*DENALI_PHY_727_DATA*/ ++ 0x00000000 /*DENALI_PHY_728_DATA*/ ++ 0x00000000 /*DENALI_PHY_729_DATA*/ ++ 0x00000000 /*DENALI_PHY_730_DATA*/ ++ 0x00000000 /*DENALI_PHY_731_DATA*/ ++ 0x00000000 /*DENALI_PHY_732_DATA*/ ++ 0x00000000 /*DENALI_PHY_733_DATA*/ ++ 0x00000000 /*DENALI_PHY_734_DATA*/ ++ 0x00000000 /*DENALI_PHY_735_DATA*/ ++ 0x00000000 /*DENALI_PHY_736_DATA*/ ++ 0x00000000 /*DENALI_PHY_737_DATA*/ ++ 0x00000000 /*DENALI_PHY_738_DATA*/ ++ 0x00000000 /*DENALI_PHY_739_DATA*/ ++ 0x00000000 /*DENALI_PHY_740_DATA*/ ++ 0x00000000 /*DENALI_PHY_741_DATA*/ ++ 0x00000000 /*DENALI_PHY_742_DATA*/ ++ 0x00000000 /*DENALI_PHY_743_DATA*/ ++ 0x00000000 /*DENALI_PHY_744_DATA*/ ++ 0x00000000 /*DENALI_PHY_745_DATA*/ ++ 0x00000000 /*DENALI_PHY_746_DATA*/ ++ 0x00000000 /*DENALI_PHY_747_DATA*/ ++ 0x00000000 /*DENALI_PHY_748_DATA*/ ++ 0x00000000 /*DENALI_PHY_749_DATA*/ ++ 0x00000000 /*DENALI_PHY_750_DATA*/ ++ 0x00000000 /*DENALI_PHY_751_DATA*/ ++ 0x00000000 /*DENALI_PHY_752_DATA*/ ++ 0x00000000 /*DENALI_PHY_753_DATA*/ ++ 0x00000000 /*DENALI_PHY_754_DATA*/ ++ 0x00000000 /*DENALI_PHY_755_DATA*/ ++ 0x00000000 /*DENALI_PHY_756_DATA*/ ++ 0x00000000 /*DENALI_PHY_757_DATA*/ ++ 0x00000000 /*DENALI_PHY_758_DATA*/ ++ 0x00000000 /*DENALI_PHY_759_DATA*/ ++ 0x00000000 /*DENALI_PHY_760_DATA*/ ++ 0x00000000 /*DENALI_PHY_761_DATA*/ ++ 0x00000000 /*DENALI_PHY_762_DATA*/ ++ 0x00000000 /*DENALI_PHY_763_DATA*/ ++ 0x00000000 /*DENALI_PHY_764_DATA*/ ++ 0x00000000 /*DENALI_PHY_765_DATA*/ ++ 0x00000000 /*DENALI_PHY_766_DATA*/ ++ 0x00000000 /*DENALI_PHY_767_DATA*/ ++ 0x10526347 /*DENALI_PHY_768_DATA*/ ++ 0x0004c008 /*DENALI_PHY_769_DATA*/ ++ 0x000000da /*DENALI_PHY_770_DATA*/ ++ 0x00000000 /*DENALI_PHY_771_DATA*/ ++ 0x00000000 /*DENALI_PHY_772_DATA*/ ++ 0x00010000 /*DENALI_PHY_773_DATA*/ ++ 0x01DDDD90 /*DENALI_PHY_774_DATA*/ ++ 0x01DDDD90 /*DENALI_PHY_775_DATA*/ ++ 0x01030001 /*DENALI_PHY_776_DATA*/ ++ 0x01000000 /*DENALI_PHY_777_DATA*/ ++ 0x00c00000 /*DENALI_PHY_778_DATA*/ ++ 0x00000007 /*DENALI_PHY_779_DATA*/ ++ 0x00000000 /*DENALI_PHY_780_DATA*/ ++ 0x00000000 /*DENALI_PHY_781_DATA*/ ++ 0x04000408 /*DENALI_PHY_782_DATA*/ ++ 0x00000408 /*DENALI_PHY_783_DATA*/ ++ 0x00e4e400 /*DENALI_PHY_784_DATA*/ ++ 0x00000000 /*DENALI_PHY_785_DATA*/ ++ 0x00000000 /*DENALI_PHY_786_DATA*/ ++ 0x00000000 /*DENALI_PHY_787_DATA*/ ++ 0x00000000 /*DENALI_PHY_788_DATA*/ ++ 0x00000000 /*DENALI_PHY_789_DATA*/ ++ 0x00000000 /*DENALI_PHY_790_DATA*/ ++ 0x00000000 /*DENALI_PHY_791_DATA*/ ++ 0x00000000 /*DENALI_PHY_792_DATA*/ ++ 0x00000000 /*DENALI_PHY_793_DATA*/ ++ 0x00000000 /*DENALI_PHY_794_DATA*/ ++ 0x00000000 /*DENALI_PHY_795_DATA*/ ++ 0x00000000 /*DENALI_PHY_796_DATA*/ ++ 0x00000000 /*DENALI_PHY_797_DATA*/ ++ 0x00000000 /*DENALI_PHY_798_DATA*/ ++ 0x00000000 /*DENALI_PHY_799_DATA*/ ++ 0x00000000 /*DENALI_PHY_800_DATA*/ ++ 0x00200000 /*DENALI_PHY_801_DATA*/ ++ 0x00000000 /*DENALI_PHY_802_DATA*/ ++ 0x00000000 /*DENALI_PHY_803_DATA*/ ++ 0x00000000 /*DENALI_PHY_804_DATA*/ ++ 0x00000000 /*DENALI_PHY_805_DATA*/ ++ 0x00000000 /*DENALI_PHY_806_DATA*/ ++ 0x00000000 /*DENALI_PHY_807_DATA*/ ++ 0x02800280 /*DENALI_PHY_808_DATA*/ ++ 0x02800280 /*DENALI_PHY_809_DATA*/ ++ 0x02800280 /*DENALI_PHY_810_DATA*/ ++ 0x02800280 /*DENALI_PHY_811_DATA*/ ++ 0x00000280 /*DENALI_PHY_812_DATA*/ ++ 0x00000000 /*DENALI_PHY_813_DATA*/ ++ 0x00000000 /*DENALI_PHY_814_DATA*/ ++ 0x00000000 /*DENALI_PHY_815_DATA*/ ++ 0x00000000 /*DENALI_PHY_816_DATA*/ ++ 0x00000000 /*DENALI_PHY_817_DATA*/ ++ 0x00800080 /*DENALI_PHY_818_DATA*/ ++ 0x00800080 /*DENALI_PHY_819_DATA*/ ++ 0x00800080 /*DENALI_PHY_820_DATA*/ ++ 0x00800080 /*DENALI_PHY_821_DATA*/ ++ 0x00800080 /*DENALI_PHY_822_DATA*/ ++ 0x00800080 /*DENALI_PHY_823_DATA*/ ++ 0x00800080 /*DENALI_PHY_824_DATA*/ ++ 0x00800080 /*DENALI_PHY_825_DATA*/ ++ 0x00800080 /*DENALI_PHY_826_DATA*/ ++ 0x000100da /*DENALI_PHY_827_DATA*/ ++ 0x01ff0010 /*DENALI_PHY_828_DATA*/ ++ 0x00000000 /*DENALI_PHY_829_DATA*/ ++ 0x00000000 /*DENALI_PHY_830_DATA*/ ++ 0x00000002 /*DENALI_PHY_831_DATA*/ ++ 0x51313152 /*DENALI_PHY_832_DATA*/ ++ 0x80013130 /*DENALI_PHY_833_DATA*/ ++ 0x02000080 /*DENALI_PHY_834_DATA*/ ++ 0x00100001 /*DENALI_PHY_835_DATA*/ ++ 0x0c064208 /*DENALI_PHY_836_DATA*/ ++ 0x000f0c0f /*DENALI_PHY_837_DATA*/ ++ 0x01000140 /*DENALI_PHY_838_DATA*/ ++ 0x0000000c /*DENALI_PHY_839_DATA*/ ++ 0x00000000 /*DENALI_PHY_840_DATA*/ ++ 0x00000000 /*DENALI_PHY_841_DATA*/ ++ 0x00000000 /*DENALI_PHY_842_DATA*/ ++ 0x00000000 /*DENALI_PHY_843_DATA*/ ++ 0x00000000 /*DENALI_PHY_844_DATA*/ ++ 0x00000000 /*DENALI_PHY_845_DATA*/ ++ 0x00000000 /*DENALI_PHY_846_DATA*/ ++ 0x00000000 /*DENALI_PHY_847_DATA*/ ++ 0x00000000 /*DENALI_PHY_848_DATA*/ ++ 0x00000000 /*DENALI_PHY_849_DATA*/ ++ 0x00000000 /*DENALI_PHY_850_DATA*/ ++ 0x00000000 /*DENALI_PHY_851_DATA*/ ++ 0x00000000 /*DENALI_PHY_852_DATA*/ ++ 0x00000000 /*DENALI_PHY_853_DATA*/ ++ 0x00000000 /*DENALI_PHY_854_DATA*/ ++ 0x00000000 /*DENALI_PHY_855_DATA*/ ++ 0x00000000 /*DENALI_PHY_856_DATA*/ ++ 0x00000000 /*DENALI_PHY_857_DATA*/ ++ 0x00000000 /*DENALI_PHY_858_DATA*/ ++ 0x00000000 /*DENALI_PHY_859_DATA*/ ++ 0x00000000 /*DENALI_PHY_860_DATA*/ ++ 0x00000000 /*DENALI_PHY_861_DATA*/ ++ 0x00000000 /*DENALI_PHY_862_DATA*/ ++ 0x00000000 /*DENALI_PHY_863_DATA*/ ++ 0x00000000 /*DENALI_PHY_864_DATA*/ ++ 0x00000000 /*DENALI_PHY_865_DATA*/ ++ 0x00000000 /*DENALI_PHY_866_DATA*/ ++ 0x00000000 /*DENALI_PHY_867_DATA*/ ++ 0x00000000 /*DENALI_PHY_868_DATA*/ ++ 0x00000000 /*DENALI_PHY_869_DATA*/ ++ 0x00000000 /*DENALI_PHY_870_DATA*/ ++ 0x00000000 /*DENALI_PHY_871_DATA*/ ++ 0x00000000 /*DENALI_PHY_872_DATA*/ ++ 0x00000000 /*DENALI_PHY_873_DATA*/ ++ 0x00000000 /*DENALI_PHY_874_DATA*/ ++ 0x00000000 /*DENALI_PHY_875_DATA*/ ++ 0x00000000 /*DENALI_PHY_876_DATA*/ ++ 0x00000000 /*DENALI_PHY_877_DATA*/ ++ 0x00000000 /*DENALI_PHY_878_DATA*/ ++ 0x00000000 /*DENALI_PHY_879_DATA*/ ++ 0x00000000 /*DENALI_PHY_880_DATA*/ ++ 0x00000000 /*DENALI_PHY_881_DATA*/ ++ 0x00000000 /*DENALI_PHY_882_DATA*/ ++ 0x00000000 /*DENALI_PHY_883_DATA*/ ++ 0x00000000 /*DENALI_PHY_884_DATA*/ ++ 0x00000000 /*DENALI_PHY_885_DATA*/ ++ 0x00000000 /*DENALI_PHY_886_DATA*/ ++ 0x00000000 /*DENALI_PHY_887_DATA*/ ++ 0x00000000 /*DENALI_PHY_888_DATA*/ ++ 0x00000000 /*DENALI_PHY_889_DATA*/ ++ 0x00000000 /*DENALI_PHY_890_DATA*/ ++ 0x00000000 /*DENALI_PHY_891_DATA*/ ++ 0x00000000 /*DENALI_PHY_892_DATA*/ ++ 0x00000000 /*DENALI_PHY_893_DATA*/ ++ 0x00000000 /*DENALI_PHY_894_DATA*/ ++ 0x00000000 /*DENALI_PHY_895_DATA*/ ++ 0x41753260 /*DENALI_PHY_896_DATA*/ ++ 0x0004c008 /*DENALI_PHY_897_DATA*/ ++ 0x000000da /*DENALI_PHY_898_DATA*/ ++ 0x00000000 /*DENALI_PHY_899_DATA*/ ++ 0x00000000 /*DENALI_PHY_900_DATA*/ ++ 0x00010000 /*DENALI_PHY_901_DATA*/ ++ 0x01DDDD90 /*DENALI_PHY_902_DATA*/ ++ 0x01DDDD90 /*DENALI_PHY_903_DATA*/ ++ 0x01030001 /*DENALI_PHY_904_DATA*/ ++ 0x01000000 /*DENALI_PHY_905_DATA*/ ++ 0x00c00000 /*DENALI_PHY_906_DATA*/ ++ 0x00000007 /*DENALI_PHY_907_DATA*/ ++ 0x00000000 /*DENALI_PHY_908_DATA*/ ++ 0x00000000 /*DENALI_PHY_909_DATA*/ ++ 0x04000408 /*DENALI_PHY_910_DATA*/ ++ 0x00000408 /*DENALI_PHY_911_DATA*/ ++ 0x00e4e400 /*DENALI_PHY_912_DATA*/ ++ 0x00000000 /*DENALI_PHY_913_DATA*/ ++ 0x00000000 /*DENALI_PHY_914_DATA*/ ++ 0x00000000 /*DENALI_PHY_915_DATA*/ ++ 0x00000000 /*DENALI_PHY_916_DATA*/ ++ 0x00000000 /*DENALI_PHY_917_DATA*/ ++ 0x00000000 /*DENALI_PHY_918_DATA*/ ++ 0x00000000 /*DENALI_PHY_919_DATA*/ ++ 0x00000000 /*DENALI_PHY_920_DATA*/ ++ 0x00000000 /*DENALI_PHY_921_DATA*/ ++ 0x00000000 /*DENALI_PHY_922_DATA*/ ++ 0x00000000 /*DENALI_PHY_923_DATA*/ ++ 0x00000000 /*DENALI_PHY_924_DATA*/ ++ 0x00000000 /*DENALI_PHY_925_DATA*/ ++ 0x00000000 /*DENALI_PHY_926_DATA*/ ++ 0x00000000 /*DENALI_PHY_927_DATA*/ ++ 0x00000000 /*DENALI_PHY_928_DATA*/ ++ 0x00200000 /*DENALI_PHY_929_DATA*/ ++ 0x00000000 /*DENALI_PHY_930_DATA*/ ++ 0x00000000 /*DENALI_PHY_931_DATA*/ ++ 0x00000000 /*DENALI_PHY_932_DATA*/ ++ 0x00000000 /*DENALI_PHY_933_DATA*/ ++ 0x00000000 /*DENALI_PHY_934_DATA*/ ++ 0x00000000 /*DENALI_PHY_935_DATA*/ ++ 0x02800280 /*DENALI_PHY_936_DATA*/ ++ 0x02800280 /*DENALI_PHY_937_DATA*/ ++ 0x02800280 /*DENALI_PHY_938_DATA*/ ++ 0x02800280 /*DENALI_PHY_939_DATA*/ ++ 0x00000280 /*DENALI_PHY_940_DATA*/ ++ 0x00000000 /*DENALI_PHY_941_DATA*/ ++ 0x00000000 /*DENALI_PHY_942_DATA*/ ++ 0x00000000 /*DENALI_PHY_943_DATA*/ ++ 0x00000000 /*DENALI_PHY_944_DATA*/ ++ 0x00000000 /*DENALI_PHY_945_DATA*/ ++ 0x00800080 /*DENALI_PHY_946_DATA*/ ++ 0x00800080 /*DENALI_PHY_947_DATA*/ ++ 0x00800080 /*DENALI_PHY_948_DATA*/ ++ 0x00800080 /*DENALI_PHY_949_DATA*/ ++ 0x00800080 /*DENALI_PHY_950_DATA*/ ++ 0x00800080 /*DENALI_PHY_951_DATA*/ ++ 0x00800080 /*DENALI_PHY_952_DATA*/ ++ 0x00800080 /*DENALI_PHY_953_DATA*/ ++ 0x00800080 /*DENALI_PHY_954_DATA*/ ++ 0x000100da /*DENALI_PHY_955_DATA*/ ++ 0x01ff0010 /*DENALI_PHY_956_DATA*/ ++ 0x00000000 /*DENALI_PHY_957_DATA*/ ++ 0x00000000 /*DENALI_PHY_958_DATA*/ ++ 0x00000002 /*DENALI_PHY_959_DATA*/ ++ 0x51313152 /*DENALI_PHY_960_DATA*/ ++ 0x80013130 /*DENALI_PHY_961_DATA*/ ++ 0x02000080 /*DENALI_PHY_962_DATA*/ ++ 0x00100001 /*DENALI_PHY_963_DATA*/ ++ 0x0c064208 /*DENALI_PHY_964_DATA*/ ++ 0x000f0c0f /*DENALI_PHY_965_DATA*/ ++ 0x01000140 /*DENALI_PHY_966_DATA*/ ++ 0x0000000c /*DENALI_PHY_967_DATA*/ ++ 0x00000000 /*DENALI_PHY_968_DATA*/ ++ 0x00000000 /*DENALI_PHY_969_DATA*/ ++ 0x00000000 /*DENALI_PHY_970_DATA*/ ++ 0x00000000 /*DENALI_PHY_971_DATA*/ ++ 0x00000000 /*DENALI_PHY_972_DATA*/ ++ 0x00000000 /*DENALI_PHY_973_DATA*/ ++ 0x00000000 /*DENALI_PHY_974_DATA*/ ++ 0x00000000 /*DENALI_PHY_975_DATA*/ ++ 0x00000000 /*DENALI_PHY_976_DATA*/ ++ 0x00000000 /*DENALI_PHY_977_DATA*/ ++ 0x00000000 /*DENALI_PHY_978_DATA*/ ++ 0x00000000 /*DENALI_PHY_979_DATA*/ ++ 0x00000000 /*DENALI_PHY_980_DATA*/ ++ 0x00000000 /*DENALI_PHY_981_DATA*/ ++ 0x00000000 /*DENALI_PHY_982_DATA*/ ++ 0x00000000 /*DENALI_PHY_983_DATA*/ ++ 0x00000000 /*DENALI_PHY_984_DATA*/ ++ 0x00000000 /*DENALI_PHY_985_DATA*/ ++ 0x00000000 /*DENALI_PHY_986_DATA*/ ++ 0x00000000 /*DENALI_PHY_987_DATA*/ ++ 0x00000000 /*DENALI_PHY_988_DATA*/ ++ 0x00000000 /*DENALI_PHY_989_DATA*/ ++ 0x00000000 /*DENALI_PHY_990_DATA*/ ++ 0x00000000 /*DENALI_PHY_991_DATA*/ ++ 0x00000000 /*DENALI_PHY_992_DATA*/ ++ 0x00000000 /*DENALI_PHY_993_DATA*/ ++ 0x00000000 /*DENALI_PHY_994_DATA*/ ++ 0x00000000 /*DENALI_PHY_995_DATA*/ ++ 0x00000000 /*DENALI_PHY_996_DATA*/ ++ 0x00000000 /*DENALI_PHY_997_DATA*/ ++ 0x00000000 /*DENALI_PHY_998_DATA*/ ++ 0x00000000 /*DENALI_PHY_999_DATA*/ ++ 0x00000000 /*DENALI_PHY_1000_DATA*/ ++ 0x00000000 /*DENALI_PHY_1001_DATA*/ ++ 0x00000000 /*DENALI_PHY_1002_DATA*/ ++ 0x00000000 /*DENALI_PHY_1003_DATA*/ ++ 0x00000000 /*DENALI_PHY_1004_DATA*/ ++ 0x00000000 /*DENALI_PHY_1005_DATA*/ ++ 0x00000000 /*DENALI_PHY_1006_DATA*/ ++ 0x00000000 /*DENALI_PHY_1007_DATA*/ ++ 0x00000000 /*DENALI_PHY_1008_DATA*/ ++ 0x00000000 /*DENALI_PHY_1009_DATA*/ ++ 0x00000000 /*DENALI_PHY_1010_DATA*/ ++ 0x00000000 /*DENALI_PHY_1011_DATA*/ ++ 0x00000000 /*DENALI_PHY_1012_DATA*/ ++ 0x00000000 /*DENALI_PHY_1013_DATA*/ ++ 0x00000000 /*DENALI_PHY_1014_DATA*/ ++ 0x00000000 /*DENALI_PHY_1015_DATA*/ ++ 0x00000000 /*DENALI_PHY_1016_DATA*/ ++ 0x00000000 /*DENALI_PHY_1017_DATA*/ ++ 0x00000000 /*DENALI_PHY_1018_DATA*/ ++ 0x00000000 /*DENALI_PHY_1019_DATA*/ ++ 0x00000000 /*DENALI_PHY_1020_DATA*/ ++ 0x00000000 /*DENALI_PHY_1021_DATA*/ ++ 0x00000000 /*DENALI_PHY_1022_DATA*/ ++ 0x00000000 /*DENALI_PHY_1023_DATA*/ ++ 0x76543210 /*DENALI_PHY_1024_DATA*/ ++ 0x0004c008 /*DENALI_PHY_1025_DATA*/ ++ 0x000000da /*DENALI_PHY_1026_DATA*/ ++ 0x00000000 /*DENALI_PHY_1027_DATA*/ ++ 0x00000000 /*DENALI_PHY_1028_DATA*/ ++ 0x00010000 /*DENALI_PHY_1029_DATA*/ ++ 0x01665555 /*DENALI_PHY_1030_DATA*/ ++ 0x01665555 /*DENALI_PHY_1031_DATA*/ ++ 0x01030001 /*DENALI_PHY_1032_DATA*/ ++ 0x01000000 /*DENALI_PHY_1033_DATA*/ ++ 0x00c00000 /*DENALI_PHY_1034_DATA*/ ++ 0x00000007 /*DENALI_PHY_1035_DATA*/ ++ 0x00000000 /*DENALI_PHY_1036_DATA*/ ++ 0x00000000 /*DENALI_PHY_1037_DATA*/ ++ 0x04000408 /*DENALI_PHY_1038_DATA*/ ++ 0x00000408 /*DENALI_PHY_1039_DATA*/ ++ 0x00e4e400 /*DENALI_PHY_1040_DATA*/ ++ 0x00000000 /*DENALI_PHY_1041_DATA*/ ++ 0x00000000 /*DENALI_PHY_1042_DATA*/ ++ 0x00000000 /*DENALI_PHY_1043_DATA*/ ++ 0x00000000 /*DENALI_PHY_1044_DATA*/ ++ 0x00000000 /*DENALI_PHY_1045_DATA*/ ++ 0x00000000 /*DENALI_PHY_1046_DATA*/ ++ 0x00000000 /*DENALI_PHY_1047_DATA*/ ++ 0x00000000 /*DENALI_PHY_1048_DATA*/ ++ 0x00000000 /*DENALI_PHY_1049_DATA*/ ++ 0x00000000 /*DENALI_PHY_1050_DATA*/ ++ 0x00000000 /*DENALI_PHY_1051_DATA*/ ++ 0x00000000 /*DENALI_PHY_1052_DATA*/ ++ 0x00000000 /*DENALI_PHY_1053_DATA*/ ++ 0x00000000 /*DENALI_PHY_1054_DATA*/ ++ 0x00000000 /*DENALI_PHY_1055_DATA*/ ++ 0x00000000 /*DENALI_PHY_1056_DATA*/ ++ 0x00200000 /*DENALI_PHY_1057_DATA*/ ++ 0x00000000 /*DENALI_PHY_1058_DATA*/ ++ 0x00000000 /*DENALI_PHY_1059_DATA*/ ++ 0x00000000 /*DENALI_PHY_1060_DATA*/ ++ 0x00000000 /*DENALI_PHY_1061_DATA*/ ++ 0x00000000 /*DENALI_PHY_1062_DATA*/ ++ 0x00000000 /*DENALI_PHY_1063_DATA*/ ++ 0x02800280 /*DENALI_PHY_1064_DATA*/ ++ 0x02800280 /*DENALI_PHY_1065_DATA*/ ++ 0x02800280 /*DENALI_PHY_1066_DATA*/ ++ 0x02800280 /*DENALI_PHY_1067_DATA*/ ++ 0x00000280 /*DENALI_PHY_1068_DATA*/ ++ 0x00000000 /*DENALI_PHY_1069_DATA*/ ++ 0x00000000 /*DENALI_PHY_1070_DATA*/ ++ 0x00000000 /*DENALI_PHY_1071_DATA*/ ++ 0x00000000 /*DENALI_PHY_1072_DATA*/ ++ 0x00000000 /*DENALI_PHY_1073_DATA*/ ++ 0x00800080 /*DENALI_PHY_1074_DATA*/ ++ 0x00800080 /*DENALI_PHY_1075_DATA*/ ++ 0x00800080 /*DENALI_PHY_1076_DATA*/ ++ 0x00800080 /*DENALI_PHY_1077_DATA*/ ++ 0x00800080 /*DENALI_PHY_1078_DATA*/ ++ 0x00800080 /*DENALI_PHY_1079_DATA*/ ++ 0x00800080 /*DENALI_PHY_1080_DATA*/ ++ 0x00800080 /*DENALI_PHY_1081_DATA*/ ++ 0x00800080 /*DENALI_PHY_1082_DATA*/ ++ 0x000100da /*DENALI_PHY_1083_DATA*/ ++ 0x01ff0010 /*DENALI_PHY_1084_DATA*/ ++ 0x00000000 /*DENALI_PHY_1085_DATA*/ ++ 0x00000000 /*DENALI_PHY_1086_DATA*/ ++ 0x00000002 /*DENALI_PHY_1087_DATA*/ ++ 0x51313152 /*DENALI_PHY_1088_DATA*/ ++ 0x80013130 /*DENALI_PHY_1089_DATA*/ ++ 0x02000080 /*DENALI_PHY_1090_DATA*/ ++ 0x00100001 /*DENALI_PHY_1091_DATA*/ ++ 0x0c064208 /*DENALI_PHY_1092_DATA*/ ++ 0x000f0c0f /*DENALI_PHY_1093_DATA*/ ++ 0x01000140 /*DENALI_PHY_1094_DATA*/ ++ 0x0000000c /*DENALI_PHY_1095_DATA*/ ++ 0x00000000 /*DENALI_PHY_1096_DATA*/ ++ 0x00000000 /*DENALI_PHY_1097_DATA*/ ++ 0x00000000 /*DENALI_PHY_1098_DATA*/ ++ 0x00000000 /*DENALI_PHY_1099_DATA*/ ++ 0x00000000 /*DENALI_PHY_1100_DATA*/ ++ 0x00000000 /*DENALI_PHY_1101_DATA*/ ++ 0x00000000 /*DENALI_PHY_1102_DATA*/ ++ 0x00000000 /*DENALI_PHY_1103_DATA*/ ++ 0x00000000 /*DENALI_PHY_1104_DATA*/ ++ 0x00000000 /*DENALI_PHY_1105_DATA*/ ++ 0x00000000 /*DENALI_PHY_1106_DATA*/ ++ 0x00000000 /*DENALI_PHY_1107_DATA*/ ++ 0x00000000 /*DENALI_PHY_1108_DATA*/ ++ 0x00000000 /*DENALI_PHY_1109_DATA*/ ++ 0x00000000 /*DENALI_PHY_1110_DATA*/ ++ 0x00000000 /*DENALI_PHY_1111_DATA*/ ++ 0x00000000 /*DENALI_PHY_1112_DATA*/ ++ 0x00000000 /*DENALI_PHY_1113_DATA*/ ++ 0x00000000 /*DENALI_PHY_1114_DATA*/ ++ 0x00000000 /*DENALI_PHY_1115_DATA*/ ++ 0x00000000 /*DENALI_PHY_1116_DATA*/ ++ 0x00000000 /*DENALI_PHY_1117_DATA*/ ++ 0x00000000 /*DENALI_PHY_1118_DATA*/ ++ 0x00000000 /*DENALI_PHY_1119_DATA*/ ++ 0x00000000 /*DENALI_PHY_1120_DATA*/ ++ 0x00000000 /*DENALI_PHY_1121_DATA*/ ++ 0x00000000 /*DENALI_PHY_1122_DATA*/ ++ 0x00000000 /*DENALI_PHY_1123_DATA*/ ++ 0x00000000 /*DENALI_PHY_1124_DATA*/ ++ 0x00000000 /*DENALI_PHY_1125_DATA*/ ++ 0x00000000 /*DENALI_PHY_1126_DATA*/ ++ 0x00000000 /*DENALI_PHY_1127_DATA*/ ++ 0x00000000 /*DENALI_PHY_1128_DATA*/ ++ 0x00000000 /*DENALI_PHY_1129_DATA*/ ++ 0x00000000 /*DENALI_PHY_1130_DATA*/ ++ 0x00000000 /*DENALI_PHY_1131_DATA*/ ++ 0x00000000 /*DENALI_PHY_1132_DATA*/ ++ 0x00000000 /*DENALI_PHY_1133_DATA*/ ++ 0x00000000 /*DENALI_PHY_1134_DATA*/ ++ 0x00000000 /*DENALI_PHY_1135_DATA*/ ++ 0x00000000 /*DENALI_PHY_1136_DATA*/ ++ 0x00000000 /*DENALI_PHY_1137_DATA*/ ++ 0x00000000 /*DENALI_PHY_1138_DATA*/ ++ 0x00000000 /*DENALI_PHY_1139_DATA*/ ++ 0x00000000 /*DENALI_PHY_1140_DATA*/ ++ 0x00000000 /*DENALI_PHY_1141_DATA*/ ++ 0x00000000 /*DENALI_PHY_1142_DATA*/ ++ 0x00000000 /*DENALI_PHY_1143_DATA*/ ++ 0x00000000 /*DENALI_PHY_1144_DATA*/ ++ 0x00000000 /*DENALI_PHY_1145_DATA*/ ++ 0x00000000 /*DENALI_PHY_1146_DATA*/ ++ 0x00000000 /*DENALI_PHY_1147_DATA*/ ++ 0x00000000 /*DENALI_PHY_1148_DATA*/ ++ 0x00000000 /*DENALI_PHY_1149_DATA*/ ++ 0x00000000 /*DENALI_PHY_1150_DATA*/ ++ 0x00000000 /*DENALI_PHY_1151_DATA*/ ++ 0x00000000 /*DENALI_PHY_1152_DATA*/ ++ 0x00000000 /*DENALI_PHY_1153_DATA*/ ++ 0x00050000 /*DENALI_PHY_1154_DATA*/ ++ 0x00000000 /*DENALI_PHY_1155_DATA*/ ++ 0x00000000 /*DENALI_PHY_1156_DATA*/ ++ 0x00000000 /*DENALI_PHY_1157_DATA*/ ++ 0x00000100 /*DENALI_PHY_1158_DATA*/ ++ 0x00000000 /*DENALI_PHY_1159_DATA*/ ++ 0x00000000 /*DENALI_PHY_1160_DATA*/ ++ 0x00506401 /*DENALI_PHY_1161_DATA*/ ++ 0x01221102 /*DENALI_PHY_1162_DATA*/ ++ 0x00000122 /*DENALI_PHY_1163_DATA*/ ++ 0x00000000 /*DENALI_PHY_1164_DATA*/ ++ 0x000B1F00 /*DENALI_PHY_1165_DATA*/ ++ 0x0B1F0B1F /*DENALI_PHY_1166_DATA*/ ++ 0x0B1F0B1F /*DENALI_PHY_1167_DATA*/ ++ 0x0B1F0B1F /*DENALI_PHY_1168_DATA*/ ++ 0x0B1F0B1F /*DENALI_PHY_1169_DATA*/ ++ 0x00000B00 /*DENALI_PHY_1170_DATA*/ ++ 0x42080010 /*DENALI_PHY_1171_DATA*/ ++ 0x01000100 /*DENALI_PHY_1172_DATA*/ ++ 0x01000100 /*DENALI_PHY_1173_DATA*/ ++ 0x01000100 /*DENALI_PHY_1174_DATA*/ ++ 0x01000100 /*DENALI_PHY_1175_DATA*/ ++ 0x00000000 /*DENALI_PHY_1176_DATA*/ ++ 0x00000000 /*DENALI_PHY_1177_DATA*/ ++ 0x00000000 /*DENALI_PHY_1178_DATA*/ ++ 0x00000000 /*DENALI_PHY_1179_DATA*/ ++ 0x00000000 /*DENALI_PHY_1180_DATA*/ ++ 0x00000803 /*DENALI_PHY_1181_DATA*/ ++ 0x223FFF00 /*DENALI_PHY_1182_DATA*/ ++ 0x000008FF /*DENALI_PHY_1183_DATA*/ ++ 0x0000057F /*DENALI_PHY_1184_DATA*/ ++ 0x0000057F /*DENALI_PHY_1185_DATA*/ ++ 0x00037FFF /*DENALI_PHY_1186_DATA*/ ++ 0x00037FFF /*DENALI_PHY_1187_DATA*/ ++ 0x00004410 /*DENALI_PHY_1188_DATA*/ ++ 0x00004410 /*DENALI_PHY_1189_DATA*/ ++ 0x00004410 /*DENALI_PHY_1190_DATA*/ ++ 0x00004410 /*DENALI_PHY_1191_DATA*/ ++ 0x00004410 /*DENALI_PHY_1192_DATA*/ ++ 0x00000111 /*DENALI_PHY_1193_DATA*/ ++ 0x00000111 /*DENALI_PHY_1194_DATA*/ ++ 0x00000000 /*DENALI_PHY_1195_DATA*/ ++ 0x00000000 /*DENALI_PHY_1196_DATA*/ ++ 0x00000000 /*DENALI_PHY_1197_DATA*/ ++ 0x04000000 /*DENALI_PHY_1198_DATA*/ ++ 0x00000000 /*DENALI_PHY_1199_DATA*/ ++ 0x00000000 /*DENALI_PHY_1200_DATA*/ ++ 0x00000108 /*DENALI_PHY_1201_DATA*/ ++ 0x00000000 /*DENALI_PHY_1202_DATA*/ ++ 0x00000000 /*DENALI_PHY_1203_DATA*/ ++ 0x00000000 /*DENALI_PHY_1204_DATA*/ ++ 0x00000001 /*DENALI_PHY_1205_DATA*/ ++ 0x00000000 /*DENALI_PHY_1206_DATA*/ ++ 0x00000000 /*DENALI_PHY_1207_DATA*/ ++ 0x00000000 /*DENALI_PHY_1208_DATA*/ ++ 0x00000000 /*DENALI_PHY_1209_DATA*/ ++ 0x00000000 /*DENALI_PHY_1210_DATA*/ ++ 0x00000000 /*DENALI_PHY_1211_DATA*/ ++ 0x00020100 /*DENALI_PHY_1212_DATA*/ ++ 0x00000000 /*DENALI_PHY_1213_DATA*/ ++ 0x00000000 /*DENALI_PHY_1214_DATA*/ + >; + }; +diff --git a/arch/riscv/dts/hifive-unmatched-a00.dts b/arch/riscv/dts/hifive-unmatched-a00.dts +index 6588512..c2f9bf0 100644 +--- a/arch/riscv/dts/hifive-unmatched-a00.dts ++++ b/arch/riscv/dts/hifive-unmatched-a00.dts +@@ -1,5 +1,5 @@ + // SPDX-License-Identifier: (GPL-2.0 OR MIT) +-/* Copyright (c) 2019 SiFive, Inc */ ++/* Copyright (c) 2020-2021 SiFive, Inc */ + + #include "fu740-c000.dtsi" + #include +@@ -24,7 +24,7 @@ + + memory@80000000 { + device_type = "memory"; +- reg = <0x0 0x80000000 0x2 0x00000000>; ++ reg = <0x0 0x80000000 0x4 0x00000000>; + }; + + soc { +@@ -72,16 +72,16 @@ + + regulators { + vdd_bcore1: bcore1 { +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; ++ regulator-min-microvolt = <1050000>; ++ regulator-max-microvolt = <1050000>; + regulator-min-microamp = <5000000>; + regulator-max-microamp = <5000000>; + regulator-always-on; + }; + + vdd_bcore2: bcore2 { +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; ++ regulator-min-microvolt = <1050000>; ++ regulator-max-microvolt = <1050000>; + regulator-min-microamp = <5000000>; + regulator-max-microamp = <5000000>; + regulator-always-on; +@@ -136,48 +136,48 @@ + }; + + vdd_ldo3: ldo3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; + regulator-min-microamp = <200000>; + regulator-max-microamp = <200000>; + regulator-always-on; + }; + + vdd_ldo4: ldo4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; ++ regulator-min-microvolt = <2500000>; ++ regulator-max-microvolt = <2500000>; + regulator-min-microamp = <200000>; + regulator-max-microamp = <200000>; + regulator-always-on; + }; + + vdd_ldo5: ldo5 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; + regulator-min-microamp = <100000>; + regulator-max-microamp = <100000>; + regulator-always-on; + }; + + vdd_ldo6: ldo6 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; + regulator-min-microamp = <200000>; + regulator-max-microamp = <200000>; + regulator-always-on; + }; + + vdd_ldo7: ldo7 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; + regulator-min-microamp = <200000>; + regulator-max-microamp = <200000>; + regulator-always-on; + }; + + vdd_ldo8: ldo8 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; + regulator-min-microamp = <200000>; + regulator-max-microamp = <200000>; + regulator-always-on; +-- +2.7.4 + diff -Nru u-boot-2021.01+dfsg/debian/patches/riscv64/0041-Fix-CRC32-checksum-for-SiFive-HiFive-EEPROM.patch u-boot-2021.01+dfsg/debian/patches/riscv64/0041-Fix-CRC32-checksum-for-SiFive-HiFive-EEPROM.patch --- u-boot-2021.01+dfsg/debian/patches/riscv64/0041-Fix-CRC32-checksum-for-SiFive-HiFive-EEPROM.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/riscv64/0041-Fix-CRC32-checksum-for-SiFive-HiFive-EEPROM.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,28 @@ +From c31930f5ab5a7637cb2af7ea56d99b1c262bd993 Mon Sep 17 00:00:00 2001 +From: David Abdurachmanov +Date: Mon, 15 Mar 2021 10:26:40 -0700 +Subject: [PATCH 41/41] Fix CRC32 checksum for SiFive HiFive EEPROM + +Signed-off-by: David Abdurachmanov +--- + board/sifive/hifive_unmatched_fu740/hifive-platform-i2c-eeprom.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/board/sifive/hifive_unmatched_fu740/hifive-platform-i2c-eeprom.c b/board/sifive/hifive_unmatched_fu740/hifive-platform-i2c-eeprom.c +index be7a4fe..851a313 100644 +--- a/board/sifive/hifive_unmatched_fu740/hifive-platform-i2c-eeprom.c ++++ b/board/sifive/hifive_unmatched_fu740/hifive-platform-i2c-eeprom.c +@@ -86,8 +86,8 @@ static const unsigned char magic[MAGIC_NUMBER_BYTES] = { 0xf1, 0x5e, 0x50, + + + static u32 __compute_eeprom_crc(struct sifive_eeprom *eeprom) { +- return crc32(0, (void *)&eeprom, +- sizeof(eeprom) - sizeof(eeprom->crc)); ++ return crc32(0, (void *)eeprom, ++ sizeof(struct sifive_eeprom) - 4); + } + + /* Does the magic number match that of a SiFive EEPROM? */ +-- +2.7.4 + diff -Nru u-boot-2021.01+dfsg/debian/patches/riscv64/qemu-skip-fdtdir.patch u-boot-2021.01+dfsg/debian/patches/riscv64/qemu-skip-fdtdir.patch --- u-boot-2021.01+dfsg/debian/patches/riscv64/qemu-skip-fdtdir.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/riscv64/qemu-skip-fdtdir.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,24 @@ +Description: Skip processing fdtdir on qemu-riscv64_smode target + it crashes the riscv qemu VM. +Author: Dimitri John Ledkov +Bug-Ubuntu: https://bugs.launchpad.net/bugs/1925267 + + +--- u-boot-2021.01+dfsg.orig/cmd/pxe_utils.c ++++ u-boot-2021.01+dfsg/cmd/pxe_utils.c +@@ -471,6 +471,7 @@ static int label_boot(struct cmd_tbl *cm + + if (label->fdt) { + fdtfile = label->fdt; ++#if !(defined(CONFIG_TARGET_QEMU_VIRT) && defined(CONFIG_RISCV_SMODE)) + } else if (label->fdtdir) { + char *f1, *f2, *f3, *f4, *slash; + +@@ -513,6 +514,7 @@ static int label_boot(struct cmd_tbl *cm + snprintf(fdtfilefree, len, "%s%s%s%s%s%s", + label->fdtdir, slash, f1, f2, f3, f4); + fdtfile = fdtfilefree; ++#endif + } + + if (fdtfile) { diff -Nru u-boot-2021.01+dfsg/debian/patches/riscv64/sifive-fu540-compressed-booti-support.patch u-boot-2021.01+dfsg/debian/patches/riscv64/sifive-fu540-compressed-booti-support.patch --- u-boot-2021.01+dfsg/debian/patches/riscv64/sifive-fu540-compressed-booti-support.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/riscv64/sifive-fu540-compressed-booti-support.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,13 @@ +diff --git a/include/configs/sifive-fu540.h b/include/configs/sifive-fu540.h +index c1c79db147..9750381a8c 100644 +--- a/include/configs/sifive-fu540.h ++++ b/include/configs/sifive-fu540.h +@@ -66,6 +66,8 @@ + "script_size_f=0x1000\0" \ + "pxefile_addr_r=0x88200000\0" \ + "ramdisk_addr_r=0x88300000\0" \ ++ "kernel_comp_addr_r=0x90000000\0" \ ++ "kernel_comp_size=0x4000000\0" \ + "type_guid_gpt_loader1=" TYPE_GUID_LOADER1 "\0" \ + "type_guid_gpt_loader2=" TYPE_GUID_LOADER2 "\0" \ + "type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \ diff -Nru u-boot-2021.01+dfsg/debian/patches/riscv64/sifive-unleashed-default-fdt-files.patch u-boot-2021.01+dfsg/debian/patches/riscv64/sifive-unleashed-default-fdt-files.patch --- u-boot-2021.01+dfsg/debian/patches/riscv64/sifive-unleashed-default-fdt-files.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/riscv64/sifive-unleashed-default-fdt-files.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,24 @@ +Description: set default FDT filenames to load from boot disk +Bug: https://github.com/sifive/meta-sifive/issues/16 + +Index: u-boot-2021.01+dfsg/configs/sifive_fu540_defconfig +=================================================================== +--- u-boot-2021.01+dfsg.orig/configs/sifive_fu540_defconfig ++++ u-boot-2021.01+dfsg/configs/sifive_fu540_defconfig +@@ -1,3 +1,4 @@ ++CONFIG_DEFAULT_FDT_FILE="sifive/hifive-unleashed-a00.dtb" + CONFIG_RISCV=y + CONFIG_SPL_GPIO_SUPPORT=y + CONFIG_SYS_MALLOC_F_LEN=0x3000 +Index: u-boot-2021.01+dfsg/include/configs/sifive-fu540.h +=================================================================== +--- u-boot-2021.01+dfsg.orig/include/configs/sifive-fu540.h ++++ u-boot-2021.01+dfsg/include/configs/sifive-fu540.h +@@ -72,6 +72,7 @@ + "type_guid_gpt_loader2=" TYPE_GUID_LOADER2 "\0" \ + "type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \ + "partitions=" PARTS_DEFAULT "\0" \ ++ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + BOOTENV \ + BOOTENV_SF + diff -Nru u-boot-2021.01+dfsg/debian/patches/riscv64/sifive-unmatched-default-fdt-files.patch u-boot-2021.01+dfsg/debian/patches/riscv64/sifive-unmatched-default-fdt-files.patch --- u-boot-2021.01+dfsg/debian/patches/riscv64/sifive-unmatched-default-fdt-files.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/riscv64/sifive-unmatched-default-fdt-files.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,24 @@ +Description: set default FDT filenames to load from boot disk +Bug: https://github.com/sifive/meta-sifive/issues/16 + +Index: u-boot-2021.01+dfsg/configs/sifive_hifive_unmatched_fu740_defconfig +=================================================================== +--- u-boot-2021.01+dfsg.orig/configs/sifive_hifive_unmatched_fu740_defconfig ++++ u-boot-2021.01+dfsg/configs/sifive_hifive_unmatched_fu740_defconfig +@@ -1,3 +1,4 @@ ++CONFIG_DEFAULT_FDT_FILE="sifive/hifive-unmatched-a00.dtb" + CONFIG_RISCV=y + CONFIG_SPL_GPIO_SUPPORT=y + CONFIG_SYS_MALLOC_F_LEN=0x3000 +Index: u-boot-2021.01+dfsg/include/configs/sifive-hifive-unmatched-fu740.h +=================================================================== +--- u-boot-2021.01+dfsg.orig/include/configs/sifive-hifive-unmatched-fu740.h ++++ u-boot-2021.01+dfsg/include/configs/sifive-hifive-unmatched-fu740.h +@@ -84,6 +84,7 @@ + "type_guid_gpt_loader2=" TYPE_GUID_LOADER2 "\0" \ + "type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \ + "partitions=" PARTS_DEFAULT "\0" \ ++ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + BOOTENV + + #define CONFIG_PREBOOT \ diff -Nru u-boot-2021.01+dfsg/debian/patches/riscv64/use-preboot-unmatched.patch u-boot-2021.01+dfsg/debian/patches/riscv64/use-preboot-unmatched.patch --- u-boot-2021.01+dfsg/debian/patches/riscv64/use-preboot-unmatched.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/riscv64/use-preboot-unmatched.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,12 @@ +Index: u-boot-2021.01+dfsg/configs/sifive_hifive_unmatched_fu740_defconfig +=================================================================== +--- u-boot-2021.01+dfsg.orig/configs/sifive_hifive_unmatched_fu740_defconfig ++++ u-boot-2021.01+dfsg/configs/sifive_hifive_unmatched_fu740_defconfig +@@ -22,6 +22,7 @@ CONFIG_SPL_YMODEM_SUPPORT=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_SPL_CLK=y + CONFIG_DM_RESET=y ++CONFIG_USE_PREBOOT=y + CONFIG_CMD_PCI=y + CONFIG_PCI=y + CONFIG_DM_PCI=y diff -Nru u-boot-2021.01+dfsg/debian/patches/rpi-8gb-pci.patch u-boot-2021.01+dfsg/debian/patches/rpi-8gb-pci.patch --- u-boot-2021.01+dfsg/debian/patches/rpi-8gb-pci.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/rpi-8gb-pci.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,34 @@ +Author: Dave Jones +Forwarded: yes +Description: Disable Broadcom PCI driver + The Broadcom PCI driver seems to break u-boot when booting on a Pi 4B with + 8Gb of RAM, when no monitor is attached. This is a brute-force and ignorance + patch and further (upstream) investigation is warranted to discover why this + is the case. Commit 3113c84ba25ec3ceae072cc5ad450c4238425939 (a merge, + annoyingly) is the first bad commit in the u-boot repository when bisecting + this issue. + +Index: u-boot/configs/rpi_4_32b_defconfig +=================================================================== +--- u-boot.orig/configs/rpi_4_32b_defconfig ++++ u-boot/configs/rpi_4_32b_defconfig +@@ -31,7 +31,6 @@ CONFIG_DM_ETH=y + CONFIG_BCMGENET=y + CONFIG_PCI=y + CONFIG_DM_PCI=y +-CONFIG_PCI_BRCMSTB=y + CONFIG_PINCTRL=y + # CONFIG_PINCTRL_GENERIC is not set + CONFIG_DM_RESET=y +Index: u-boot/configs/rpi_4_defconfig +=================================================================== +--- u-boot.orig/configs/rpi_4_defconfig ++++ u-boot/configs/rpi_4_defconfig +@@ -31,7 +31,6 @@ CONFIG_DM_ETH=y + CONFIG_BCMGENET=y + CONFIG_PCI=y + CONFIG_DM_PCI=y +-CONFIG_PCI_BRCMSTB=y + CONFIG_PINCTRL=y + # CONFIG_PINCTRL_GENERIC is not set + CONFIG_DM_RESET=y diff -Nru u-boot-2021.01+dfsg/debian/patches/rpi-board-dt.patch u-boot-2021.01+dfsg/debian/patches/rpi-board-dt.patch --- u-boot-2021.01+dfsg/debian/patches/rpi-board-dt.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/rpi-board-dt.patch 2021-05-13 22:11:00.000000000 +0100 @@ -0,0 +1,37 @@ +Author: Dave Jones +Description: Use the board's device-tree rather than embedded + Our u-boot binaries should accept the device-tree passed by the firmware + rather than use an embedded one. Firstly, the OF_EMBED option is actively + discouraged by u-boot itself, and secondly it allows the same binary to + operate correctly on platforms with differing serial configurations, e.g. the + Pi 3 and Compute Module 3. +--- a/configs/rpi_2_defconfig ++++ b/configs/rpi_2_defconfig +@@ -18,6 +18,7 @@ + CONFIG_CMD_USB=y + CONFIG_CMD_FS_UUID=y + CONFIG_OF_EMBED=y ++CONFIG_OF_BOARD=y + CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +--- a/configs/rpi_3_32b_defconfig ++++ b/configs/rpi_3_32b_defconfig +@@ -19,6 +19,7 @@ + CONFIG_CMD_USB=y + CONFIG_CMD_FS_UUID=y + CONFIG_OF_EMBED=y ++CONFIG_OF_BOARD=y + CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +--- a/configs/rpi_3_defconfig ++++ b/configs/rpi_3_defconfig +@@ -19,6 +19,7 @@ + CONFIG_CMD_USB=y + CONFIG_CMD_FS_UUID=y + CONFIG_OF_EMBED=y ++CONFIG_OF_BOARD=y + CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y diff -Nru u-boot-2021.01+dfsg/debian/patches/rpi-cm4-sdhci.patch u-boot-2021.01+dfsg/debian/patches/rpi-cm4-sdhci.patch --- u-boot-2021.01+dfsg/debian/patches/rpi-cm4-sdhci.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/rpi-cm4-sdhci.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,26 @@ +Author: Dave Jones +Forwarded: yes +Description: Revert commit c6b9fbf7566f84a807a5c116288648085fa529df + This commit adds SDHCI DMA support which works happily with the SD card + interface on the Pi 4, but breaks eMMC support on the CM4 + +--- a/configs/rpi_4_32b_defconfig ++++ b/configs/rpi_4_32b_defconfig +@@ -26,7 +26,6 @@ + CONFIG_DM_KEYBOARD=y + CONFIG_DM_MMC=y + CONFIG_MMC_SDHCI=y +-CONFIG_MMC_SDHCI_SDMA=y + CONFIG_MMC_SDHCI_BCM2835=y + CONFIG_DM_ETH=y + CONFIG_BCMGENET=y +--- a/configs/rpi_4_defconfig ++++ b/configs/rpi_4_defconfig +@@ -26,7 +26,6 @@ + CONFIG_DM_KEYBOARD=y + CONFIG_DM_MMC=y + CONFIG_MMC_SDHCI=y +-CONFIG_MMC_SDHCI_SDMA=y + CONFIG_MMC_SDHCI_BCM2835=y + CONFIG_DM_ETH=y + CONFIG_BCMGENET=y diff -Nru u-boot-2021.01+dfsg/debian/patches/rpi-config-tweaks.patch u-boot-2021.01+dfsg/debian/patches/rpi-config-tweaks.patch --- u-boot-2021.01+dfsg/debian/patches/rpi-config-tweaks.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/rpi-config-tweaks.patch 2021-05-13 22:10:34.000000000 +0100 @@ -0,0 +1,110 @@ +Author: Dave Jones +Description: Configuration adjustments to the RPi2 and RPi3 configs + Based off rpi2-config-tweaks.patch created by Steve Langasek, and + subsequently rpi2-rpi3-config-tweaks.patch created by Łukasz Zemczak, this + ensures that all pi-related configurations are consistent. Specifically that + all support "raw" initrds (used by Core to append the psplash initrd to the + regular one), that all use 128Kb environments (excessive, but several related + code-bases now assume this), and that all use the "redundant" environment + setting (entirely pointlessly but this changes the env header and, again, + several related code-bases now assume this). + +--- a/include/configs/rpi.h ++++ b/include/configs/rpi.h +@@ -13,7 +13,7 @@ + #include + #endif + +-#if defined(CONFIG_TARGET_RPI_2) || defined(CONFIG_TARGET_RPI_3_32B) ++#ifndef CONFIG_ARM64 + #define CONFIG_SKIP_LOWLEVEL_INIT + #endif + +@@ -96,6 +96,7 @@ + + /* Environment */ + #define CONFIG_SYS_LOAD_ADDR 0x1000000 ++#define CONFIG_SYS_REDUNDAND_ENVIRONMENT + + /* Shell */ + +--- a/configs/rpi_2_defconfig ++++ b/configs/rpi_2_defconfig +@@ -4,7 +4,7 @@ + CONFIG_SYS_TEXT_BASE=0x00008000 + CONFIG_TARGET_RPI_2=y + CONFIG_NR_DRAM_BANKS=1 +-CONFIG_ENV_SIZE=0x4000 ++CONFIG_ENV_SIZE=0x20000 + CONFIG_DEFAULT_DEVICE_TREE="bcm2836-rpi-2-b" + CONFIG_DISTRO_DEFAULTS=y + CONFIG_OF_BOARD_SETUP=y +@@ -42,3 +42,4 @@ + CONFIG_CONSOLE_SCROLL_LINES=10 + CONFIG_PHYS_TO_BUS=y + CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_SUPPORT_RAW_INITRD=y +--- a/configs/rpi_3_32b_defconfig ++++ b/configs/rpi_3_32b_defconfig +@@ -5,7 +5,7 @@ + CONFIG_TARGET_RPI_3_32B=y + CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_NR_DRAM_BANKS=1 +-CONFIG_ENV_SIZE=0x4000 ++CONFIG_ENV_SIZE=0x20000 + CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b" + CONFIG_DISTRO_DEFAULTS=y + CONFIG_OF_BOARD_SETUP=y +@@ -45,3 +45,4 @@ + CONFIG_CONSOLE_SCROLL_LINES=10 + CONFIG_PHYS_TO_BUS=y + CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_SUPPORT_RAW_INITRD=y +--- a/configs/rpi_3_defconfig ++++ b/configs/rpi_3_defconfig +@@ -5,7 +5,7 @@ + CONFIG_TARGET_RPI_3=y + CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_NR_DRAM_BANKS=1 +-CONFIG_ENV_SIZE=0x4000 ++CONFIG_ENV_SIZE=0x20000 + CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b" + CONFIG_DISTRO_DEFAULTS=y + CONFIG_OF_BOARD_SETUP=y +@@ -45,3 +45,4 @@ + CONFIG_CONSOLE_SCROLL_LINES=10 + CONFIG_PHYS_TO_BUS=y + CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_SUPPORT_RAW_INITRD=y +--- a/configs/rpi_4_32b_defconfig ++++ b/configs/rpi_4_32b_defconfig +@@ -3,7 +3,7 @@ + CONFIG_SYS_TEXT_BASE=0x00008000 + CONFIG_TARGET_RPI_4_32B=y + CONFIG_SYS_MALLOC_F_LEN=0x2000 +-CONFIG_ENV_SIZE=0x4000 ++CONFIG_ENV_SIZE=0x20000 + CONFIG_DISTRO_DEFAULTS=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_USE_PREBOOT=y +@@ -58,3 +58,4 @@ + CONFIG_ADDR_MAP=y + CONFIG_SYS_NUM_ADDR_MAP=2 + CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_SUPPORT_RAW_INITRD=y +--- a/configs/rpi_4_defconfig ++++ b/configs/rpi_4_defconfig +@@ -3,7 +3,7 @@ + CONFIG_SYS_TEXT_BASE=0x00080000 + CONFIG_TARGET_RPI_4=y + CONFIG_SYS_MALLOC_F_LEN=0x2000 +-CONFIG_ENV_SIZE=0x4000 ++CONFIG_ENV_SIZE=0x20000 + CONFIG_DISTRO_DEFAULTS=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_USE_PREBOOT=y +@@ -56,3 +56,4 @@ + CONFIG_CONSOLE_SCROLL_LINES=10 + CONFIG_PHYS_TO_BUS=y + CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_SUPPORT_RAW_INITRD=y diff -Nru u-boot-2021.01+dfsg/debian/patches/rpi-maxargs.patch u-boot-2021.01+dfsg/debian/patches/rpi-maxargs.patch --- u-boot-2021.01+dfsg/debian/patches/rpi-maxargs.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/rpi-maxargs.patch 2021-05-13 22:11:21.000000000 +0100 @@ -0,0 +1,17 @@ +Author: Dave Jones +Forwarded: no +Description: Allow more than 16 args for a command for LP: #1910094 + The default u-boot command line configuration only permits a maximum of + 16 arguments per command. Unfortunately, the fix for LP: #1900879 demands + considerably more than this. + +--- a/include/configs/rpi.h ++++ b/include/configs/rpi.h +@@ -93,6 +93,7 @@ + + /* Console configuration */ + #define CONFIG_SYS_CBSIZE 1024 ++#define CONFIG_SYS_MAXARGS 64 + + /* Environment */ + #define CONFIG_SYS_LOAD_ADDR 0x1000000 diff -Nru u-boot-2021.01+dfsg/debian/patches/series u-boot-2021.01+dfsg/debian/patches/series --- u-boot-2021.01+dfsg/debian/patches/series 2021-03-12 21:17:18.000000000 +0000 +++ u-boot-2021.01+dfsg/debian/patches/series 2021-05-13 22:11:21.000000000 +0100 @@ -14,10 +14,66 @@ exynos/0001-arm-config-fix-default-console-only-to-specify-the-d.patch +riscv64/sifive-unleashed-default-fdt-files.patch riscv64/qemu-riscv64_smode-sifive-fu540-fix-extlinux-define-.patch +# patches to here, will be used for the fu540 unleashed +# patches from here, will also be applied for unmatched +riscv64/sifive-fu540-compressed-booti-support.patch +riscv64/0001-clk-sifive-fu540-prci-Extract-prci-core-to-common-ba.patch +riscv64/0002-clk-sifive-fu540-prci-Use-common-name-for-prci-confi.patch +riscv64/0003-clk-sifive-fu740-Sync-up-DT-bindings-header-with-ups.patch +riscv64/0004-clk-sifive-fu740-prci-Add-a-driver-for-the-SiFive-FU.patch +riscv64/0005-clk-sifive-select-PLL-clock-as-input-source-after-en.patch +riscv64/0006-clk-sifive-fu740-prci-set-HFPCLKPLL-rate-to-260-Mhz.patch +riscv64/0007-riscv-dts-Add-SiFive-FU740-C000-SoC-dts-from-Linux.patch +riscv64/0008-riscv-dts-Add-hifive-unmatched-a00-dts-from-Linux.patch +riscv64/0009-riscv-cpu-fu740-Add-support-for-cpu-fu740.patch +riscv64/0010-riscv-Add-SiFive-HiFive-Unmatched-FU740-board-suppor.patch +riscv64/0011-riscv-sifive-dts-fu740-Add-board-u-boot.dtsi-files.patch +riscv64/0012-dt-bindings-sifive-fu740-add-indexes-for-reset-signa.patch +riscv64/0013-fu740-dtsi-add-reset-producer-and-consumer-entries.patch +riscv64/0014-ram-sifive-Add-common-DDR-driver-for-sifive.patch +riscv64/0015-ram-sifive-Added-compatible-string-for-FU740-c000-dd.patch +riscv64/0016-sifive-dts-fu740-Add-DDR-controller-and-phy-register.patch +riscv64/0017-riscv-sifive-dts-fu740-add-U-Boot-dmc-node.patch +riscv64/0018-riscv-sifive-hifive_unmatched_fu740-add-SPL-configur.patch +riscv64/0019-sifive-hifive_unmatched_fu740-Add-sample-SD-gpt-part.patch +riscv64/0020-sifive-fu740-Add-U-Boot-proper-sector-start.patch +riscv64/0021-configs-hifive_unmatched_fu740-Add-config-options-fo.patch +riscv64/0022-riscv-sifive-fu540-enable-all-cache-ways-from-U-Boot.patch +riscv64/0023-riscv-sifive-dts-fu740-set-ethernet-clock-rate.patch +riscv64/0024-sifive-fu740-set-kernel_comp_addr_r-and-kernel_comp_.patch +riscv64/0025-sifive-fu740-enable-full-L2-cache-ways-16-ways-total.patch +riscv64/0026-sifive-fu740-fix-cache-controller-signals-order.patch +riscv64/0027-sifive-fu740-change-eth0-assigned-clock-rates-to-125.patch +riscv64/0028-sifive-hifive_unmatched_fu740-Enable-64bit-PCI-resou.patch +riscv64/0029-clk-sifive-add-pciaux-clock.patch +riscv64/0030-pci-sifive-add-pcie-driver-for-fu740.patch +riscv64/0031-Update-SiFive-Unmatched-defconfig.patch +riscv64/0032-riscv-sifive-unmatched-set-cacheline-size-to-64-byte.patch +riscv64/0033-fu740-add-CONFIG_CMD_GPT-and-CONFIG_CMD_GPT_RENAME.patch +riscv64/0034-Unmathced-FU740-add-NVME-USB-and-PXE-to-boot-targets.patch +riscv64/0035-riscv-clear-feature-disable-CSR.patch +riscv64/0036-riscv-sifive-unmatched-add-I2C-EEPROM.patch +riscv64/0037-cmd-Add-a-pwm-command.patch +riscv64/0038-cmd-pwm-Rework-argc-sanity-checking.patch +riscv64/0039-riscv-sifive-unmatched-enable-PWM.patch +riscv64/0040-riscv-sifive-unmatched-update-for-rev3-16GB-1866.patch +riscv64/0041-Fix-CRC32-checksum-for-SiFive-HiFive-EEPROM.patch +riscv64/sifive-unmatched-default-fdt-files.patch +riscv64/use-preboot-unmatched.patch +riscv64/qemu-skip-fdtdir.patch n900/bootz_and_raw_initrd.patch rk3399/disable-preboot pinetab/0001-configs-add-PineTab-defconfig.patch + +rpi-config-tweaks.patch +ubuntu-hardening-limit-keynames-to-keydir.patch +ubuntu-nitrogen6q2g-config-tweaks.patch +rpi-board-dt.patch +rpi-cm4-sdhci.patch +rpi-8gb-pci.patch +rpi-maxargs.patch diff -Nru u-boot-2021.01+dfsg/debian/patches/ubuntu-hardening-limit-keynames-to-keydir.patch u-boot-2021.01+dfsg/debian/patches/ubuntu-hardening-limit-keynames-to-keydir.patch --- u-boot-2021.01+dfsg/debian/patches/ubuntu-hardening-limit-keynames-to-keydir.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/ubuntu-hardening-limit-keynames-to-keydir.patch 2021-05-13 22:11:00.000000000 +0100 @@ -0,0 +1,49 @@ +Description: limit keyname to prevent escape from keydir + Limit key names to keys within the keydir by refusing keynames containing + a slash. +Author: Andy Whitcroft +Forwarded: no +Last-Update: 2019-05-31 + +--- + +--- a/lib/rsa/rsa-sign.c ++++ b/lib/rsa/rsa-sign.c +@@ -63,6 +63,11 @@ + FILE *f; + int ret; + ++ if (strchr(name, '/')) { ++ fprintf(stderr, "Invalid key name '%s': contains '/' \n", name); ++ return -EACCES; ++ } ++ + *rsap = NULL; + snprintf(path, sizeof(path), "%s/%s.crt", keydir, name); + f = fopen(path, "r"); +@@ -210,6 +215,11 @@ + RSA *rsa; + FILE *f; + ++ if (strchr(name, '/')) { ++ fprintf(stderr, "Invalid key name '%s': contains '/' \n", name); ++ return -EACCES; ++ } ++ + *rsap = NULL; + snprintf(path, sizeof(path), "%s/%s.key", keydir, name); + f = fopen(path, "r"); +--- a/tools/kwbimage.c ++++ b/tools/kwbimage.c +@@ -395,6 +395,11 @@ + if (!keydir) + keydir = "."; + ++ if (strchr(name, '/')) { ++ fprintf(stderr, "Invalid key name '%s': contains '/' \n", name); ++ return -EACCES; ++ } ++ + snprintf(path, sizeof(path), "%s/%s.key", keydir, name); + f = fopen(path, "r"); + if (!f) { diff -Nru u-boot-2021.01+dfsg/debian/patches/ubuntu-nitrogen6q2g-config-tweaks.patch u-boot-2021.01+dfsg/debian/patches/ubuntu-nitrogen6q2g-config-tweaks.patch --- u-boot-2021.01+dfsg/debian/patches/ubuntu-nitrogen6q2g-config-tweaks.patch 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/patches/ubuntu-nitrogen6q2g-config-tweaks.patch 2021-05-13 22:11:00.000000000 +0100 @@ -0,0 +1,55 @@ +--- a/configs/nitrogen6q2g_defconfig ++++ b/configs/nitrogen6q2g_defconfig +@@ -5,7 +5,7 @@ + CONFIG_NR_DRAM_BANKS=1 + CONFIG_SYS_MEMTEST_START=0x10000000 + CONFIG_SYS_MEMTEST_END=0x10010000 +-CONFIG_ENV_SIZE=0x2000 ++CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_OFFSET=0xC0000 + CONFIG_ENV_SECT_SIZE=0x2000 + CONFIG_MX6Q=y +@@ -27,8 +27,10 @@ + CONFIG_SYS_ALT_MEMTEST=y + # CONFIG_CMD_FLASH is not set + CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y ++CONFIG_CMD_PART=y + CONFIG_CMD_SATA=y + CONFIG_CMD_USB=y + CONFIG_CMD_USB_MASS_STORAGE=y +@@ -46,6 +48,10 @@ + CONFIG_OF_CONTROL=y + CONFIG_ENV_OVERWRITE=y + CONFIG_ENV_IS_IN_SPI_FLASH=y ++CONFIG_ENV_IS_IN_FAT=y ++CONFIG_ENV_FAT_INTERFACE="mmc" ++CONFIG_ENV_FAT_DEVICE_AND_PART="0:auto" ++CONFIG_ENV_FAT_FILE="uboot.env" + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_NETCONSOLE=y + CONFIG_DM=y +@@ -53,6 +59,8 @@ + CONFIG_DWC_AHSATA=y + CONFIG_USB_FUNCTION_FASTBOOT=y + CONFIG_FASTBOOT_BUF_ADDR=0x12000000 ++CONFIG_FAT_WRITE=y ++CONFIG_FS_FAT=y + CONFIG_DM_MMC=y + CONFIG_FSL_USDHC=y + CONFIG_MTD=y +--- a/include/configs/nitrogen6x.h ++++ b/include/configs/nitrogen6x.h +@@ -11,6 +11,10 @@ + + #include "mx6_common.h" + ++#if defined(CONFIG_TARGET_NITROGEN6X) ++#define CONFIG_SYS_REDUNDAND_ENVIRONMENT ++#endif ++ + #define CONFIG_MACH_TYPE 3769 + + /* Size of malloc() pool */ diff -Nru u-boot-2021.01+dfsg/debian/rules u-boot-2021.01+dfsg/debian/rules --- u-boot-2021.01+dfsg/debian/rules 2021-03-12 21:33:38.000000000 +0000 +++ u-boot-2021.01+dfsg/debian/rules 2021-05-13 22:11:21.000000000 +0100 @@ -35,6 +35,8 @@ # Enable debugging symbols and remove build paths export HOSTCFLAGS = -g -ffile-prefix-map=$(CURDIR)=. +export OPENSBI=/usr/lib/riscv64-linux-gnu/opensbi/generic/fw_dynamic.bin + %: dh $@ @@ -69,6 +71,9 @@ case $$platform in \ novena-rawsd) targets="$$targets" ;\ ;; \ + sifive_fu540) \ + quilt pop riscv64/sifive-fu540-compressed-booti-support.patch ; \ + ;; \ *) targets="$$targets uboot.elf" ;\ ;; \ esac;\ @@ -115,6 +120,11 @@ cp $$builddir/.config $$builddir/config.$$platform; \ echo $$builddir/config.$$platform /usr/share/doc/$$subpackage/configs/ \ >> debian/build/targets.$$subarch; \ + case $$platform in \ + sifive_fu540) \ + quilt push -a ;\ + ;; \ + esac;\ done TOOLSDIR := debian/build/tools diff -Nru u-boot-2021.01+dfsg/debian/targets u-boot-2021.01+dfsg/debian/targets --- u-boot-2021.01+dfsg/debian/targets 2021-03-12 19:10:05.000000000 +0000 +++ u-boot-2021.01+dfsg/debian/targets 2021-05-13 22:11:21.000000000 +0100 @@ -44,6 +44,9 @@ # Hector Oron armhf imx nitrogen6q u-boot-dtb.imx +# Shrirang Bagul +armhf imx nitrogen6q2g u-boot-dtb.imx + # Vagrant Cascadian armhf imx novena u-boot.img SPL armhf imx novena-rawsd SPL @@ -271,7 +274,8 @@ avr32 - hammerhead u-boot.img # Hector Oron -riscv64 sifive sifive_fu540 u-boot.bin +riscv64 sifive sifive_fu540 u-boot.bin spl/u-boot-spl.bin u-boot.itb +riscv64 sifive sifive_hifive_unmatched_fu740 u-boot.bin spl/u-boot-spl.bin u-boot.itb sh4 - r2dplus u-boot.bin diff -Nru u-boot-2021.01+dfsg/debian/u-boot-rpi.triggers u-boot-2021.01+dfsg/debian/u-boot-rpi.triggers --- u-boot-2021.01+dfsg/debian/u-boot-rpi.triggers 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2021.01+dfsg/debian/u-boot-rpi.triggers 2021-05-13 22:11:00.000000000 +0100 @@ -0,0 +1 @@ +activate-noawait flash-kernel