SPL output with DEBUG enabled:

U-Boot SPL 2011.09-rc2 (Dec 08 2011 - 10:07:02)
Texas Instruments OMAP4430 ES2.0
Enable clock domain - 0x4a009400
Enable clock domain - 0x4a009300
Enable clock domain - 0x4a008b00
Enable clock domain - 0x4a008d00
Enable clock module - 0x4a307838
Enable clock module - 0x4a009460
Enable clock module - 0x4a009468
Enable clock module - 0x4a009470
Enable clock module - 0x4a009478
Enable clock module - 0x4a009480
Enable clock module - 0x4a008b30
Enable clock module - 0x4a008b38
Enable clock module - 0x4a009360
Enable clock module - 0x4a0093e0
Enable clock module - 0x4a008d20
Enable clock module - 0x4a009438
Enable clock module - 0x4a009328
Enable clock module - 0x4a009330
Enable clock module - 0x4a0094f0
Enable clock module - 0x4a307840
Enable clock module - 0x4a0094a0
Enable clock module - 0x4a0094a8
Enable clock module - 0x4a0094b0
Enable clock module - 0x4a0094b8
Enable clock module - 0x4a307830
Enable clock module - 0x4a009550
Enable clock domain - 0x4a009400
Enable clock domain - 0x4a009300
Enable clock domain - 0x4a008b00
Enable clock domain - 0x4a008d00
do_scale_vcore: volt - 1417 offset_code - 0x39
do_scale_vcore: volt - 1200 offset_code - 0x28
do_scale_vcore: volt - 1200 offset_code - 0x28
setup_dplls
Core DPLL configured}
                     PER DPLL locked
MPU DPLL locked
Enable clock domain - 0x4a008900
Enable clock domain - 0x4a008f00
Enable clock domain - 0x4a004400
Enable clock domain - 0x4a009100
Enable clock domain - 0x4a009200
Enable clock domain - 0x4a004500
Enable clock domain - 0x4a008c00
Enable clock domain - 0x4a009000
Enable clock domain - 0x4a009100
Enable clock domain - 0x4a008a00
Enable clock module - 0x4a008920
Enable clock module - 0x4a008f20
Enable clock module - 0x4a008f28
Enable clock module - 0x4a004420
Enable clock module - 0x4a008828
Enable clock module - 0x4a008e20
Enable clock module - 0x4a008e28
Enable clock module - 0x4a008e40
Enable clock module - 0x4a009338
Enable clock module - 0x4a009368
Enable clock module - 0x4a004528
Enable clock module - 0x4a004530
Enable clock module - 0x4a004538
Enable clock module - 0x4a004540
Enable clock module - 0x4a004548
Enable clock module - 0x4a004550
Enable clock module - 0x4a004558
Enable clock module - 0x4a004560
Enable clock module - 0x4a004568
Enable clock module - 0x4a004570
Enable clock module - 0x4a004578
Enable clock module - 0x4a004580
Enable clock module - 0x4a004588
Enable clock module - 0x4a009450
Enable clock module - 0x4a009428
Enable clock module - 0x4a009430
Enable clock module - 0x4a009440
Enable clock module - 0x4a009448
Enable clock module - 0x4a009488
Enable clock module - 0x4a0094e0
Enable clock module - 0x4a0094f8
Enable clock module - 0x4a009500
Enable clock module - 0x4a009508
Enable clock module - 0x4a009520
Enable clock module - 0x4a009528
Enable clock module - 0x4a009560
Enable clock module - 0x4a009540
Enable clock module - 0x4a009548
Enable clock module - 0x4a009558
Enable clock module - 0x4a307878
Enable clock module - 0x4a307830
Enable clock module - 0x4a009020
Enable clock module - 0x4a009028
Enable clock module - 0x4a009120
Enable clock module - 0x4a009220
Enable clock module - 0x4a009358
Enable clock module - 0x4a0093d0
Enable clock domain - 0x4a008900
Enable clock domain - 0x4a008f00
Enable clock domain - 0x4a004400
Enable clock domain - 0x4a009100
Enable clock domain - 0x4a009200
Enable clock domain - 0x4a004500
Enable clock domain - 0x4a008c00
Enable clock domain - 0x4a009000
Enable clock domain - 0x4a009100
Enable clock domain - 0x4a008a00
>>sdram_init()
in_sdram = 0
>>do_sdram_init() 4c000000
get_mr: EMIF1 cs 0 mr 00000000 val 0x0
get_mr: EMIF1 cs 1 mr 80000000 val 0x0
<<do_sdram_init() 4c000000
>>do_sdram_init() 4d000000
get_mr: EMIF2 cs 0 mr 00000000 val 0x0
get_mr: EMIF2 cs 1 mr 80000000 val 0x0
<<do_sdram_init() 4d000000
Enable clock domain - 0x4a008b00
Enable clock domain - 0x4a008b00
SDRAM: identified size not same as expected size identified: 0 expected: 40000000
<<sdram_init()
>>board_init_f()
>>spl:board_init_r()
boot device - 5