| 2023-05-17 13:48:00 |
Markus Schade |
bug |
|
|
added bug |
| 2023-05-19 05:08:06 |
Markus Schade |
description |
[Impact]
Add the following feature bits for EPYC-Milan model and bump the version.
vaes : Vector VAES(ENC|DEC), VAES(ENC|DEC)LAST instruction support
vpclmulqdq : Vector VPCLMULQDQ instruction support
stibp-always-on : Single Thread Indirect Branch Prediction Mode has enhanced
performance and may be left Always on
amd-psfd : Predictive Store Forward Disable
no-nested-data-bp : Processor ignores nested data breakpoints
lfence-always-serializing : LFENCE instruction is always serializing
null-sel-clr-base : Null Selector Clears Base. When this bit is
set, a null segment load clears the segment base
[Test Plan]
* First of all we'll (and have in advance) run general regression tests
* Qemu shall show to be aware of the new types
# qemu-system-x86_64 -cpu ? | grep EPYC-Milan
x86 EPYC-Milan (alias configured by machine type)
x86 EPYC-Milan-v1 AMD EPYC-Milan Processor
x86 EPYC-Milan-v2 AMD EPYC-Milan Processor
[Where problems could occur]
* There are two areas to look at
a) compat behavior on old systems - e.g. libvirt would now detect IBRS
on such AMD chips and one might wonder about the change.
E.g. compatibility would exist between old-code/new-code/old->new
code; but any action (e.g. suspend resume) from new to old code
might run into trouble (not supported that way but worth to mention
for awareness)
b) Migrations between systems - this should be covered by chip
versioning but still is worth to mention. Versioning will recognize
a formerly started system as v1 and continue to handle it that way.
Only new started guests would become v2 and behave the new and
improved way.
[Other Info]
* n/a
---
https://lists.gnu.org/archive/html/qemu-devel/2023-05/msg02082.html
https://github.com/qemu/qemu/commit/27f03be6f59d04bd5673ba1e1628b2b490f9a9ff.patch
This patch depends on the definitions that were added as part of the EPYC-Milan patch:
amd-psfd, stibp-always-on:
* https://github.com/qemu/qemu/commit/bb039a230e6a7920d71d21fa9afee2653a678c48.patch
Add feature bits for CPUID_Fn80000021_EAX:
* https://github.com/qemu/qemu/commit/b70eec312b185197d639bff689007727e596afd1.patch |
[Impact]
Add the following feature bits for EPYC-Milan model and bump the version.
vaes : Vector VAES(ENC|DEC), VAES(ENC|DEC)LAST instruction support
vpclmulqdq : Vector VPCLMULQDQ instruction support
stibp-always-on : Single Thread Indirect Branch Prediction Mode has enhanced
performance and may be left Always on
amd-psfd : Predictive Store Forward Disable
no-nested-data-bp : Processor ignores nested data breakpoints
lfence-always-serializing : LFENCE instruction is always serializing
null-sel-clr-base : Null Selector Clears Base. When this bit is
set, a null segment load clears the segment base
[Test Plan]
* First of all we'll (and have in advance) run general regression tests
* Qemu shall show to be aware of the new types
# qemu-system-x86_64 -cpu ? | grep EPYC-Milan
x86 EPYC-Milan (alias configured by machine type)
x86 EPYC-Milan-v1 AMD EPYC-Milan Processor
x86 EPYC-Milan-v2 AMD EPYC-Milan Processor
[Where problems could occur]
* There are two areas to look at
a) compat behavior on old systems - e.g. libvirt would now detect IBRS
on such AMD chips and one might wonder about the change.
E.g. compatibility would exist between old-code/new-code/old->new
code; but any action (e.g. suspend resume) from new to old code
might run into trouble (not supported that way but worth to mention
for awareness)
b) Migrations between systems - this should be covered by chip
versioning but still is worth to mention. Versioning will recognize
a formerly started system as v1 and continue to handle it that way.
Only new started guests would become v2 and behave the new and
improved way.
[Other Info]
* n/a
---
https://lists.gnu.org/archive/html/qemu-devel/2023-05/msg02082.html
https://github.com/qemu/qemu/commit/27f03be6f59d04bd5673ba1e1628b2b490f9a9ff.patch
This patch depends on the definitions that were added as part of the EPYC-Milan patch:
amd-psfd, stibp-always-on:
* https://github.com/qemu/qemu/commit/bb039a230e6a7920d71d21fa9afee2653a678c48.patch
Add feature bits for CPUID_Fn80000021_EAX:
* https://github.com/qemu/qemu/commit/b70eec312b185197d639bff689007727e596afd1.patch
Kernel patches:
https://lkml.kernel.org/lkml/20230124163319.2277355-1-kim.phillips@amd.com/ |
|
| 2023-05-19 05:20:09 |
Markus Schade |
description |
[Impact]
Add the following feature bits for EPYC-Milan model and bump the version.
vaes : Vector VAES(ENC|DEC), VAES(ENC|DEC)LAST instruction support
vpclmulqdq : Vector VPCLMULQDQ instruction support
stibp-always-on : Single Thread Indirect Branch Prediction Mode has enhanced
performance and may be left Always on
amd-psfd : Predictive Store Forward Disable
no-nested-data-bp : Processor ignores nested data breakpoints
lfence-always-serializing : LFENCE instruction is always serializing
null-sel-clr-base : Null Selector Clears Base. When this bit is
set, a null segment load clears the segment base
[Test Plan]
* First of all we'll (and have in advance) run general regression tests
* Qemu shall show to be aware of the new types
# qemu-system-x86_64 -cpu ? | grep EPYC-Milan
x86 EPYC-Milan (alias configured by machine type)
x86 EPYC-Milan-v1 AMD EPYC-Milan Processor
x86 EPYC-Milan-v2 AMD EPYC-Milan Processor
[Where problems could occur]
* There are two areas to look at
a) compat behavior on old systems - e.g. libvirt would now detect IBRS
on such AMD chips and one might wonder about the change.
E.g. compatibility would exist between old-code/new-code/old->new
code; but any action (e.g. suspend resume) from new to old code
might run into trouble (not supported that way but worth to mention
for awareness)
b) Migrations between systems - this should be covered by chip
versioning but still is worth to mention. Versioning will recognize
a formerly started system as v1 and continue to handle it that way.
Only new started guests would become v2 and behave the new and
improved way.
[Other Info]
* n/a
---
https://lists.gnu.org/archive/html/qemu-devel/2023-05/msg02082.html
https://github.com/qemu/qemu/commit/27f03be6f59d04bd5673ba1e1628b2b490f9a9ff.patch
This patch depends on the definitions that were added as part of the EPYC-Milan patch:
amd-psfd, stibp-always-on:
* https://github.com/qemu/qemu/commit/bb039a230e6a7920d71d21fa9afee2653a678c48.patch
Add feature bits for CPUID_Fn80000021_EAX:
* https://github.com/qemu/qemu/commit/b70eec312b185197d639bff689007727e596afd1.patch
Kernel patches:
https://lkml.kernel.org/lkml/20230124163319.2277355-1-kim.phillips@amd.com/ |
[Impact]
Add the following feature bits for EPYC-Milan model and bump the version.
vaes : Vector VAES(ENC|DEC), VAES(ENC|DEC)LAST instruction support
vpclmulqdq : Vector VPCLMULQDQ instruction support
stibp-always-on : Single Thread Indirect Branch Prediction Mode has enhanced
performance and may be left Always on
amd-psfd : Predictive Store Forward Disable
no-nested-data-bp : Processor ignores nested data breakpoints
lfence-always-serializing : LFENCE instruction is always serializing
null-sel-clr-base : Null Selector Clears Base. When this bit is
set, a null segment load clears the segment base
[Test Plan]
* First of all we'll (and have in advance) run general regression tests
* Qemu shall show to be aware of the new types
# qemu-system-x86_64 -cpu ? | grep EPYC-Milan
x86 EPYC-Milan (alias configured by machine type)
x86 EPYC-Milan-v1 AMD EPYC-Milan Processor
x86 EPYC-Milan-v2 AMD EPYC-Milan Processor
[Where problems could occur]
* There are two areas to look at
a) compat behavior on old systems - e.g. libvirt would now detect IBRS
on such AMD chips and one might wonder about the change.
E.g. compatibility would exist between old-code/new-code/old->new
code; but any action (e.g. suspend resume) from new to old code
might run into trouble (not supported that way but worth to mention
for awareness)
b) Migrations between systems - this should be covered by chip
versioning but still is worth to mention. Versioning will recognize
a formerly started system as v1 and continue to handle it that way.
Only new started guests would become v2 and behave the new and
improved way.
[Other Info]
* n/a
---
https://lists.gnu.org/archive/html/qemu-devel/2023-05/msg02082.html
https://github.com/qemu/qemu/commit/27f03be6f59d04bd5673ba1e1628b2b490f9a9ff.patch
This patch depends on the definitions that were added as part of the EPYC-Milan patch:
amd-psfd, stibp-always-on:
* https://github.com/qemu/qemu/commit/bb039a230e6a7920d71d21fa9afee2653a678c48.patch
Add feature bits for CPUID_Fn80000021_EAX:
* https://github.com/qemu/qemu/commit/b70eec312b185197d639bff689007727e596afd1.patch
Kernel patches:
https://lkml.kernel.org/lkml/20230124163319.2277355-1-kim.phillips@amd.com/
kvm: Add support for CPUID_80000021_EAX
* https://github.com/torvalds/linux/commit/8415a74852d7c24795007ee9862d25feb519007c.patch
kvm: Add the NO_NESTED_DATA_BP feature
* https://github.com/torvalds/linux/commit/a9dc9ec5a1fafc3d2fe7a7b594eefaeaccf89a6b.patch
kvm: Move X86_FEATURE_LFENCE_RDTSC to its native leaf
* https://github.com/torvalds/linux/commit/84168ae786f8a15a7eb0f79d34f20b8d261ce2f5.patch
kvm: Add the Null Selector Clears Base feature
* https://github.com/torvalds/linux/commit/5b909d4ae59aedc711b7a432da021be0e82c95a0.patch
kvm: Add the SMM_CTL MSR not present feature
https://github.com/torvalds/linux/commit/faabfcb194a8d0686396e3fff6a5b42911f65191.patch |
|
| 2023-05-19 05:22:09 |
Markus Schade |
description |
[Impact]
Add the following feature bits for EPYC-Milan model and bump the version.
vaes : Vector VAES(ENC|DEC), VAES(ENC|DEC)LAST instruction support
vpclmulqdq : Vector VPCLMULQDQ instruction support
stibp-always-on : Single Thread Indirect Branch Prediction Mode has enhanced
performance and may be left Always on
amd-psfd : Predictive Store Forward Disable
no-nested-data-bp : Processor ignores nested data breakpoints
lfence-always-serializing : LFENCE instruction is always serializing
null-sel-clr-base : Null Selector Clears Base. When this bit is
set, a null segment load clears the segment base
[Test Plan]
* First of all we'll (and have in advance) run general regression tests
* Qemu shall show to be aware of the new types
# qemu-system-x86_64 -cpu ? | grep EPYC-Milan
x86 EPYC-Milan (alias configured by machine type)
x86 EPYC-Milan-v1 AMD EPYC-Milan Processor
x86 EPYC-Milan-v2 AMD EPYC-Milan Processor
[Where problems could occur]
* There are two areas to look at
a) compat behavior on old systems - e.g. libvirt would now detect IBRS
on such AMD chips and one might wonder about the change.
E.g. compatibility would exist between old-code/new-code/old->new
code; but any action (e.g. suspend resume) from new to old code
might run into trouble (not supported that way but worth to mention
for awareness)
b) Migrations between systems - this should be covered by chip
versioning but still is worth to mention. Versioning will recognize
a formerly started system as v1 and continue to handle it that way.
Only new started guests would become v2 and behave the new and
improved way.
[Other Info]
* n/a
---
https://lists.gnu.org/archive/html/qemu-devel/2023-05/msg02082.html
https://github.com/qemu/qemu/commit/27f03be6f59d04bd5673ba1e1628b2b490f9a9ff.patch
This patch depends on the definitions that were added as part of the EPYC-Milan patch:
amd-psfd, stibp-always-on:
* https://github.com/qemu/qemu/commit/bb039a230e6a7920d71d21fa9afee2653a678c48.patch
Add feature bits for CPUID_Fn80000021_EAX:
* https://github.com/qemu/qemu/commit/b70eec312b185197d639bff689007727e596afd1.patch
Kernel patches:
https://lkml.kernel.org/lkml/20230124163319.2277355-1-kim.phillips@amd.com/
kvm: Add support for CPUID_80000021_EAX
* https://github.com/torvalds/linux/commit/8415a74852d7c24795007ee9862d25feb519007c.patch
kvm: Add the NO_NESTED_DATA_BP feature
* https://github.com/torvalds/linux/commit/a9dc9ec5a1fafc3d2fe7a7b594eefaeaccf89a6b.patch
kvm: Move X86_FEATURE_LFENCE_RDTSC to its native leaf
* https://github.com/torvalds/linux/commit/84168ae786f8a15a7eb0f79d34f20b8d261ce2f5.patch
kvm: Add the Null Selector Clears Base feature
* https://github.com/torvalds/linux/commit/5b909d4ae59aedc711b7a432da021be0e82c95a0.patch
kvm: Add the SMM_CTL MSR not present feature
https://github.com/torvalds/linux/commit/faabfcb194a8d0686396e3fff6a5b42911f65191.patch |
[Impact]
Add the following feature bits for EPYC-Milan model and bump the version.
vaes : Vector VAES(ENC|DEC), VAES(ENC|DEC)LAST instruction support
vpclmulqdq : Vector VPCLMULQDQ instruction support
stibp-always-on : Single Thread Indirect Branch Prediction Mode has enhanced
performance and may be left Always on
amd-psfd : Predictive Store Forward Disable
no-nested-data-bp : Processor ignores nested data breakpoints
lfence-always-serializing : LFENCE instruction is always serializing
null-sel-clr-base : Null Selector Clears Base. When this bit is
set, a null segment load clears the segment base
[Test Plan]
* First of all we'll (and have in advance) run general regression tests
* Qemu shall show to be aware of the new types
# qemu-system-x86_64 -cpu ? | grep EPYC-Milan
x86 EPYC-Milan (alias configured by machine type)
x86 EPYC-Milan-v1 AMD EPYC-Milan Processor
x86 EPYC-Milan-v2 AMD EPYC-Milan Processor
[Where problems could occur]
* There are two areas to look at
a) compat behavior on old systems - e.g. libvirt would now detect IBRS
on such AMD chips and one might wonder about the change.
E.g. compatibility would exist between old-code/new-code/old->new
code; but any action (e.g. suspend resume) from new to old code
might run into trouble (not supported that way but worth to mention
for awareness)
b) Migrations between systems - this should be covered by chip
versioning but still is worth to mention. Versioning will recognize
a formerly started system as v1 and continue to handle it that way.
Only new started guests would become v2 and behave the new and
improved way.
[Other Info]
* n/a
---
https://lists.gnu.org/archive/html/qemu-devel/2023-05/msg02082.html
https://github.com/qemu/qemu/commit/27f03be6f59d04bd5673ba1e1628b2b490f9a9ff.patch
This patch depends on the definitions that were added as part of the EPYC-Milan patch:
amd-psfd, stibp-always-on:
* https://github.com/qemu/qemu/commit/bb039a230e6a7920d71d21fa9afee2653a678c48.patch
Add feature bits for CPUID_Fn80000021_EAX:
* https://github.com/qemu/qemu/commit/b70eec312b185197d639bff689007727e596afd1.patch
Kernel patches:
https://lkml.kernel.org/lkml/20230124163319.2277355-1-kim.phillips@amd.com/
kvm: Add support for CPUID_80000021_EAX
* https://github.com/torvalds/linux/commit/8415a74852d7c24795007ee9862d25feb519007c.patch
kvm: Add the NO_NESTED_DATA_BP feature
* https://github.com/torvalds/linux/commit/a9dc9ec5a1fafc3d2fe7a7b594eefaeaccf89a6b.patch
kvm: Move X86_FEATURE_LFENCE_RDTSC to its native leaf
* https://github.com/torvalds/linux/commit/84168ae786f8a15a7eb0f79d34f20b8d261ce2f5.patch
kvm: Add the Null Selector Clears Base feature
* https://github.com/torvalds/linux/commit/5b909d4ae59aedc711b7a432da021be0e82c95a0.patch
kvm: Add the SMM_CTL MSR not present feature
https://github.com/torvalds/linux/commit/faabfcb194a8d0686396e3fff6a5b42911f65191.patch
And probably this one as well:
KVM: Add common feature flag for AMD's PSFD
https://github.com/torvalds/linux/commit/3d8f61bf8bcd69bcd397276d53aa18f7ca8347f9.patch |
|
| 2023-05-22 20:03:59 |
Lena Voytek |
nominated for series |
|
Ubuntu Jammy |
|
| 2023-05-22 20:03:59 |
Lena Voytek |
bug task added |
|
qemu (Ubuntu Jammy) |
|
| 2023-05-22 20:03:59 |
Lena Voytek |
nominated for series |
|
Ubuntu Mantic |
|
| 2023-05-22 20:03:59 |
Lena Voytek |
bug task added |
|
qemu (Ubuntu Mantic) |
|
| 2023-05-22 20:03:59 |
Lena Voytek |
nominated for series |
|
Ubuntu Lunar |
|
| 2023-05-22 20:03:59 |
Lena Voytek |
bug task added |
|
qemu (Ubuntu Lunar) |
|
| 2023-05-22 20:03:59 |
Lena Voytek |
nominated for series |
|
Ubuntu Kinetic |
|
| 2023-05-22 20:03:59 |
Lena Voytek |
bug task added |
|
qemu (Ubuntu Kinetic) |
|
| 2023-05-22 20:04:34 |
Lena Voytek |
tags |
|
server-triage-discuss |
|
| 2023-05-31 15:04:48 |
Robie Basak |
qemu (Ubuntu Mantic): assignee |
|
Sergio Durigan Junior (sergiodj) |
|
| 2023-05-31 15:04:55 |
Robie Basak |
tags |
server-triage-discuss |
server-todo |
|
| 2023-07-17 23:19:11 |
Sergio Durigan Junior |
bug task added |
|
linux (Ubuntu) |
|
| 2023-08-10 18:02:34 |
Utkarsh Gupta |
linux (Ubuntu Kinetic): status |
New |
Won't Fix |
|
| 2023-08-22 15:32:24 |
Ubuntu Kernel Bot |
linux (Ubuntu): status |
New |
Incomplete |
|
| 2023-08-22 15:32:25 |
Ubuntu Kernel Bot |
linux (Ubuntu Jammy): status |
New |
Incomplete |
|
| 2023-08-22 15:32:26 |
Ubuntu Kernel Bot |
linux (Ubuntu Lunar): status |
New |
Incomplete |
|
| 2023-09-02 04:02:24 |
Sergio Durigan Junior |
linux (Ubuntu Jammy): status |
Incomplete |
New |
|
| 2023-09-02 04:02:30 |
Sergio Durigan Junior |
linux (Ubuntu Lunar): status |
Incomplete |
New |
|
| 2023-09-02 04:02:35 |
Sergio Durigan Junior |
linux (Ubuntu Mantic): status |
Incomplete |
New |
|
| 2023-09-02 04:02:42 |
Sergio Durigan Junior |
qemu (Ubuntu Kinetic): status |
New |
Won't Fix |
|
| 2023-09-02 04:30:07 |
Ubuntu Kernel Bot |
linux (Ubuntu): status |
New |
Incomplete |
|
| 2023-09-02 04:30:08 |
Ubuntu Kernel Bot |
linux (Ubuntu Jammy): status |
New |
Incomplete |
|
| 2023-09-02 04:30:10 |
Ubuntu Kernel Bot |
linux (Ubuntu Lunar): status |
New |
Incomplete |
|
| 2023-09-02 04:36:42 |
Sergio Durigan Junior |
linux (Ubuntu Jammy): status |
Incomplete |
Confirmed |
|
| 2023-09-02 04:36:49 |
Sergio Durigan Junior |
linux (Ubuntu Lunar): status |
Incomplete |
Confirmed |
|
| 2023-09-02 04:36:55 |
Sergio Durigan Junior |
linux (Ubuntu Mantic): status |
Incomplete |
Confirmed |
|
| 2024-01-25 20:39:37 |
Brian Murray |
linux (Ubuntu Lunar): status |
Confirmed |
Won't Fix |
|
