Comment 11 for bug 1872945

FYI v5.0.0-rc3 - working as well

Bisect log (looking for the fix):

git bisect start
# old: [b0ca999a43a22b38158a222233d3f5881648bb4f] Update version for v4.2.0 release
git bisect old b0ca999a43a22b38158a222233d3f5881648bb4f
# new: [20038cd7a8412feeb49c01f6ede89e36c8995472] Update version for v5.0.0-rc3 release
git bisect new 20038cd7a8412feeb49c01f6ede89e36c8995472
# new: [971b2a1e5b1a8cc8f597ac5d7016908f9fa880de] Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-5.0-sf2' into staging
git bisect new 971b2a1e5b1a8cc8f597ac5d7016908f9fa880de
# old: [bd5de61e7b926b5bb9dae254630bf3c8be575bc0] migration: add savevm_state_handler_remove()
git bisect old bd5de61e7b926b5bb9dae254630bf3c8be575bc0
# new: [cd45c506c8ec37c05fdfe06441ad350ab8e19138] hw/s390x/ipl: replace deprecated qdev_reset_all registration
git bisect new cd45c506c8ec37c05fdfe06441ad350ab8e19138
# old: [cdc497c6925be745bc895355bd4674a17a4b2a8b] virtiofsd: prevent FUSE_INIT/FUSE_DESTROY races
git bisect old cdc497c6925be745bc895355bd4674a17a4b2a8b
# new: [760df0d121a836dcbf3726b80b820115aef21b30] Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
git bisect new 760df0d121a836dcbf3726b80b820115aef21b30
# old: [4f67d30b5e74e060b8dbe10528829b47345cd6e8] qdev: set properties with device_class_set_props()
git bisect old 4f67d30b5e74e060b8dbe10528829b47345cd6e8
# old: [c0248b36d8d190933a43919b9f71013a255e866c] Merge remote-tracking branch 'remotes/kraxel/tags/ui-20200123-pull-request' into staging
git bisect old c0248b36d8d190933a43919b9f71013a255e866c
# old: [a4abb6f2061f3a40f01cfe4c79c1527db655ac89] hw/misc/stm32f4xx_syscfg: Fix copy/paste error
git bisect old a4abb6f2061f3a40f01cfe4c79c1527db655ac89
# new: [ba2ed84fe6a78f64b2da441750fc6e925d94106a] Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-5.0-sf1' into staging
git bisect new ba2ed84fe6a78f64b2da441750fc6e925d94106a
# old: [1d59b1b210d7c3b0bdf4b10ebe0bb1fccfcb8b95] virtiofsd: add some options to the help message
git bisect old 1d59b1b210d7c3b0bdf4b10ebe0bb1fccfcb8b95
# old: [613fa160e19abe8e1fe44423fcfa8ec73d3d48e5] target/riscv: Fix tb->flags FS status
git bisect old 613fa160e19abe8e1fe44423fcfa8ec73d3d48e5
# old: [a37f21c27d3e2342c2080aafd4cfe7e949612428] riscv: Set xPIE to 1 after xRET
git bisect old a37f21c27d3e2342c2080aafd4cfe7e949612428
# new: [82f014671cf057de51c4a577c9e2ad637dcec6f9] target/riscv: update mstatus.SD when FS is set dirty
git bisect new 82f014671cf057de51c4a577c9e2ad637dcec6f9
# old: [a59796eb6d59bbd74ce28ddbddb1b83e60674e96] target/riscv: fsd/fsw doesn't dirty FP state
git bisect old a59796eb6d59bbd74ce28ddbddb1b83e60674e96
# first new commit: [82f014671cf057de51c4a577c9e2ad637dcec6f9] target/riscv: update mstatus.SD when FS is set dirty

$ git bisect old
82f014671cf057de51c4a577c9e2ad637dcec6f9 is the first new commit
commit 82f014671cf057de51c4a577c9e2ad637dcec6f9
Author: ShihPo Hung <email address hidden>
Date: Tue Jan 14 22:17:33 2020 -0800

    target/riscv: update mstatus.SD when FS is set dirty

    remove the check becuase SD bit should summarize FS and XS fields
    unconditionally.

    Signed-off-by: ShihPo Hung <email address hidden>
    Reviewed-by: Richard Henderson <email address hidden>
    Reviewed-by: Alistair Francis <email address hidden>
    Signed-off-by: Palmer Dabbelt <email address hidden>

 target/riscv/csr.c | 3 +--
 target/riscv/translate.c | 2 +-
 2 files changed, 2 insertions(+), 3 deletions(-)

I double checked
- 82f014671cf057de51c4a577c9e2ad637dcec6f9 - works
- a59796eb6d59bbd74ce28ddbddb1b83e60674e96 - fails

Also
[10:49] <wgrant> Both 613fa16 and 82f0146 revert parts of b345b48
[10:51] <wgrant> Confirmed that those two on top of v4.2.0 gets sshd good

But we might need/want more of that series ?!
97a254b3f0 target/openrisc: Fix FPCSR mask to allow setting DZF
82f014671c target/riscv: update mstatus.SD when FS is set dirty
a59796eb6d target/riscv: fsd/fsw doesn't dirty FP state
613fa160e1 target/riscv: Fix tb->flags FS status
a37f21c27d riscv: Set xPIE to 1 after xRET
bb8136df69 riscv/sifive_u: fix a memory leak in soc_realize()