opensta 0~20191111gitc018cb2+dfsg-1.1 source package in Ubuntu

Changelog

opensta (0~20191111gitc018cb2+dfsg-1.1) unstable; urgency=medium

  * Non-maintainer upload
  * add gcc14.patch (Closes: #1037806)

 -- Thorsten Alteholz <email address hidden>  Sun, 17 Nov 2024 12:03:02 +0100

Upload details

Uploaded by:
Debian Electronics Team
Uploaded to:
Sid
Original maintainer:
Debian Electronics Team
Architectures:
any
Section:
misc
Urgency:
Medium Urgency

See full publishing history Publishing

Series Pocket Published Component Section
Resolute release universe misc
Questing release universe misc
Plucky release universe misc

Downloads

File Size SHA-256 Checksum
opensta_0~20191111gitc018cb2+dfsg-1.1.dsc 2.3 KiB 8816e6452d4700aa89409a916ddff62775f73f77afabef9b65361325c289d1bf
opensta_0~20191111gitc018cb2+dfsg.orig.tar.xz 703.4 KiB 0018afff74fb12f963d8a95227552f9b391d4f281f39b68186dff91244c0d701
opensta_0~20191111gitc018cb2+dfsg-1.1.debian.tar.xz 5.8 KiB 51ff67999989460acbd7bedbf5d25757332ebad7550e0c4bde3a808d8d598a70

No changes file available.

Binary packages built by this source

opensta: Gate-level Static Timing Analyzer

 After synthesis, place and route of a digital circuit, it is necessary to
 verify the timing of the design. OpenSTA is a tool for doing exactly that. It
 has a Tcl interface for entering commands for analysing designs.
 .
 It typically takes as input a verilog netlist, a liberty file, and other
 parasitics information from the placed and routed design.

opensta-dbgsym: debug symbols for opensta
opensta-dev: Gate-level Static Timing Analyzer - development files

 After synthesis, place and route of a digital circuit, it is necessary to
 verify the timing of the design. OpenSTA is a tool for doing exactly that. It
 has a Tcl interface for entering commands for analysing designs.
 .
 It typically takes as input a verilog netlist, a liberty file, and other
 parasitics information from the placed and routed design.
 .
 This package contains the header files and some libraries for development.