opensta 0~20191111gitc018cb2+dfsg-1 source package in Ubuntu

Changelog

opensta (0~20191111gitc018cb2+dfsg-1) unstable; urgency=medium

  * New upstream version
  * debian/README.Debian: add README explaining changes done to Debian version

 -- Ruben Undheim <email address hidden>  Sat, 21 Dec 2019 16:14:40 +0100

Upload details

Uploaded by:
Debian Electronics Team on 2019-12-21
Uploaded to:
Sid
Original maintainer:
Debian Electronics Team
Architectures:
any
Section:
misc
Urgency:
Medium Urgency

See full publishing history Publishing

Series Pocket Published Component Section
Focal release on 2019-12-23 universe misc

Downloads

File Size SHA-256 Checksum
opensta_0~20191111gitc018cb2+dfsg-1.dsc 2.3 KiB 90f408228e33e0090ccf6949af52f0acd7ad3b754af064818ea088f2b312ea36
opensta_0~20191111gitc018cb2+dfsg.orig.tar.xz 703.4 KiB 0018afff74fb12f963d8a95227552f9b391d4f281f39b68186dff91244c0d701
opensta_0~20191111gitc018cb2+dfsg-1.debian.tar.xz 5.6 KiB d402de3f826d9115b1299d7a63f4c91b4b790458318faf20320e165681e0343b

No changes file available.

Binary packages built by this source

opensta: Gate-level Static Timing Analyzer

 After synthesis, place and route of a digital circuit, it is necessary to
 verify the timing of the design. OpenSTA is a tool for doing exactly that. It
 has a Tcl interface for entering commands for analysing designs.
 .
 It typically takes as input a verilog netlist, a liberty file, and other
 parasitics information from the placed and routed design.

opensta-dbgsym: debug symbols for opensta
opensta-dev: Gate-level Static Timing Analyzer - development files

 After synthesis, place and route of a digital circuit, it is necessary to
 verify the timing of the design. OpenSTA is a tool for doing exactly that. It
 has a Tcl interface for entering commands for analysing designs.
 .
 It typically takes as input a verilog netlist, a liberty file, and other
 parasitics information from the placed and routed design.
 .
 This package contains the header files and some libraries for development.