diff -Nru llvm-toolchain-13-13.0.1/debian/changelog llvm-toolchain-13-13.0.1/debian/changelog --- llvm-toolchain-13-13.0.1/debian/changelog 2022-05-09 20:47:26.000000000 +0200 +++ llvm-toolchain-13-13.0.1/debian/changelog 2022-05-25 12:04:49.000000000 +0200 @@ -1,3 +1,26 @@ +llvm-toolchain-13 (1:13.0.1-4ubuntu1) kinetic; urgency=low + + [ Ubuntu Merge-o-Matic ] + * Merge from Debian unstable. Remaining changes: + - Backport upstream patches to allow building EFI images for Ubuntu Core + for arm64 (LP: #1960300) + - Don't build clangd with GRPC support on i386. + * Dropped changes, superseded by Debian changes: + - d/rules: Don't remove libRemoteIndex{ServiceProto,Proto}.a nor + libMonitoringServiceProto.a. These are necessary for autopkgtest. + Adjust d/llvm-X.Y-dev.install accordingly when building on + i386 (i.e., don't install libRemoteIndex{ServiceProto,Proto}.a in such + case). + - d/llvm-X.Y-dev.install.in: Install libs mentioned above. + * d/libclang-X.Y-dev: don't install libRemoteIndex{ServiceProto,Proto}.a on + i386 since we don't have support for it in Ubuntu. + * d/control: declare libclang-13-dev Replaces and Breaks previous versions + of llvm-13-dev due to aforementioned libs moving packages + * d/p/risc/riscv-insn-support.patch: Backport assembler .insn support on riscv64 + for rustc 1.59.0 (LP: #1973041) + + -- Simon Chopin Wed, 25 May 2022 12:04:49 +0200 + llvm-toolchain-13 (1:13.0.1-4) unstable; urgency=medium * Backport D115098 for Rust 1.59 (Closes: #1010150) @@ -16,6 +39,31 @@ -- Sylvestre Ledru Tue, 08 Feb 2022 21:39:18 +0100 +llvm-toolchain-13 (1:13.0.1-2ubuntu3) kinetic; urgency=medium + + * Rebuild against new OCAML ABI. + + -- Gianfranco Costamagna Wed, 04 May 2022 12:28:18 +0200 + +llvm-toolchain-13 (1:13.0.1-2ubuntu2) jammy; urgency=medium + + * Backport upstream patches to allow building EFI images for Ubuntu Core + for arm64 (LP: #1960300) + + -- Alfonso Sanchez-Beato Tue, 15 Mar 2022 13:56:30 +0000 + +llvm-toolchain-13 (1:13.0.1-2ubuntu1) jammy; urgency=medium + + * Don't build clangd with GRPC support on i386. + * d/rules: Don't remove libRemoteIndex{ServiceProto,Proto}.a nor + libMonitoringServiceProto.a. These are necessary for autopkgtest. + Adjust d/llvm-X.Y-dev.install accordingly when building on + i386 (i.e., don't install libRemoteIndex{ServiceProto,Proto}.a in such + case). + * d/llvm-X.Y-dev.install.in: Install libs mentioned above. + + -- Sergio Durigan Junior Mon, 07 Feb 2022 16:56:51 -0500 + llvm-toolchain-13 (1:13.0.1-2) unstable; urgency=medium * mlir: use the cmake option to avoid installing object files @@ -2674,6 +2722,38 @@ -- Sylvestre Ledru Wed, 02 Jan 2019 12:37:45 +0100 +llvm-toolchain-snapshot (1:8~svn346586-1~exp1) experimental; urgency=medium + + * New snapshot release + * Also install libOptRemarks.so + * Merge all the recent 7 changes into snapshot + (Closes: #913058) the co install issue with libc++ & openmp + + -- Sylvestre Ledru Sat, 10 Nov 2018 15:14:15 +0100 + +llvm-toolchain-snapshot (1:8~svn345569-1~exp1) experimental; urgency=medium + + [ Sylvestre Ledru ] + * Remove bat files https://bugs.llvm.org/show_bug.cgi?id=30755 + * Fix the autopkgtest script (no gcc in the test) + * remove dep from lld to llvm-8-dev because lld + doesn't use LLVM LTO + * remove old Replaces/Breaks + * Standards-Version: 4.2.1 + * Backport a fix to improve scan-build code error. + Thanks to Roman Lebedev for the fix(Closes: #909662) + * Remove bat files https://bugs.llvm.org/show_bug.cgi?id=30755 + * Install bash-completion for clang + * Disable ocaml on armel + + [ Gianfranco Costamagna ] + * Take option two in bug #877567 to fix FTBFS on mips and mipsel + + [ Sylvestre Ledru ] + * New snapshot release + + -- Sylvestre Ledru Tue, 30 Oct 2018 08:31:14 +0100 + llvm-toolchain-7 (1:7.0.1-4) unstable; urgency=medium * New snapshot release @@ -5261,3 +5341,4 @@ Thanks to Matthias Klose. -- Sylvestre Ledru Sat, 09 Feb 2013 12:14:10 +0100 + diff -Nru llvm-toolchain-13-13.0.1/debian/control llvm-toolchain-13-13.0.1/debian/control --- llvm-toolchain-13-13.0.1/debian/control 2022-02-05 11:12:03.000000000 +0100 +++ llvm-toolchain-13-13.0.1/debian/control 2022-05-25 10:33:07.000000000 +0200 @@ -2,7 +2,8 @@ Section: devel Priority: optional Rules-Requires-Root: no -Maintainer: LLVM Packaging Team +Maintainer: Ubuntu Developers +XSBC-Original-Maintainer: LLVM Packaging Team Uploaders: Sylvestre Ledru , Gianfranco Costamagna Build-Depends: debhelper (>= 10.0), cmake, ninja-build, chrpath, texinfo, sharutils, @@ -24,7 +25,7 @@ libpfm4-dev [linux-any], python3-setuptools, libz3-dev, llvm-spirv [ amd64 arm64 armel armhf mips64el mipsel ppc64el s390x ] | hello [!i386], spirv-tools [ linux-any ] | hello [ !i386], - libgrpc++-dev, libprotobuf-dev, protobuf-compiler, protobuf-compiler-grpc + libgrpc++-dev [!i386], libprotobuf-dev [!i386], protobuf-compiler [!i386], protobuf-compiler-grpc [!i386] # "| hello" is for older buster/bionic distros without spirv support Build-Conflicts: oprofile Standards-Version: 4.2.1 @@ -150,6 +151,8 @@ Depends: ${shlibs:Depends}, ${misc:Depends}, ${dep:devlibs}, ${dep:devlibs-objc}, libclang1-13 (= ${binary:Version}), libclang-common-13-dev (= ${binary:Version}) +Breaks: llvm-13-dev (<< 1:13.0.1-4ubuntu1) +Replaces: llvm-13-dev (<< 1:13.0.1-4ubuntu1) Description: Clang library - Development package Clang project is a C, C++, Objective C and Objective C++ front-end based on the LLVM compiler. Its goal is to offer a replacement to the diff -Nru llvm-toolchain-13-13.0.1/debian/libclang-X.Y-dev.install.in llvm-toolchain-13-13.0.1/debian/libclang-X.Y-dev.install.in --- llvm-toolchain-13-13.0.1/debian/libclang-X.Y-dev.install.in 2022-02-13 14:08:44.000000000 +0100 +++ llvm-toolchain-13-13.0.1/debian/libclang-X.Y-dev.install.in 2022-05-25 10:59:31.000000000 +0200 @@ -1,3 +1,5 @@ +#!/usr/bin/dh-exec + usr/lib/llvm-@LLVM_VERSION@/include/clang usr/lib/llvm-@LLVM_VERSION@/include/clang-c usr/lib/llvm-@LLVM_VERSION@/include/clang-tidy @@ -7,6 +9,6 @@ usr/lib/llvm-@LLVM_VERSION@/lib/libfindAllSymbols.a # clangd -usr/lib/llvm-@LLVM_VERSION@/lib/libRemoteIndexProto.a -usr/lib/llvm-@LLVM_VERSION@/lib/libRemoteIndexServiceProto.a -usr/lib/llvm-@LLVM_VERSION@/lib/libMonitoringServiceProto.a +[!i386] usr/lib/llvm-@LLVM_VERSION@/lib/libRemoteIndexProto.a +[!i386] usr/lib/llvm-@LLVM_VERSION@/lib/libRemoteIndexServiceProto.a +[!i386] usr/lib/llvm-@LLVM_VERSION@/lib/libMonitoringServiceProto.a diff -Nru llvm-toolchain-13-13.0.1/debian/patches/llvm-objcopy-COFF-Consider-section-flags-when-adding.patch llvm-toolchain-13-13.0.1/debian/patches/llvm-objcopy-COFF-Consider-section-flags-when-adding.patch --- llvm-toolchain-13-13.0.1/debian/patches/llvm-objcopy-COFF-Consider-section-flags-when-adding.patch 1970-01-01 01:00:00.000000000 +0100 +++ llvm-toolchain-13-13.0.1/debian/patches/llvm-objcopy-COFF-Consider-section-flags-when-adding.patch 2022-03-15 14:55:55.000000000 +0100 @@ -0,0 +1,128 @@ +From cdd407286a9652ec62b33f437a298754fe3ba7ab Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Alfonso=20S=C3=A1nchez-Beato?= + +Date: Wed, 25 Aug 2021 23:03:32 +0300 +Subject: [PATCH] [llvm-objcopy] [COFF] Consider section flags when adding + section + +The --set-section-flags option was being ignored when adding a new +section. Take it into account if present. + +Fixes https://llvm.org/PR51244 + +Reviewed By: jhenderson, MaskRay + +Differential Revision: https://reviews.llvm.org/D106942 +--- + .../COFF/add-section-and-set-flags.test | 36 +++++++++++++++++++ + llvm/tools/llvm-objcopy/COFF/COFFObjcopy.cpp | 19 ++++++---- + 2 files changed, 49 insertions(+), 6 deletions(-) + create mode 100644 llvm/test/tools/llvm-objcopy/COFF/add-section-and-set-flags.test + +diff --git a/llvm/test/tools/llvm-objcopy/COFF/add-section-and-set-flags.test b/llvm/test/tools/llvm-objcopy/COFF/add-section-and-set-flags.test +new file mode 100644 +index 000000000000..b5fdcb8f6624 +--- /dev/null ++++ b/llvm/test/tools/llvm-objcopy/COFF/add-section-and-set-flags.test +@@ -0,0 +1,36 @@ ++# RUN: yaml2obj %s -o %t ++ ++## Test that llvm-objcopy can add sections and set its flags in the same ++## call. ++# RUN: echo DEADBEEF > %t.sec ++# RUN: llvm-objcopy --set-section-flags=.test.section1=code --add-section=.test.section1=%t.sec --set-section-flags=.test.section2=data --add-section=.test.section2=%t.sec %t %t1 ++# RUN: llvm-readobj --sections --section-data %t1 | FileCheck %s ++ ++# CHECK: Name: .test.section1 ++# CHECK-NEXT: VirtualSize: 0x9 ++# CHECK-NEXT: VirtualAddress: 0x0 ++# CHECK-NEXT: RawDataSize: 9 ++# CHECK: Characteristics [ ++# CHECK-NEXT: IMAGE_SCN_CNT_CODE ++# CHECK-NEXT: IMAGE_SCN_MEM_EXECUTE ++# CHECK-NEXT: IMAGE_SCN_MEM_READ ++# CHECK-NEXT: IMAGE_SCN_MEM_WRITE ++# CHECK-NEXT: ] ++ ++# CHECK: Name: .test.section2 ++# CHECK-NEXT: VirtualSize: 0x9 ++# CHECK-NEXT: VirtualAddress: 0x9 ++# CHECK-NEXT: RawDataSize: 9 ++# CHECK: Characteristics [ ++# CHECK-NEXT: IMAGE_SCN_CNT_INITIALIZED_DATA ++# CHECK-NEXT: IMAGE_SCN_MEM_READ ++# CHECK-NEXT: IMAGE_SCN_MEM_WRITE ++# CHECK-NEXT: ] ++ ++--- !COFF ++header: ++ Machine: IMAGE_FILE_MACHINE_AMD64 ++ Characteristics: [ ] ++sections: ++symbols: ++... +diff --git a/llvm/tools/llvm-objcopy/COFF/COFFObjcopy.cpp b/llvm/tools/llvm-objcopy/COFF/COFFObjcopy.cpp +index e50ac2e12e2f..38c9cd09433b 100644 +--- a/llvm/tools/llvm-objcopy/COFF/COFFObjcopy.cpp ++++ b/llvm/tools/llvm-objcopy/COFF/COFFObjcopy.cpp +@@ -94,7 +94,7 @@ static Error addGnuDebugLink(Object &Obj, StringRef DebugLinkFile) { + return Error::success(); + } + +-static void setSectionFlags(Section &Sec, SectionFlag AllFlags) { ++static uint32_t flagsToCharacteristics(SectionFlag AllFlags, uint32_t OldChar) { + // Need to preserve alignment flags. + const uint32_t PreserveMask = + IMAGE_SCN_ALIGN_1BYTES | IMAGE_SCN_ALIGN_2BYTES | IMAGE_SCN_ALIGN_4BYTES | +@@ -107,8 +107,7 @@ static void setSectionFlags(Section &Sec, SectionFlag AllFlags) { + + // Setup new section characteristics based on the flags provided in command + // line. +- uint32_t NewCharacteristics = +- (Sec.Header.Characteristics & PreserveMask) | IMAGE_SCN_MEM_READ; ++ uint32_t NewCharacteristics = (OldChar & PreserveMask) | IMAGE_SCN_MEM_READ; + + if ((AllFlags & SectionFlag::SecAlloc) && !(AllFlags & SectionFlag::SecLoad)) + NewCharacteristics |= IMAGE_SCN_CNT_UNINITIALIZED_DATA; +@@ -128,7 +127,7 @@ static void setSectionFlags(Section &Sec, SectionFlag AllFlags) { + if (AllFlags & SectionFlag::SecExclude) + NewCharacteristics |= IMAGE_SCN_LNK_REMOVE; + +- Sec.Header.Characteristics = NewCharacteristics; ++ return NewCharacteristics; + } + + static Error handleArgs(const CommonConfig &Config, Object &Obj) { +@@ -226,7 +225,8 @@ static Error handleArgs(const CommonConfig &Config, Object &Obj) { + for (Section &Sec : Obj.getMutableSections()) { + const auto It = Config.SetSectionFlags.find(Sec.Name); + if (It != Config.SetSectionFlags.end()) +- setSectionFlags(Sec, It->second.NewFlags); ++ Sec.Header.Characteristics = flagsToCharacteristics( ++ It->second.NewFlags, Sec.Header.Characteristics); + } + + for (const auto &Flag : Config.AddSection) { +@@ -238,11 +238,18 @@ static Error handleArgs(const CommonConfig &Config, Object &Obj) { + return createFileError(FileName, errorCodeToError(BufOrErr.getError())); + auto Buf = std::move(*BufOrErr); + ++ uint32_t Characteristics; ++ const auto It = Config.SetSectionFlags.find(SecName); ++ if (It != Config.SetSectionFlags.end()) ++ Characteristics = flagsToCharacteristics(It->second.NewFlags, 0); ++ else ++ Characteristics = IMAGE_SCN_CNT_INITIALIZED_DATA | IMAGE_SCN_ALIGN_1BYTES; ++ + addSection( + Obj, SecName, + makeArrayRef(reinterpret_cast(Buf->getBufferStart()), + Buf->getBufferSize()), +- IMAGE_SCN_CNT_INITIALIZED_DATA | IMAGE_SCN_ALIGN_1BYTES); ++ Characteristics); + } + + if (!Config.AddGnuDebugLink.empty()) +-- +2.25.1 + diff -Nru llvm-toolchain-13-13.0.1/debian/patches/llvm-objcopy-COFF-Fix-test-for-debug-dir-presence.patch llvm-toolchain-13-13.0.1/debian/patches/llvm-objcopy-COFF-Fix-test-for-debug-dir-presence.patch --- llvm-toolchain-13-13.0.1/debian/patches/llvm-objcopy-COFF-Fix-test-for-debug-dir-presence.patch 1970-01-01 01:00:00.000000000 +0100 +++ llvm-toolchain-13-13.0.1/debian/patches/llvm-objcopy-COFF-Fix-test-for-debug-dir-presence.patch 2022-03-15 14:55:55.000000000 +0100 @@ -0,0 +1,124 @@ +From b25ab4f313f38d3dee9674789cf56b9143515034 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Alfonso=20S=C3=A1nchez-Beato?= + +Date: Fri, 10 Sep 2021 09:55:26 +0100 +Subject: [PATCH] [llvm-objcopy][COFF] Fix test for debug dir presence + +If the number of directories was 6 (equal to the DEBUG_DIRECTORY +index), patchDebugDirectory() was run even though the debug directory +is actually the 7th entry. Use <= in the comparison to fix that. + +This fixes https://llvm.org/PR51243 + +Differential Revision: https://reviews.llvm.org/D106940 + +Reviewed by: jhenderson +--- + .../COFF/check-debug-dir-present.test | 81 +++++++++++++++++++ + llvm/tools/llvm-objcopy/COFF/Writer.cpp | 2 +- + 2 files changed, 82 insertions(+), 1 deletion(-) + create mode 100644 llvm/test/tools/llvm-objcopy/COFF/check-debug-dir-present.test + +diff --git a/llvm/test/tools/llvm-objcopy/COFF/check-debug-dir-present.test b/llvm/test/tools/llvm-objcopy/COFF/check-debug-dir-present.test +new file mode 100644 +index 000000000000..7fd10486b585 +--- /dev/null ++++ b/llvm/test/tools/llvm-objcopy/COFF/check-debug-dir-present.test +@@ -0,0 +1,81 @@ ++## We check that we copy sections to an image in the case when there are ++## exactly 6 directory entries. ++# RUN: yaml2obj --docnum=1 %s -o %t ++# RUN: llvm-objcopy --add-section new_sect=%t %t %t1 ++# RUN: obj2yaml %t1 | FileCheck %s ++ ++# CHECK: NumberOfRvaAndSize: 6 ++# CHECK-NEXT: ExportTable: ++# CHECK-NEXT: RelativeVirtualAddress: 0 ++# CHECK-NEXT: Size: 0 ++# CHECK-NEXT: ImportTable: ++# CHECK-NEXT: RelativeVirtualAddress: 0 ++# CHECK-NEXT: Size: 0 ++# CHECK-NEXT: ResourceTable: ++# CHECK-NEXT: RelativeVirtualAddress: 0 ++# CHECK-NEXT: Size: 0 ++# CHECK-NEXT: ExceptionTable: ++# CHECK-NEXT: RelativeVirtualAddress: 0 ++# CHECK-NEXT: Size: 0 ++# CHECK-NEXT: CertificateTable: ++# CHECK-NEXT: RelativeVirtualAddress: 0 ++# CHECK-NEXT: Size: 0 ++# CHECK-NEXT: BaseRelocationTable: ++# CHECK-NEXT: RelativeVirtualAddress: 0 ++# CHECK-NEXT: Size: 0 ++# CHECK: sections: ++# CHECK-NEXT: - Name: foo ++# CHECK-NEXT: Characteristics: [ ] ++# CHECK-NEXT: Alignment: 4 ++# CHECK-NEXT: SectionData: '' ++# CHECK-NEXT: - Name: new_sect ++# CHECK-NEXT: Characteristics: [ IMAGE_SCN_CNT_INITIALIZED_DATA ] ++# CHECK-NEXT: Alignment: 1 ++# CHECK-NEXT: SectionData: '' ++ ++--- !COFF ++OptionalHeader: ++ AddressOfEntryPoint: 4096 ++ ImageBase: 0 ++ SectionAlignment: 4096 ++ FileAlignment: 512 ++ MajorOperatingSystemVersion: 0 ++ MinorOperatingSystemVersion: 0 ++ MajorImageVersion: 0 ++ MinorImageVersion: 0 ++ MajorSubsystemVersion: 0 ++ MinorSubsystemVersion: 0 ++ Subsystem: IMAGE_SUBSYSTEM_EFI_APPLICATION ++ DLLCharacteristics: [ ] ++ SizeOfStackReserve: 0 ++ SizeOfStackCommit: 0 ++ SizeOfHeapReserve: 0 ++ SizeOfHeapCommit: 0 ++ NumberOfRvaAndSize: 6 ++ ExportTable: ++ RelativeVirtualAddress: 0 ++ Size: 0 ++ ImportTable: ++ RelativeVirtualAddress: 0 ++ Size: 0 ++ ResourceTable: ++ RelativeVirtualAddress: 0 ++ Size: 0 ++ ExceptionTable: ++ RelativeVirtualAddress: 0 ++ Size: 0 ++ CertificateTable: ++ RelativeVirtualAddress: 0 ++ Size: 0 ++ BaseRelocationTable: ++ RelativeVirtualAddress: 0 ++ Size: 0 ++header: ++ Machine: IMAGE_FILE_MACHINE_AMD64 ++ Characteristics: [ ] ++sections: ++ - Name: foo ++ Characteristics: [ ] ++ Alignment: 4 ++symbols: ++... +diff --git a/llvm/tools/llvm-objcopy/COFF/Writer.cpp b/llvm/tools/llvm-objcopy/COFF/Writer.cpp +index 8cc2312d137c..cbd0e4261238 100644 +--- a/llvm/tools/llvm-objcopy/COFF/Writer.cpp ++++ b/llvm/tools/llvm-objcopy/COFF/Writer.cpp +@@ -406,7 +406,7 @@ Expected COFFWriter::virtualAddressToFileAddress(uint32_t RVA) { + // the debug_directory structs in there, and set the PointerToRawData field + // in all of them, according to their new physical location in the file. + Error COFFWriter::patchDebugDirectory() { +- if (Obj.DataDirectories.size() < DEBUG_DIRECTORY) ++ if (Obj.DataDirectories.size() <= DEBUG_DIRECTORY) + return Error::success(); + const data_directory *Dir = &Obj.DataDirectories[DEBUG_DIRECTORY]; + if (Dir->Size <= 0) +-- +2.25.1 + diff -Nru llvm-toolchain-13-13.0.1/debian/patches/risc/riscv-insn-support.patch llvm-toolchain-13-13.0.1/debian/patches/risc/riscv-insn-support.patch --- llvm-toolchain-13-13.0.1/debian/patches/risc/riscv-insn-support.patch 1970-01-01 01:00:00.000000000 +0100 +++ llvm-toolchain-13-13.0.1/debian/patches/risc/riscv-insn-support.patch 2022-05-25 11:58:40.000000000 +0200 @@ -0,0 +1,566 @@ +From d5ea5842d627e63f780b524dddf67dac7222779c Mon Sep 17 00:00:00 2001 +From: Craig Topper +Date: Sun, 12 Sep 2021 13:45:52 -0700 +Origin: upstream + rustc: https://github.com/rust-lang/llvm-project/pull/121 +Bug-Ubuntu: https://bugs.launchpad.net/ubuntu/+source/llvm-toolchain-13/+bug/1973041 +Applied-Upstream: from version 14.0.0-rc1 +Subject: [PATCH] [RISCV] Initial support .insn directive for the assembler. + +This allows for a custom encoding to be emitted. It can also be +used with inline assembly to allow the custom instruction to be +register allocated like other instructions. + +I initially started from SystemZ's implementation, but some of +the formats allow operands to be specified in multiple ways so I +had to add support for matching different operand class lists for +the same format. That implementation is a simplified version of +what is emitted by tablegen for regular instructions. + +I've left out the compressed formats. And I haven't supported the +named opcodes like LUI or OP_IMM_32. Those can be added in future +patches. + +Documentation can be found here https://sourceware.org/binutils/docs-2.37/as/RISC_002dV_002dFormats.html + +Reviewed By: jrtc27, MaskRay + +Differential Revision: https://reviews.llvm.org/D108602 +--- + .../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 63 ++++++++- + .../Target/RISCV/MCTargetDesc/RISCVBaseInfo.h | 5 +- + .../RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp | 2 +- + llvm/lib/Target/RISCV/RISCVInstrFormats.td | 132 ++++++++++++++++++ + llvm/lib/Target/RISCV/RISCVInstrInfo.td | 102 ++++++++++++++ + llvm/lib/Target/RISCV/RISCVRegisterInfo.td | 12 ++ + llvm/test/MC/RISCV/insn-invalid.s | 17 +++ + llvm/test/MC/RISCV/insn.s | 77 ++++++++++ + 8 files changed, 407 insertions(+), 3 deletions(-) + create mode 100644 llvm/test/MC/RISCV/insn-invalid.s + create mode 100644 llvm/test/MC/RISCV/insn.s + +diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +index 87496e0b9330f..ff2841a50d2d3 100644 +--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp ++++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +@@ -169,6 +169,7 @@ class RISCVAsmParser : public MCTargetAsmParser { + + bool parseDirectiveOption(); + bool parseDirectiveAttribute(); ++ bool parseDirectiveInsn(SMLoc L); + + void setFeatureBits(uint64_t Feature, StringRef FeatureString) { + if (!(getSTI().getFeatureBits()[Feature])) { +@@ -504,6 +505,24 @@ struct RISCVOperand : public MCParsedAsmOperand { + return (isRV64() && isUInt<5>(Imm)) || isUInt<4>(Imm); + } + ++ bool isUImm2() const { ++ int64_t Imm; ++ RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; ++ if (!isImm()) ++ return false; ++ bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); ++ return IsConstantImm && isUInt<2>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; ++ } ++ ++ bool isUImm3() const { ++ int64_t Imm; ++ RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; ++ if (!isImm()) ++ return false; ++ bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); ++ return IsConstantImm && isUInt<3>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; ++ } ++ + bool isUImm5() const { + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; +@@ -513,6 +532,15 @@ struct RISCVOperand : public MCParsedAsmOperand { + return IsConstantImm && isUInt<5>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; + } + ++ bool isUImm7() const { ++ int64_t Imm; ++ RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; ++ if (!isImm()) ++ return false; ++ bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); ++ return IsConstantImm && isUInt<7>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; ++ } ++ + bool isSImm5() const { + if (!isImm()) + return false; +@@ -1835,8 +1863,10 @@ bool RISCVAsmParser::ParseDirective(AsmToken DirectiveID) { + + if (IDVal == ".option") + return parseDirectiveOption(); +- else if (IDVal == ".attribute") ++ if (IDVal == ".attribute") + return parseDirectiveAttribute(); ++ if (IDVal == ".insn") ++ return parseDirectiveInsn(DirectiveID.getLoc()); + + return true; + } +@@ -2200,6 +2230,37 @@ bool RISCVAsmParser::parseDirectiveAttribute() { + return false; + } + ++/// parseDirectiveInsn ++/// ::= .insn [ format encoding, (operands (, operands)*) ] ++bool RISCVAsmParser::parseDirectiveInsn(SMLoc L) { ++ MCAsmParser &Parser = getParser(); ++ ++ // Expect instruction format as identifier. ++ StringRef Format; ++ SMLoc ErrorLoc = Parser.getTok().getLoc(); ++ if (Parser.parseIdentifier(Format)) ++ return Error(ErrorLoc, "expected instruction format"); ++ ++ if (Format != "r" && Format != "r4" && Format != "i" && Format != "b" && ++ Format != "sb" && Format != "u" && Format != "j" && Format != "uj" && ++ Format != "s") ++ return Error(ErrorLoc, "invalid instruction format"); ++ ++ std::string FormatName = (".insn_" + Format).str(); ++ ++ ParseInstructionInfo Info; ++ SmallVector, 8> Operands; ++ ++ if (ParseInstruction(Info, FormatName, L, Operands)) ++ return true; ++ ++ unsigned Opcode; ++ uint64_t ErrorInfo; ++ return MatchAndEmitInstruction(L, Opcode, Operands, Parser.getStreamer(), ++ ErrorInfo, ++ /*MatchingInlineAsm=*/false); ++} ++ + void RISCVAsmParser::emitToStreamer(MCStreamer &S, const MCInst &Inst) { + MCInst CInst; + bool Res = compressInst(CInst, Inst, getSTI(), S.getContext()); +diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h +index 9bdd2003cb15d..b837c4e25270b 100644 +--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h ++++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h +@@ -158,8 +158,11 @@ enum { + namespace RISCVOp { + enum OperandType : unsigned { + OPERAND_FIRST_RISCV_IMM = MCOI::OPERAND_FIRST_TARGET, +- OPERAND_UIMM4 = OPERAND_FIRST_RISCV_IMM, ++ OPERAND_UIMM2 = OPERAND_FIRST_RISCV_IMM, ++ OPERAND_UIMM3, ++ OPERAND_UIMM4, + OPERAND_UIMM5, ++ OPERAND_UIMM7, + OPERAND_UIMM12, + OPERAND_SIMM12, + OPERAND_UIMM20, +diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp +index 1ef276b101003..14d0191a505fc 100644 +--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp ++++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp +@@ -358,7 +358,7 @@ unsigned RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo, + } + } else if (Kind == MCExpr::SymbolRef && + cast(Expr)->getKind() == MCSymbolRefExpr::VK_None) { +- if (Desc.getOpcode() == RISCV::JAL) { ++ if (MIFrm == RISCVII::InstFormatJ) { + FixupKind = RISCV::fixup_riscv_jal; + } else if (MIFrm == RISCVII::InstFormatB) { + FixupKind = RISCV::fixup_riscv_branch; +diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td +index 8e9d245f13eb0..944650c870b62 100644 +--- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td ++++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td +@@ -406,3 +406,135 @@ class RVInstJ ++ : RVInst { ++ bits<7> opcode; ++ bits<7> funct7; ++ bits<3> funct3; ++ ++ bits<5> rs2; ++ bits<5> rs1; ++ bits<5> rd; ++ ++ let Inst{31-25} = funct7; ++ let Inst{24-20} = rs2; ++ let Inst{19-15} = rs1; ++ let Inst{14-12} = funct3; ++ let Inst{11-7} = rd; ++ let Opcode = opcode; ++ ++ let AsmString = ".insn r " # argstr; ++} ++ ++class DirectiveInsnR4 ++ : RVInst { ++ bits<7> opcode; ++ bits<2> funct2; ++ bits<3> funct3; ++ ++ bits<5> rs3; ++ bits<5> rs2; ++ bits<5> rs1; ++ bits<5> rd; ++ ++ let Inst{31-27} = rs3; ++ let Inst{26-25} = funct2; ++ let Inst{24-20} = rs2; ++ let Inst{19-15} = rs1; ++ let Inst{14-12} = funct3; ++ let Inst{11-7} = rd; ++ let Opcode = opcode; ++ ++ let AsmString = ".insn r4 " # argstr; ++} ++ ++class DirectiveInsnI ++ : RVInst { ++ bits<7> opcode; ++ bits<3> funct3; ++ ++ bits<12> imm12; ++ bits<5> rs1; ++ bits<5> rd; ++ ++ let Inst{31-20} = imm12; ++ let Inst{19-15} = rs1; ++ let Inst{14-12} = funct3; ++ let Inst{11-7} = rd; ++ let Opcode = opcode; ++ ++ let AsmString = ".insn i " # argstr; ++} ++ ++class DirectiveInsnS ++ : RVInst { ++ bits<7> opcode; ++ bits<3> funct3; ++ ++ bits<12> imm12; ++ bits<5> rs2; ++ bits<5> rs1; ++ ++ let Inst{31-25} = imm12{11-5}; ++ let Inst{24-20} = rs2; ++ let Inst{19-15} = rs1; ++ let Inst{14-12} = funct3; ++ let Inst{11-7} = imm12{4-0}; ++ let Opcode = opcode; ++ ++ let AsmString = ".insn s " # argstr; ++} ++ ++class DirectiveInsnB ++ : RVInst { ++ bits<7> opcode; ++ bits<3> funct3; ++ ++ bits<12> imm12; ++ bits<5> rs2; ++ bits<5> rs1; ++ ++ let Inst{31} = imm12{11}; ++ let Inst{30-25} = imm12{9-4}; ++ let Inst{24-20} = rs2; ++ let Inst{19-15} = rs1; ++ let Inst{14-12} = funct3; ++ let Inst{11-8} = imm12{3-0}; ++ let Inst{7} = imm12{10}; ++ let Opcode = opcode; ++ ++ let AsmString = ".insn b " # argstr; ++} ++ ++class DirectiveInsnU ++ : RVInst { ++ bits<7> opcode; ++ ++ bits<20> imm20; ++ bits<5> rd; ++ ++ let Inst{31-12} = imm20; ++ let Inst{11-7} = rd; ++ let Opcode = opcode; ++ ++ let AsmString = ".insn u " # argstr; ++} ++ ++class DirectiveInsnJ ++ : RVInst { ++ bits<7> opcode; ++ ++ bits<20> imm20; ++ bits<5> rd; ++ ++ let Inst{31-12} = imm20; ++ let Inst{11-7} = rd; ++ let Opcode = opcode; ++ ++ let AsmString = ".insn j " # argstr; ++} +diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td +index 949fff25e9e0a..1d6e4f04fce49 100644 +--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td ++++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td +@@ -152,6 +152,20 @@ def uimmlog2xlen : Operand, ImmLeaf { ++ let ParserMatchClass = UImmAsmOperand<2>; ++ let DecoderMethod = "decodeUImmOperand<2>"; ++ let OperandType = "OPERAND_UIMM2"; ++ let OperandNamespace = "RISCVOp"; ++} ++ ++def uimm3 : Operand { ++ let ParserMatchClass = UImmAsmOperand<3>; ++ let DecoderMethod = "decodeUImmOperand<3>"; ++ let OperandType = "OPERAND_UIMM3"; ++ let OperandNamespace = "RISCVOp"; ++} ++ + def uimm5 : Operand, ImmLeaf(Imm);}]> { + let ParserMatchClass = UImmAsmOperand<5>; + let DecoderMethod = "decodeUImmOperand<5>"; +@@ -159,6 +173,13 @@ def uimm5 : Operand, ImmLeaf(Imm);}]> { + let OperandNamespace = "RISCVOp"; + } + ++def uimm7 : Operand { ++ let ParserMatchClass = UImmAsmOperand<7>; ++ let DecoderMethod = "decodeUImmOperand<7>"; ++ let OperandType = "OPERAND_UIMM7"; ++ let OperandNamespace = "RISCVOp"; ++} ++ + def simm12 : Operand, ImmLeaf(Imm);}]> { + let ParserMatchClass = SImmAsmOperand<12>; + let EncoderMethod = "getImmOpValue"; +@@ -848,6 +869,87 @@ def : MnemonicAlias<"sbreak", "ebreak">; + // that don't support this alias. + def : InstAlias<"zext.b $rd, $rs", (ANDI GPR:$rd, GPR:$rs, 0xFF), 0>; + ++//===----------------------------------------------------------------------===// ++// .insn directive instructions ++//===----------------------------------------------------------------------===// ++ ++// isCodeGenOnly = 1 to hide them from the tablegened assembly parser. ++let isCodeGenOnly = 1, hasSideEffects = 1, mayLoad = 1, mayStore = 1, ++ hasNoSchedulingInfo = 1 in { ++def InsnR : DirectiveInsnR<(outs AnyReg:$rd), (ins uimm7:$opcode, uimm3:$funct3, ++ uimm7:$funct7, AnyReg:$rs1, ++ AnyReg:$rs2), ++ "$opcode, $funct3, $funct7, $rd, $rs1, $rs2">; ++def InsnR4 : DirectiveInsnR4<(outs AnyReg:$rd), (ins uimm7:$opcode, ++ uimm3:$funct3, ++ uimm2:$funct2, ++ AnyReg:$rs1, AnyReg:$rs2, ++ AnyReg:$rs3), ++ "$opcode, $funct3, $funct2, $rd, $rs1, $rs2, $rs3">; ++def InsnI : DirectiveInsnI<(outs AnyReg:$rd), (ins uimm7:$opcode, uimm3:$funct3, ++ AnyReg:$rs1, simm12:$imm12), ++ "$opcode, $funct3, $rd, $rs1, $imm12">; ++def InsnI_Mem : DirectiveInsnI<(outs AnyReg:$rd), (ins uimm7:$opcode, ++ uimm3:$funct3, ++ AnyReg:$rs1, ++ simm12:$imm12), ++ "$opcode, $funct3, $rd, ${imm12}(${rs1})">; ++def InsnB : DirectiveInsnB<(outs), (ins uimm7:$opcode, uimm3:$funct3, ++ AnyReg:$rs1, AnyReg:$rs2, ++ simm13_lsb0:$imm12), ++ "$opcode, $funct3, $rs1, $rs2, $imm12">; ++def InsnU : DirectiveInsnU<(outs AnyReg:$rd), (ins uimm7:$opcode, ++ uimm20_lui:$imm20), ++ "$opcode, $rd, $imm20">; ++def InsnJ : DirectiveInsnJ<(outs AnyReg:$rd), (ins uimm7:$opcode, ++ simm21_lsb0_jal:$imm20), ++ "$opcode, $rd, $imm20">; ++def InsnS : DirectiveInsnS<(outs), (ins uimm7:$opcode, uimm3:$funct3, ++ AnyReg:$rs2, AnyReg:$rs1, ++ simm12:$imm12), ++ "$opcode, $funct3, $rs2, ${imm12}(${rs1})">; ++} ++ ++// Use InstAliases to match these so that we can combine the insn and format ++// into a mnemonic to use as the key for the tablegened asm matcher table. The ++// parser will take care of creating these fake mnemonics and will only do it ++// for known formats. ++let EmitPriority = 0 in { ++def : InstAlias<".insn_r $opcode, $funct3, $funct7, $rd, $rs1, $rs2", ++ (InsnR AnyReg:$rd, uimm7:$opcode, uimm3:$funct3, uimm7:$funct7, ++ AnyReg:$rs1, AnyReg:$rs2)>; ++// Accept 4 register form of ".insn r" as alias for ".insn r4". ++def : InstAlias<".insn_r $opcode, $funct3, $funct7, $rd, $rs1, $rs2, $rs3", ++ (InsnR4 AnyReg:$rd, uimm7:$opcode, uimm3:$funct3, uimm7:$funct7, ++ AnyReg:$rs1, AnyReg:$rs2, AnyReg:$rs3)>; ++def : InstAlias<".insn_r4 $opcode, $funct3, $funct7, $rd, $rs1, $rs2, $rs3", ++ (InsnR4 AnyReg:$rd, uimm7:$opcode, uimm3:$funct3, uimm7:$funct7, ++ AnyReg:$rs1, AnyReg:$rs2, AnyReg:$rs3)>; ++def : InstAlias<".insn_i $opcode, $funct3, $rd, $rs1, $imm12", ++ (InsnI AnyReg:$rd, uimm7:$opcode, uimm3:$funct3, AnyReg:$rs1, ++ simm12:$imm12)>; ++def : InstAlias<".insn_i $opcode, $funct3, $rd, ${imm12}(${rs1})", ++ (InsnI_Mem AnyReg:$rd, uimm7:$opcode, uimm3:$funct3, ++ AnyReg:$rs1, simm12:$imm12)>; ++def : InstAlias<".insn_b $opcode, $funct3, $rs1, $rs2, $imm12", ++ (InsnB uimm7:$opcode, uimm3:$funct3, AnyReg:$rs1, ++ AnyReg:$rs2, simm13_lsb0:$imm12)>; ++// Accept sb as an alias for b. ++def : InstAlias<".insn_sb $opcode, $funct3, $rs1, $rs2, $imm12", ++ (InsnB uimm7:$opcode, uimm3:$funct3, AnyReg:$rs1, ++ AnyReg:$rs2, simm13_lsb0:$imm12)>; ++def : InstAlias<".insn_u $opcode, $rd, $imm20", ++ (InsnU AnyReg:$rd, uimm7:$opcode, uimm20_lui:$imm20)>; ++def : InstAlias<".insn_j $opcode, $rd, $imm20", ++ (InsnJ AnyReg:$rd, uimm7:$opcode, simm21_lsb0_jal:$imm20)>; ++// Accept uj as an alias for j. ++def : InstAlias<".insn_uj $opcode, $rd, $imm20", ++ (InsnJ AnyReg:$rd, uimm7:$opcode, simm21_lsb0_jal:$imm20)>; ++def : InstAlias<".insn_s $opcode, $funct3, $rs2, ${imm12}(${rs1})", ++ (InsnS uimm7:$opcode, uimm3:$funct3, AnyReg:$rs2, ++ AnyReg:$rs1, simm12:$imm12)>; ++} ++ + //===----------------------------------------------------------------------===// + // Pseudo-instructions and codegen patterns + // +diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td +index fde75206889c8..4dbeb61c48159 100644 +--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td ++++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td +@@ -557,3 +557,15 @@ foreach m = LMULList.m in { + def FFLAGS : RISCVReg<0, "fflags">; + def FRM : RISCVReg<0, "frm">; + def FCSR : RISCVReg<0, "fcsr">; ++ ++// Any type register. Used for .insn directives when we don't know what the ++// register types could be. ++// NOTE: The alignment and size are bogus values. The Size needs to be non-zero ++// or tablegen will use "untyped" to determine the size which will assert. ++let isAllocatable = 0 in ++def AnyReg : RegisterClass<"RISCV", [untyped], 32, ++ (add (sequence "X%u", 0, 31), ++ (sequence "F%u_D", 0, 31), ++ (sequence "V%u", 0, 31))> { ++ let Size = 32; ++} +diff --git a/llvm/test/MC/RISCV/insn-invalid.s b/llvm/test/MC/RISCV/insn-invalid.s +new file mode 100644 +index 0000000000000..5d7eaf69f01dc +--- /dev/null ++++ b/llvm/test/MC/RISCV/insn-invalid.s +@@ -0,0 +1,17 @@ ++# RUN: not llvm-mc -triple riscv32 < %s 2>&1 | FileCheck %s ++ ++# Too many operands ++.insn i 0x13, 0, a0, a1, 13, 14 # CHECK: :[[@LINE]]:33: error: invalid operand for instruction ++.insn r 0x43, 0, 0, fa0, fa1, fa2, fa3, fa4 # CHECK: :[[@LINE]]:44: error: invalid operand for instruction ++ ++# Too few operands ++.insn r 0x33, 0, 0, a0, a1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction ++.insn i 0x13, 0, a0, a1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction ++ ++.insn r 0x33, 0, 0, a0, 13 # CHECK: :[[@LINE]]:28: error: invalid operand for instruction ++.insn i 0x13, 0, a0, a1, a2 # CHECK: :[[@LINE]]:28: error: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047] ++ ++.insn q 0x13, 0, a0, a1, 13, 14 # CHECK: :[[@LINE]]:7: error: invalid instruction format ++ ++# Make fake mnemonics we use to match these in the tablegened asm match table isn't exposed. ++.insn_i 0x13, 0, a0, a1, 13, 14 # CHECK: :[[@LINE]]:1: error: unknown directive +diff --git a/llvm/test/MC/RISCV/insn.s b/llvm/test/MC/RISCV/insn.s +new file mode 100644 +index 0000000000000..1e02e22f965ad +--- /dev/null ++++ b/llvm/test/MC/RISCV/insn.s +@@ -0,0 +1,77 @@ ++# RUN: llvm-mc %s -triple=riscv32 -mattr=+f -riscv-no-aliases -show-encoding \ ++# RUN: | FileCheck -check-prefixes=CHECK-ASM %s ++# RUN: llvm-mc %s -triple riscv64 -mattr=+f -riscv-no-aliases -show-encoding \ ++# RUN: | FileCheck -check-prefixes=CHECK-ASM %s ++# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+f < %s \ ++# RUN: | llvm-objdump --mattr=+f -M no-aliases -d -r - \ ++# RUN: | FileCheck -check-prefixes=CHECK-OBJ %s ++# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+f < %s \ ++# RUN: | llvm-objdump --mattr=+f -M no-aliases -d -r - \ ++# RUN: | FileCheck -check-prefixes=CHECK-OBJ %s ++ ++target: ++ ++# CHECK-ASM: .insn r 51, 0, 0, a0, a1, a2 ++# CHECK-ASM: encoding: [0x33,0x85,0xc5,0x00] ++# CHECK-OBJ: add a0, a1, a2 ++.insn r 0x33, 0, 0, a0, a1, a2 ++ ++# CHECK-ASM: .insn i 19, 0, a0, a1, 13 ++# CHECK-ASM: encoding: [0x13,0x85,0xd5,0x00] ++# CHECK-OBJ: addi a0, a1, 13 ++.insn i 0x13, 0, a0, a1, 13 ++ ++# CHECK-ASM: .insn i 103, 0, a0, 10(a1) ++# CHECK-ASM: encoding: [0x67,0x85,0xa5,0x00] ++# CHECK-OBJ: jalr a0, 10(a1) ++.insn i 0x67, 0, a0, 10(a1) ++ ++# CHECK-ASM: .insn i 3, 0, a0, 4(a1) ++# CHECK-ASM: encoding: [0x03,0x85,0x45,0x00] ++# CHECK-OBJ: lb a0, 4(a1) ++.insn i 0x3, 0, a0, 4(a1) ++ ++# CHECK-ASM: .insn b 99, 0, a0, a1, target ++# CHECK-ASM: [0x63'A',A,0xb5'A',A] ++# CHECK-OBJ: beq a0, a1, 0x0 ++.insn sb 0x63, 0, a0, a1, target ++ ++# CHECK-ASM: .insn b 99, 0, a0, a1, target ++# CHECK-ASM: [0x63'A',A,0xb5'A',A] ++# CHECK-OBJ: beq a0, a1, 0x0 ++.insn b 0x63, 0, a0, a1, target ++ ++# CHECK-ASM: .insn s 35, 0, a0, 4(a1) ++# CHECK-ASM: encoding: [0x23,0x82,0xa5,0x00] ++# CHECK-OBJ: sb a0, 4(a1) ++.insn s 0x23, 0, a0, 4(a1) ++ ++# CHECK-ASM: .insn u 55, a0, 4095 ++# CHECK-ASM: encoding: [0x37,0xf5,0xff,0x00] ++# CHECK-OBJ: lui a0, 4095 ++.insn u 0x37, a0, 0xfff ++ ++# CHECK-ASM: .insn j 111, a0, target ++# CHECK-ASM: encoding: [0x6f,0bAAAA0101,A,A] ++# CHECK-OBJ: jal a0, 0x0 ++.insn uj 0x6f, a0, target ++ ++# CHECK-ASM: .insn j 111, a0, target ++# CHECK-ASM: encoding: [0x6f,0bAAAA0101,A,A] ++# CHECK-OBJ: jal a0, 0x0 ++.insn j 0x6f, a0, target ++ ++# CHECK-ASM: .insn r4 67, 0, 0, fa0, fa1, fa2, fa3 ++# CHECK-ASM: encoding: [0x43,0x85,0xc5,0x68] ++# CHECK-OBJ: fmadd.s fa0, fa1, fa2, fa3, rne ++.insn r 0x43, 0, 0, fa0, fa1, fa2, fa3 ++ ++# CHECK-ASM: .insn r4 67, 0, 0, fa0, fa1, fa2, fa3 ++# CHECK-ASM: encoding: [0x43,0x85,0xc5,0x68] ++# CHECK-OBJ: fmadd.s fa0, fa1, fa2, fa3, rne ++.insn r4 0x43, 0, 0, fa0, fa1, fa2, fa3 ++ ++# CHECK-ASM: .insn i 3, 5, t1, -2048(t2) ++# CHECK-ASM: encoding: [0x03,0xd3,0x03,0x80] ++# CHECK-OBJ: lhu t1, -2048(t2) ++.insn i 0x3, 0x5, x6, %lo(2048)(x7) diff -Nru llvm-toolchain-13-13.0.1/debian/patches/series llvm-toolchain-13-13.0.1/debian/patches/series --- llvm-toolchain-13-13.0.1/debian/patches/series 2022-05-09 20:47:22.000000000 +0200 +++ llvm-toolchain-13-13.0.1/debian/patches/series 2022-05-25 11:53:57.000000000 +0200 @@ -119,6 +119,7 @@ # riscv64 risc/clang-riscv64-multiarch.diff +risc/riscv-insn-support.patch # sparc64 D98574.patch @@ -154,3 +155,8 @@ wasm-ld-path.diff fix-typo.diff fix-merge-MergeFunctions-scheduling.diff + +# Fix llvm-objcopy for arm64 +llvm-objcopy-COFF-Consider-section-flags-when-adding.patch +yaml2obj-COFF-Allow-variable-number-of-directories.patch +llvm-objcopy-COFF-Fix-test-for-debug-dir-presence.patch diff -Nru llvm-toolchain-13-13.0.1/debian/patches/yaml2obj-COFF-Allow-variable-number-of-directories.patch llvm-toolchain-13-13.0.1/debian/patches/yaml2obj-COFF-Allow-variable-number-of-directories.patch --- llvm-toolchain-13-13.0.1/debian/patches/yaml2obj-COFF-Allow-variable-number-of-directories.patch 1970-01-01 01:00:00.000000000 +0100 +++ llvm-toolchain-13-13.0.1/debian/patches/yaml2obj-COFF-Allow-variable-number-of-directories.patch 2022-03-15 14:55:55.000000000 +0100 @@ -0,0 +1,421 @@ +From b33fd3177229c67fe44b65fff8666a7746595daa Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Alfonso=20S=C3=A1nchez-Beato?= + +Date: Thu, 9 Sep 2021 11:14:52 +0100 +Subject: [PATCH] [yaml2obj][COFF] Allow variable number of directories + +Allow variable number of directories, as allowed by the +specification. NumberOfRvaAndSize will default to 16 if not specified, +as in the past. + +Reviewed by: jhenderson + +Differential Revision: https://reviews.llvm.org/D108825 +--- + llvm/lib/ObjectYAML/COFFEmitter.cpp | 22 +- + llvm/lib/ObjectYAML/COFFYAML.cpp | 2 + + .../yaml2obj/COFF/variable-number-rva.yaml | 296 ++++++++++++++++++ + llvm/tools/llvm-readobj/COFFDumper.cpp | 5 +- + llvm/tools/obj2yaml/coff2yaml.cpp | 2 + + 5 files changed, 316 insertions(+), 11 deletions(-) + create mode 100644 llvm/test/tools/yaml2obj/COFF/variable-number-rva.yaml + +diff --git a/llvm/lib/ObjectYAML/COFFEmitter.cpp b/llvm/lib/ObjectYAML/COFFEmitter.cpp +index 06ce93affd38..5f38ca13cfc2 100644 +--- a/llvm/lib/ObjectYAML/COFFEmitter.cpp ++++ b/llvm/lib/ObjectYAML/COFFEmitter.cpp +@@ -170,8 +170,8 @@ static bool layoutOptionalHeader(COFFParser &CP) { + unsigned PEHeaderSize = CP.is64Bit() ? sizeof(object::pe32plus_header) + : sizeof(object::pe32_header); + CP.Obj.Header.SizeOfOptionalHeader = +- PEHeaderSize + +- sizeof(object::data_directory) * (COFF::NUM_DATA_DIRECTORIES + 1); ++ PEHeaderSize + sizeof(object::data_directory) * ++ CP.Obj.OptionalHeader->Header.NumberOfRvaAndSize; + return true; + } + +@@ -397,7 +397,7 @@ static uint32_t initializeOptionalHeader(COFFParser &CP, uint16_t Magic, + Header->SizeOfStackCommit = CP.Obj.OptionalHeader->Header.SizeOfStackCommit; + Header->SizeOfHeapReserve = CP.Obj.OptionalHeader->Header.SizeOfHeapReserve; + Header->SizeOfHeapCommit = CP.Obj.OptionalHeader->Header.SizeOfHeapCommit; +- Header->NumberOfRvaAndSize = COFF::NUM_DATA_DIRECTORIES + 1; ++ Header->NumberOfRvaAndSize = CP.Obj.OptionalHeader->Header.NumberOfRvaAndSize; + return BaseOfData; + } + +@@ -458,18 +458,20 @@ static bool writeCOFF(COFFParser &CP, raw_ostream &OS) { + PEH.BaseOfData = BaseOfData; + OS.write(reinterpret_cast(&PEH), sizeof(PEH)); + } +- for (const Optional &DD : +- CP.Obj.OptionalHeader->DataDirectories) { +- if (!DD.hasValue()) { ++ for (uint32_t I = 0; I < CP.Obj.OptionalHeader->Header.NumberOfRvaAndSize; ++ ++I) { ++ const Optional *DataDirectories = ++ CP.Obj.OptionalHeader->DataDirectories; ++ uint32_t NumDataDir = sizeof(CP.Obj.OptionalHeader->DataDirectories) / ++ sizeof(Optional); ++ if (I >= NumDataDir || !DataDirectories[I].hasValue()) { + OS << zeros(uint32_t(0)); + OS << zeros(uint32_t(0)); + } else { +- OS << binary_le(DD->RelativeVirtualAddress); +- OS << binary_le(DD->Size); ++ OS << binary_le(DataDirectories[I]->RelativeVirtualAddress); ++ OS << binary_le(DataDirectories[I]->Size); + } + } +- OS << zeros(uint32_t(0)); +- OS << zeros(uint32_t(0)); + } + + assert(OS.tell() == CP.SectionTableStart); +diff --git a/llvm/lib/ObjectYAML/COFFYAML.cpp b/llvm/lib/ObjectYAML/COFFYAML.cpp +index 96069c0c590f..5a85e22e4f49 100644 +--- a/llvm/lib/ObjectYAML/COFFYAML.cpp ++++ b/llvm/lib/ObjectYAML/COFFYAML.cpp +@@ -467,6 +467,8 @@ void MappingTraits::mapping(IO &IO, + IO.mapRequired("SizeOfHeapReserve", PH.Header.SizeOfHeapReserve); + IO.mapRequired("SizeOfHeapCommit", PH.Header.SizeOfHeapCommit); + ++ IO.mapOptional("NumberOfRvaAndSize", PH.Header.NumberOfRvaAndSize, ++ COFF::NUM_DATA_DIRECTORIES + 1); + IO.mapOptional("ExportTable", PH.DataDirectories[COFF::EXPORT_TABLE]); + IO.mapOptional("ImportTable", PH.DataDirectories[COFF::IMPORT_TABLE]); + IO.mapOptional("ResourceTable", PH.DataDirectories[COFF::RESOURCE_TABLE]); +diff --git a/llvm/test/tools/yaml2obj/COFF/variable-number-rva.yaml b/llvm/test/tools/yaml2obj/COFF/variable-number-rva.yaml +new file mode 100644 +index 000000000000..01f8f33db227 +--- /dev/null ++++ b/llvm/test/tools/yaml2obj/COFF/variable-number-rva.yaml +@@ -0,0 +1,296 @@ ++## Check that the default NumberOfRvaAndSize is as expected. ++# RUN: yaml2obj --docnum=1 %s -o %t ++# RUN: llvm-readobj --file-headers %t | FileCheck %s --check-prefix=CHECK16 ++# RUN: obj2yaml %t | FileCheck %s --check-prefix=ROUNDTRIP16 ++ ++# CHECK16: NumberOfRvaAndSize: 16 ++# CHECK16-NEXT: DataDirectory { ++# CHECK16-NEXT: ExportTableRVA: 0x0 ++# CHECK16-NEXT: ExportTableSize: 0x0 ++# CHECK16-NEXT: ImportTableRVA: 0x0 ++# CHECK16-NEXT: ImportTableSize: 0x0 ++# CHECK16-NEXT: ResourceTableRVA: 0x0 ++# CHECK16-NEXT: ResourceTableSize: 0x0 ++# CHECK16-NEXT: ExceptionTableRVA: 0x0 ++# CHECK16-NEXT: ExceptionTableSize: 0x0 ++# CHECK16-NEXT: CertificateTableRVA: 0x0 ++# CHECK16-NEXT: CertificateTableSize: 0x0 ++# CHECK16-NEXT: BaseRelocationTableRVA: 0x0 ++# CHECK16-NEXT: BaseRelocationTableSize: 0x0 ++# CHECK16-NEXT: DebugRVA: 0x0 ++# CHECK16-NEXT: DebugSize: 0x0 ++# CHECK16-NEXT: ArchitectureRVA: 0x0 ++# CHECK16-NEXT: ArchitectureSize: 0x0 ++# CHECK16-NEXT: GlobalPtrRVA: 0x0 ++# CHECK16-NEXT: GlobalPtrSize: 0x0 ++# CHECK16-NEXT: TLSTableRVA: 0x0 ++# CHECK16-NEXT: TLSTableSize: 0x0 ++# CHECK16-NEXT: LoadConfigTableRVA: 0x0 ++# CHECK16-NEXT: LoadConfigTableSize: 0x0 ++# CHECK16-NEXT: BoundImportRVA: 0x0 ++# CHECK16-NEXT: BoundImportSize: 0x0 ++# CHECK16-NEXT: IATRVA: 0x0 ++# CHECK16-NEXT: IATSize: 0x0 ++# CHECK16-NEXT: DelayImportDescriptorRVA: 0x0 ++# CHECK16-NEXT: DelayImportDescriptorSize: 0x0 ++# CHECK16-NEXT: CLRRuntimeHeaderRVA: 0x0 ++# CHECK16-NEXT: CLRRuntimeHeaderSize: 0x0 ++# CHECK16-NEXT: ReservedRVA: 0x0 ++# CHECK16-NEXT: ReservedSize: 0x0 ++# CHECK16-NEXT: } ++ ++# ROUNDTRIP16: ExportTable: ++# ROUNDTRIP16-NEXT: RelativeVirtualAddress: 0 ++# ROUNDTRIP16-NEXT: Size: 0 ++# ROUNDTRIP16-NEXT: ImportTable: ++# ROUNDTRIP16-NEXT: RelativeVirtualAddress: 0 ++# ROUNDTRIP16-NEXT: Size: 0 ++# ROUNDTRIP16-NEXT: ResourceTable: ++# ROUNDTRIP16-NEXT: RelativeVirtualAddress: 0 ++# ROUNDTRIP16-NEXT: Size: 0 ++# ROUNDTRIP16-NEXT: ExceptionTable: ++# ROUNDTRIP16-NEXT: RelativeVirtualAddress: 0 ++# ROUNDTRIP16-NEXT: Size: 0 ++# ROUNDTRIP16-NEXT: CertificateTable: ++# ROUNDTRIP16-NEXT: RelativeVirtualAddress: 0 ++# ROUNDTRIP16-NEXT: Size: 0 ++# ROUNDTRIP16-NEXT: BaseRelocationTable: ++# ROUNDTRIP16-NEXT: RelativeVirtualAddress: 0 ++# ROUNDTRIP16-NEXT: Size: 0 ++# ROUNDTRIP16-NEXT: Debug: ++# ROUNDTRIP16-NEXT: RelativeVirtualAddress: 0 ++# ROUNDTRIP16-NEXT: Size: 0 ++# ROUNDTRIP16-NEXT: Architecture: ++# ROUNDTRIP16-NEXT: RelativeVirtualAddress: 0 ++# ROUNDTRIP16-NEXT: Size: 0 ++# ROUNDTRIP16-NEXT: GlobalPtr: ++# ROUNDTRIP16-NEXT: RelativeVirtualAddress: 0 ++# ROUNDTRIP16-NEXT: Size: 0 ++# ROUNDTRIP16-NEXT: TlsTable: ++# ROUNDTRIP16-NEXT: RelativeVirtualAddress: 0 ++# ROUNDTRIP16-NEXT: Size: 0 ++# ROUNDTRIP16-NEXT: LoadConfigTable: ++# ROUNDTRIP16-NEXT: RelativeVirtualAddress: 0 ++# ROUNDTRIP16-NEXT: Size: 0 ++# ROUNDTRIP16-NEXT: BoundImport: ++# ROUNDTRIP16-NEXT: RelativeVirtualAddress: 0 ++# ROUNDTRIP16-NEXT: Size: 0 ++# ROUNDTRIP16-NEXT: IAT: ++# ROUNDTRIP16-NEXT: RelativeVirtualAddress: 0 ++# ROUNDTRIP16-NEXT: Size: 0 ++# ROUNDTRIP16-NEXT: DelayImportDescriptor: ++# ROUNDTRIP16-NEXT: RelativeVirtualAddress: 0 ++# ROUNDTRIP16-NEXT: Size: 0 ++# ROUNDTRIP16-NEXT: ClrRuntimeHeader: ++# ROUNDTRIP16-NEXT: RelativeVirtualAddress: 0 ++# ROUNDTRIP16-NEXT: Size: 0 ++# ROUNDTRIP16-NEXT: header: ++ ++--- !COFF ++OptionalHeader: ++ AddressOfEntryPoint: 4096 ++ ImageBase: 0 ++ SectionAlignment: 4096 ++ FileAlignment: 512 ++ MajorOperatingSystemVersion: 0 ++ MinorOperatingSystemVersion: 0 ++ MajorImageVersion: 0 ++ MinorImageVersion: 0 ++ MajorSubsystemVersion: 0 ++ MinorSubsystemVersion: 0 ++ Subsystem: IMAGE_SUBSYSTEM_EFI_APPLICATION ++ DLLCharacteristics: [ ] ++ SizeOfStackReserve: 0 ++ SizeOfStackCommit: 0 ++ SizeOfHeapReserve: 0 ++ SizeOfHeapCommit: 0 ++header: ++ Machine: IMAGE_FILE_MACHINE_AMD64 ++ Characteristics: [ ] ++sections: ++ - Name: foo ++ Characteristics: [ ] ++ Alignment: 4 ++symbols: ++... ++ ++## Check setting NumberOfRvaAndSize equal to the default (output should ++## be the same as when unset). ++# RUN: yaml2obj --docnum=2 %s -o %t -DNUMRVA=16 ++# RUN: llvm-readobj --file-headers %t | FileCheck %s --check-prefix=CHECK16 ++# RUN: obj2yaml %t | FileCheck %s --check-prefix=ROUNDTRIP16 ++ ++## Check that NumberOfRvaAndSize can be zero. ++# RUN: yaml2obj --docnum=2 %s -o %t -DNUMRVA=0 ++# RUN: llvm-readobj --file-headers %t | FileCheck %s --check-prefix=CHECK0 ++# RUN: obj2yaml %t | FileCheck %s --check-prefix=ROUNDTRIP0 ++ ++# CHECK0: NumberOfRvaAndSize: 0 ++# CHECK0-NOT: DataDirectory ++ ++# ROUNDTRIP0: NumberOfRvaAndSize: 0 ++# ROUNDTRIP0-NOT: ExportTable ++ ++## Check setting NumberOfRvaAndSize to number below default. ++# RUN: yaml2obj --docnum=2 %s -o %t -DNUMRVA=6 ++# RUN: llvm-readobj --file-headers %t | FileCheck %s --check-prefix=CHECK6 ++# RUN: obj2yaml %t | FileCheck %s --check-prefix=ROUNDTRIP6 ++ ++# CHECK6: NumberOfRvaAndSize: 6 ++# CHECK6-NEXT: DataDirectory { ++# CHECK6-NEXT: ExportTableRVA: 0x0 ++# CHECK6-NEXT: ExportTableSize: 0x0 ++# CHECK6-NEXT: ImportTableRVA: 0x0 ++# CHECK6-NEXT: ImportTableSize: 0x0 ++# CHECK6-NEXT: ResourceTableRVA: 0x0 ++# CHECK6-NEXT: ResourceTableSize: 0x0 ++# CHECK6-NEXT: ExceptionTableRVA: 0x0 ++# CHECK6-NEXT: ExceptionTableSize: 0x0 ++# CHECK6-NEXT: CertificateTableRVA: 0x0 ++# CHECK6-NEXT: CertificateTableSize: 0x0 ++# CHECK6-NEXT: BaseRelocationTableRVA: 0x0 ++# CHECK6-NEXT: BaseRelocationTableSize: 0x0 ++# CHECK6-NEXT: } ++ ++# ROUNDTRIP6: NumberOfRvaAndSize: 6 ++# ROUNDTRIP6-NEXT: ExportTable: ++# ROUNDTRIP6-NEXT: RelativeVirtualAddress: 0 ++# ROUNDTRIP6-NEXT: Size: 0 ++# ROUNDTRIP6-NEXT: ImportTable: ++# ROUNDTRIP6-NEXT: RelativeVirtualAddress: 0 ++# ROUNDTRIP6-NEXT: Size: 0 ++# ROUNDTRIP6-NEXT: ResourceTable: ++# ROUNDTRIP6-NEXT: RelativeVirtualAddress: 0 ++# ROUNDTRIP6-NEXT: Size: 0 ++# ROUNDTRIP6-NEXT: ExceptionTable: ++# ROUNDTRIP6-NEXT: RelativeVirtualAddress: 0 ++# ROUNDTRIP6-NEXT: Size: 0 ++# ROUNDTRIP6-NEXT: CertificateTable: ++# ROUNDTRIP6-NEXT: RelativeVirtualAddress: 0 ++# ROUNDTRIP6-NEXT: Size: 0 ++# ROUNDTRIP6-NEXT: BaseRelocationTable: ++# ROUNDTRIP6-NEXT: RelativeVirtualAddress: 0 ++# ROUNDTRIP6-NEXT: Size: 0 ++# ROUNDTRIP6-NEXT: header: ++ ++## Check setting NumberOfRvaAndSize to number above default. ++# RUN: yaml2obj --docnum=2 %s -o %t -DNUMRVA=18 ++# RUN: llvm-readobj --file-headers %t | FileCheck %s --check-prefix=CHECK18 ++# RUN: obj2yaml %t | FileCheck %s --check-prefix=ROUNDTRIP18 ++ ++# CHECK18: NumberOfRvaAndSize: 18 ++# CHECK18-NEXT: DataDirectory { ++# CHECK18-NEXT: ExportTableRVA: 0x0 ++# CHECK18-NEXT: ExportTableSize: 0x0 ++# CHECK18-NEXT: ImportTableRVA: 0x0 ++# CHECK18-NEXT: ImportTableSize: 0x0 ++# CHECK18-NEXT: ResourceTableRVA: 0x0 ++# CHECK18-NEXT: ResourceTableSize: 0x0 ++# CHECK18-NEXT: ExceptionTableRVA: 0x0 ++# CHECK18-NEXT: ExceptionTableSize: 0x0 ++# CHECK18-NEXT: CertificateTableRVA: 0x0 ++# CHECK18-NEXT: CertificateTableSize: 0x0 ++# CHECK18-NEXT: BaseRelocationTableRVA: 0x0 ++# CHECK18-NEXT: BaseRelocationTableSize: 0x0 ++# CHECK18-NEXT: DebugRVA: 0x0 ++# CHECK18-NEXT: DebugSize: 0x0 ++# CHECK18-NEXT: ArchitectureRVA: 0x0 ++# CHECK18-NEXT: ArchitectureSize: 0x0 ++# CHECK18-NEXT: GlobalPtrRVA: 0x0 ++# CHECK18-NEXT: GlobalPtrSize: 0x0 ++# CHECK18-NEXT: TLSTableRVA: 0x0 ++# CHECK18-NEXT: TLSTableSize: 0x0 ++# CHECK18-NEXT: LoadConfigTableRVA: 0x0 ++# CHECK18-NEXT: LoadConfigTableSize: 0x0 ++# CHECK18-NEXT: BoundImportRVA: 0x0 ++# CHECK18-NEXT: BoundImportSize: 0x0 ++# CHECK18-NEXT: IATRVA: 0x0 ++# CHECK18-NEXT: IATSize: 0x0 ++# CHECK18-NEXT: DelayImportDescriptorRVA: 0x0 ++# CHECK18-NEXT: DelayImportDescriptorSize: 0x0 ++# CHECK18-NEXT: CLRRuntimeHeaderRVA: 0x0 ++# CHECK18-NEXT: CLRRuntimeHeaderSize: 0x0 ++# CHECK18-NEXT: ReservedRVA: 0x0 ++# CHECK18-NEXT: ReservedSize: 0x0 ++# CHECK18-NEXT: UnknownRVA: 0x0 ++# CHECK18-NEXT: UnknownSize: 0x0 ++# CHECK18-NEXT: UnknownRVA: 0x0 ++# CHECK18-NEXT: UnknownSize: 0x0 ++# CHECK18-NEXT: } ++ ++# ROUNDTRIP18: NumberOfRvaAndSize: 18 ++# ROUNDTRIP18-NEXT: ExportTable: ++# ROUNDTRIP18-NEXT: RelativeVirtualAddress: 0 ++# ROUNDTRIP18-NEXT: Size: 0 ++# ROUNDTRIP18-NEXT: ImportTable: ++# ROUNDTRIP18-NEXT: RelativeVirtualAddress: 0 ++# ROUNDTRIP18-NEXT: Size: 0 ++# ROUNDTRIP18-NEXT: ResourceTable: ++# ROUNDTRIP18-NEXT: RelativeVirtualAddress: 0 ++# ROUNDTRIP18-NEXT: Size: 0 ++# ROUNDTRIP18-NEXT: ExceptionTable: ++# ROUNDTRIP18-NEXT: RelativeVirtualAddress: 0 ++# ROUNDTRIP18-NEXT: Size: 0 ++# ROUNDTRIP18-NEXT: CertificateTable: ++# ROUNDTRIP18-NEXT: RelativeVirtualAddress: 0 ++# ROUNDTRIP18-NEXT: Size: 0 ++# ROUNDTRIP18-NEXT: BaseRelocationTable: ++# ROUNDTRIP18-NEXT: RelativeVirtualAddress: 0 ++# ROUNDTRIP18-NEXT: Size: 0 ++# ROUNDTRIP18-NEXT: Debug: ++# ROUNDTRIP18-NEXT: RelativeVirtualAddress: 0 ++# ROUNDTRIP18-NEXT: Size: 0 ++# ROUNDTRIP18-NEXT: Architecture: ++# ROUNDTRIP18-NEXT: RelativeVirtualAddress: 0 ++# ROUNDTRIP18-NEXT: Size: 0 ++# ROUNDTRIP18-NEXT: GlobalPtr: ++# ROUNDTRIP18-NEXT: RelativeVirtualAddress: 0 ++# ROUNDTRIP18-NEXT: Size: 0 ++# ROUNDTRIP18-NEXT: TlsTable: ++# ROUNDTRIP18-NEXT: RelativeVirtualAddress: 0 ++# ROUNDTRIP18-NEXT: Size: 0 ++# ROUNDTRIP18-NEXT: LoadConfigTable: ++# ROUNDTRIP18-NEXT: RelativeVirtualAddress: 0 ++# ROUNDTRIP18-NEXT: Size: 0 ++# ROUNDTRIP18-NEXT: BoundImport: ++# ROUNDTRIP18-NEXT: RelativeVirtualAddress: 0 ++# ROUNDTRIP18-NEXT: Size: 0 ++# ROUNDTRIP18-NEXT: IAT: ++# ROUNDTRIP18-NEXT: RelativeVirtualAddress: 0 ++# ROUNDTRIP18-NEXT: Size: 0 ++# ROUNDTRIP18-NEXT: DelayImportDescriptor: ++# ROUNDTRIP18-NEXT: RelativeVirtualAddress: 0 ++# ROUNDTRIP18-NEXT: Size: 0 ++# ROUNDTRIP18-NEXT: ClrRuntimeHeader: ++# ROUNDTRIP18-NEXT: RelativeVirtualAddress: 0 ++# ROUNDTRIP18-NEXT: Size: 0 ++# ROUNDTRIP18-NEXT: header: ++ ++--- !COFF ++OptionalHeader: ++ AddressOfEntryPoint: 4096 ++ ImageBase: 0 ++ SectionAlignment: 4096 ++ FileAlignment: 512 ++ MajorOperatingSystemVersion: 0 ++ MinorOperatingSystemVersion: 0 ++ MajorImageVersion: 0 ++ MinorImageVersion: 0 ++ MajorSubsystemVersion: 0 ++ MinorSubsystemVersion: 0 ++ Subsystem: IMAGE_SUBSYSTEM_EFI_APPLICATION ++ DLLCharacteristics: [ ] ++ SizeOfStackReserve: 0 ++ SizeOfStackCommit: 0 ++ SizeOfHeapReserve: 0 ++ SizeOfHeapCommit: 0 ++ NumberOfRvaAndSize: [[NUMRVA]] ++header: ++ Machine: IMAGE_FILE_MACHINE_AMD64 ++ Characteristics: [ ] ++sections: ++ - Name: foo ++ Characteristics: [ ] ++ Alignment: 4 ++symbols: ++... +diff --git a/llvm/tools/llvm-readobj/COFFDumper.cpp b/llvm/tools/llvm-readobj/COFFDumper.cpp +index 96124cc03484..91607c69369a 100644 +--- a/llvm/tools/llvm-readobj/COFFDumper.cpp ++++ b/llvm/tools/llvm-readobj/COFFDumper.cpp +@@ -709,7 +709,10 @@ void COFFDumper::printPEHeader(const PEHeader *Hdr) { + }; + + for (uint32_t i = 0; i < Hdr->NumberOfRvaAndSize; ++i) +- printDataDirectory(i, directory[i]); ++ if (i < sizeof(directory) / sizeof(char *)) ++ printDataDirectory(i, directory[i]); ++ else ++ printDataDirectory(i, "Unknown"); + } + } + +diff --git a/llvm/tools/obj2yaml/coff2yaml.cpp b/llvm/tools/obj2yaml/coff2yaml.cpp +index 03587358340f..bc8aacce1ae8 100644 +--- a/llvm/tools/obj2yaml/coff2yaml.cpp ++++ b/llvm/tools/obj2yaml/coff2yaml.cpp +@@ -80,6 +80,8 @@ template void COFFDumper::dumpOptionalHeader(T OptionalHeader) { + OptionalHeader->SizeOfHeapReserve; + YAMLObj.OptionalHeader->Header.SizeOfHeapCommit = + OptionalHeader->SizeOfHeapCommit; ++ YAMLObj.OptionalHeader->Header.NumberOfRvaAndSize = ++ OptionalHeader->NumberOfRvaAndSize; + unsigned I = 0; + for (auto &DestDD : YAMLObj.OptionalHeader->DataDirectories) { + const object::data_directory *DD = Obj.getDataDirectory(I++); +-- +2.25.1 + diff -Nru llvm-toolchain-13-13.0.1/debian/rules llvm-toolchain-13-13.0.1/debian/rules --- llvm-toolchain-13-13.0.1/debian/rules 2022-02-13 14:08:44.000000000 +0100 +++ llvm-toolchain-13-13.0.1/debian/rules 2022-05-25 11:08:13.000000000 +0200 @@ -126,6 +126,7 @@ # clangd remote index support requires GRPC & protobuf. # Enable if minimum tested versions are available. +ifneq ($(VENDOR)-$(DEB_HOST_ARCH),Ubuntu-i386) ifeq ($(shell dpkg --compare-versions $(shell dpkg-query -W -f '$${Version}' libgrpc++-dev) gt 1.30.0; echo $$?),0) ifeq ($(shell dpkg --compare-versions $(shell dpkg-query -W -f '$${Version}' protobuf-compiler-grpc) gt 1.30.0; echo $$?),0) ifeq ($(shell dpkg --compare-versions $(shell dpkg-query -W -f '$${Version}' libprotobuf-dev) gt 3.12.0; echo $$?),0) @@ -135,6 +136,7 @@ endif endif endif +endif export CC=gcc-$(GCC_VERSION) export CXX=g++-$(GCC_VERSION) @@ -433,6 +435,7 @@ # Make install file executable for dh-exec chmod +x \ debian/clang-tools-$(LLVM_VERSION).install \ + debian/libclang-$(LLVM_VERSION)-dev.install \ debian/libclang-common-$(LLVM_VERSION)-dev.install \ debian/libomp-$(LLVM_VERSION)-dev.install \ debian/llvm-$(LLVM_VERSION)-dev.install \