fc25441c7b9,drm/i915/ehl: Add one additional PCH ID to MCC,2019-06-21 08:18:47,not in drm-intel-next/linux-upstream
8dcfdfb4501,drm/i915/perf: fix ICL perf register offsets,2019-06-10 11:19:14,not in drm-intel-next/linux-upstream
f9a393875d3,drm/i915: Disable SAMPLER_STATE prefetching on all Gen11 steppings.,2019-06-25 10:06:55,not in drm-intel-next/linux-upstream
683d672c425,drm/i915/ehl/dsi: Enable AFE over PPI strap,2019-06-19 16:31:34,next-20190621
6a7bafe8fdb,drm/i915/ehl/dsi: Set lane latency optimization for DW1,2019-06-19 16:31:33,next-20190621
bdeb18dbcf8,drm/i915/ehl: Allow combo PHY A to drive a third external display,2019-06-18 10:51:31,next-20190620
patches series of Update whitelist support for new hardware,,,
1/4 5380d0b781c ADDED!,drm/i915: Support flags in whitlist WAs,2019-06-17 18:01:05,next-20190619
2/4 ebd2de47a19 ADDED!,drm/i915: Support whitelist workarounds on all engines,2019-06-17 18:01:06,next-20190619
3/4 7b3d4063109,drm/i915: Add whitelist workarounds for ICL,2019-06-17 18:01:07,next-20190619
4/4 767662bc62a ADDED!,drm/i915: Update workarounds selftest for read only regs,2019-06-17 18:01:08,next-20190619
c6f7acb80ab,drm/i915/ehl: Introduce Mule Creek Canyon PCH,2019-06-14 17:42:10,next-20190619
patches series of Enable Multi-segmented-gamma for ICL,,,
1/4 89a72304f2f,drm/i915: Change gamma/degamma_lut_size data type to u32,2019-06-12 12:14:57,next-20190619
2/4 377c70edd48,drm/i915/icl: Add register definitions for Multi Segmented gamma,2019-06-12 12:14:58,next-20190619
3/4 eec0778ec42 ADDED!,drm/i915: Rename ivb_load_lut_10_max,2019-06-12 12:14:59,next-20190619
4/4 02ae8ba9664,drm/i915/icl: Add Multi-segmented gamma support,2019-06-12 12:15:00,next-20190619
f4071997f1d,drm/i915/ehl: Update MOCS table for EHL,2019-05-30 16:40:14,next-20190617
cc49abc2460,drm/i915: Add Wa_1409120013:icl,ehl,2019-06-12 11:36:31,next-20190617
326fb6dd148,drm/i915/dmc: protect against reading random memory,2019-06-05 16:55:35,v5.2-rc5
522d47cff11,drm/i915/skl: use ranges for voltage level lookup,2019-06-10 14:48:47,next-20190612
63b1700b40d,drm/i915/cnl: use ranges for voltage level lookup,2019-06-10 14:48:34,next-20190612
4f338ac0b2f,drm/i915/icl: use ranges for voltage level lookup,2019-06-10 14:48:19,next-20190612
8500f14b639,drm/i915: Convert icl_get_stolen_reserved to uncore mmio accessors,2019-06-10 13:06:05,next-20190611
23529cbe915,drm/i915/wopcm: update default size for gen11+,2019-06-06 15:42:25,next-20190611
33ec6c9eb35,drm/i915/guc: always use Command Transport Buffers,2019-06-06 15:42:24,next-20190611
patches series of 2def5ae7d7f,,,
1/3 0e29eb9d916 ADDED!,drm/i915/dsi: Move logging of DSI VBT parameters to a helper function,2019-06-05 20:17:33,next-20190611
2/3 2def5ae7d7f,drm/i915/dsi: Move vlv/icl_dphy_param_init call out of intel_dsi_vbt_init (v2),2019-06-05 20:17:34,next-20190611
3/3 6be306bee7d ADDED!,drm/i915/dsi: Read back pclk set by GOP and use that as pclk (v3),2019-06-05 20:17:35,next-20190611
bc7b488b1d1,drm/i915/dmc: protect against reading random memory,2019-06-05 16:55:35,next-20190611
b7143860634,drm/i915/ehl: Support HBR3 on EHL combo PHY,2019-06-05 14:18:32,next-20190606
912348b64d0,drm/i915/icl: Ensure port A combo PHY HW state is correct,2019-05-31 11:26:26,next-20190604
d8fd3722207,drm/mst: Fix MST sideband up-reply failure handling,2019-05-24 00:24:33,next-20190531
a10f361d176,Revert "drm/i915: Expand subslice mask",2019-05-29 11:21:50,next-20190530
a6315005a2d,drm/i915/icl: Add WaDisableBankHangMode,2019-05-20 12:04:42,v5.2-rc4
c9e0c8d91ea,drm/i915/huc: Define HuC firmware version for Icelake,2019-05-27 18:36:12,next-20190529
f4cc8999205,drm/i915/guc: Define GuC firmware version for Icelake,2019-05-27 18:36:11,next-20190529
a18c3d5e4e4,drm/i915/guc: Enable GuC CTB communication on Gen11,2019-05-27 18:36:10,next-20190529
54c52a84125,drm/i915/guc: Correctly handle GuC interrupts on Gen11,2019-05-27 18:36:08,next-20190529
7c5ae251b04,drm/i915/huc: New HuC status register for Gen11,2019-05-27 18:36:06,next-20190529
2d4ed3a988e,drm/i915/guc: New GuC scratch registers for Gen11,2019-05-27 18:36:05,next-20190529
4a1f9dc1191,drm/i915/guc: New GuC interrupt register for Gen11,2019-05-27 18:36:04,next-20190529
c457d9cf256,drm/i915: Make sure we have enough memory bandwidth on ICL,2019-05-24 18:36:14,next-20190528
4361ccac281,drm/i915/icl: Fix AUX-B HW not done issue w/o AUX-A,2019-05-24 20:35:32,next-20190528
e2f6624cab3,ICL HACK: drm/i915/opregion: ICL should have opregion 2.1+ and relative rvda,2019-02-08 20:42:54,not in drm-intel-next/linux-upstream
397049a0302,drm/i915/gen11: enable support for headerless msgs,2019-04-25 06:50:05,next-20190528
patches series of drm/i915/dp: Support for DP YCbCr4:2:0 outputs,,,
1/6 8e9d645c683 ADDED!,drm/i915/dp: Add a config function for YCBCR420 outputs,2019-05-21 15:17:16,next-20190524
2/6 4d432f956d4 ADDED!,drm: Rename struct edp_vsc_psr to struct dp_sdp,2019-05-21 15:17:17,next-20190524
3/6 3c053a96ef5 ADDED!,drm/i915/dp: Program VSC Header and DB for Pixel Encoding/Colorimetry Format,2019-05-21 15:17:18,next-20190524
4/6 ec4401d3893 ADDED!,drm/i915/dp: Add a support of YCBCR 4:2:0 to DP MSA,2019-05-21 15:17:19,next-20190524
5/6 16668f486ff ADDED!,drm/i915/dp: Change a link bandwidth computation for DP,2019-05-21 15:17:20,next-20190524
6/6 47d0ccecc9f,drm/i915/dp: Support DP ports YUV 4:2:0 output to GEN11,2019-05-21 15:17:21,next-20190524
c5d3e39caa4,drm/i915: Engine discovery query,2019-05-22 10:00:54,next-20190523
cbe3e1d1037,drm/i915/icl: Add WaDisableBankHangMode,2019-05-20 12:04:42,next-20190523
50b03a3d831,ICL HACK: drm/i915/opregion: ICL should have opregion 2.1+ and relative rvda,2019-02-08 20:42:54,not in drm-intel-next/linux-upstream
patches series of b4c7ea63547,,,
01/11 4547c255f44 ADDED!,drm/i915: Add support for tracking wakerefs w/o power-on guarantee,2019-05-09 20:34:36,next-20190521
02/11 dbf99c1f8c7 ADDED!,drm/i915: Force printing wakeref tacking during pm_cleanup,2019-05-09 20:34:37,next-20190521
03/11 ee70080a52f ADDED!,drm/i915: Verify power domains state during suspend in all cases,2019-05-09 20:34:38,next-20190521
04/11 e0da2d63ab3,drm/i915: Add support for asynchronous display power disabling,2019-05-13 22:25:33,next-20190521
05/11 f39194a7a8b ADDED!,drm/i915: Disable power asynchronously during DP AUX transfers,2019-05-09 20:34:40,next-20190521
06/11 ad5125d6ef2 ADDED!,drm/i915: WARN for eDP encoders in intel_dp_detect_dpcd(),2019-05-09 20:34:41,next-20190521
07/11 6cfe7ec02e8 ADDED!,drm/i915: Remove the unneeded AUX power ref from intel_dp_detect(),2019-05-09 20:34:42,next-20190521
08/11 6f08ebe779a ADDED!,drm/i915: Remove the unneeded AUX power ref from intel_dp_hpd_pulse(),2019-05-09 20:34:43,next-20190521
09/11 08d8e17005a ADDED!,drm/i915: Replace use of PLLS power domain with DISPLAY_CORE domain,2019-05-09 20:34:44,next-20190521
10/11 b4c7ea63547,drm/i915: Avoid taking the PPS lock for non-eDP/VLV/CHV,2019-05-09 20:34:45,next-20190521
11/11 4e309bafeb7 ADDED!,drm/i915: Assert that TypeC ports are not used for eDP,2019-05-09 20:34:46,next-20190521
3fad10dbb68,drm/i915/icl: Fix setting 10 bit deep color mode,2019-05-07 11:18:56,next-20190521
05d9c8783bb,drm/i915/icl: Set GCP_COLOR_INDICATION only for 10/12 bit deep color,2019-04-29 16:08:11,next-20190521
b7ffc4a839a,drm/i915: Allow ICL pipe "HDR mode" when the cursor is visible,2019-05-02 23:06:07,next-20190521
a832d35762a,drm/i915: Move the PIPEMISC write the correct place,2019-05-02 23:06:06,next-20190521
cfda08cdac3,drm/i915/icl: Add missing combo PHY lane power setup,2019-04-25 21:52:53,next-20190521
bd60a562906,drm/i915/icl: Factor out combo PHY lane power setup helper,2019-04-25 21:52:52,next-20190521
patches series of 09b25812db1,,,
1/2 9b11215e40c ADDED!,drm/i915: Flatten and rename haswell_set_pipemisc(),2019-04-12 21:30:08,next-20190521
2/2 09b25812db1,drm/i915: Enable pipe HDR mode on ICL if only HDR planes are used,2019-04-12 21:30:09,next-20190521
patches series of Trivial comments and small changes,,,
1/3 fcfec1fc98f,drm/i915/icl: fix step numbers in icl_display_core_init(),2019-04-04 16:04:24,next-20190521
2/3 323b0a82efb ADDED!,drm/i915: reorder if chain to have last gen first,2019-04-04 16:04:25,next-20190521
3/3 da17223e853 ADDED!,drm/i915: do not mix workaround with normal flow,2019-04-04 16:04:26,next-20190521
9628e15ca9d,drm/i915/icl: Whitelist GEN9_SLICE_COMMON_ECO_CHICKEN1,2019-04-18 11:06:34,v5.2-rc1
patches series of 0fc2273b9ab,,,
1/2 86554f48e51 ADDED!,drm/i915/selftests: Verify whitelist of context registers,2019-04-24 12:09:41,next-20190521
2/2 0fc2273b9ab,drm/i915/icl: Whitelist GEN9_SLICE_COMMON_ECO_CHICKEN1,2019-04-18 11:06:34,next-20190521
879a4e70f96,drm/i915: Fix ICL output CSC programming,2019-04-25 22:24:19,v5.2-rc1
d428ca17ea3,drm/i915: Fix ICL output CSC programming,2019-04-25 22:24:19,next-20190521
447811a686e,drm/i915/icl: Fix MG_DP_MODE() register programming,2019-04-19 10:10:26,v5.2-rc1
patches series of 51eb1a1de7a,,,
1/3 2474028e4b9 ADDED!,drm/i915: Rename skl_wa_clkgating to the actual WA,2019-03-29 18:19:19,v5.2-rc1
2/3 fa9d38f65d3 ADDED!,drm/i915: Fix the inconsistent RMW in WA 827,2019-03-29 18:19:20,v5.2-rc1
3/3 51eb1a1de7a,drm/i915/icl: Fix clockgating issue when using scalers,2019-04-17 11:59:01,next-20190424
372b9ffb579,drm/i915: Fix skl+ max plane width,2019-04-18 22:59:07,next-20190424
9c11b12184b,drm/i915/icl: Fix MG_DP_MODE() register programming,2019-04-19 10:10:26,next-20190424
5b354966d0d,drm/i915/ehl: inherit icl cdclk init/uninit,2019-04-16 11:28:52,v5.2-rc1
d1172ab3d44,drm/i915: Introduce struct class_instance for engines across the uAPI,2019-04-12 08:14:16,v5.2-rc1
39564ae86d5,drm/i915/ehl: Inherit Ice Lake conditional code,2019-04-12 11:09:20,v5.2-rc1
e5604e2fb6d,drm/i915: Suppress spurious combo PHY B warning,2019-04-11 17:33:49,v5.2-rc1
3936867dbc1,drm/i915: Disable read only ppgtt support for gen11,2019-04-11 11:30:34,v5.2-rc1
632c7ad6f45,drm/i915/icl: Switch to using 12 deep CSB status FIFO,2019-04-05 21:46:57,v5.2-rc1
7d4c75d9097,drm/i915: Prepare for larger CSB status FIFO size,2019-04-05 21:46:56,v5.2-rc1
917dc6b53c2,drm/i915: Use Engine1 instance for gen11 pm interrupts,2019-04-10 13:59:22,v5.2-rc1
1071d0f6877,drm/i915/icl: Disable video turbo mode for rp control,2019-04-10 16:24:36,v5.2-rc1
2ea7414159c,drm/i915/icl: Enable media sampler powergate,2019-04-10 13:59:19,v5.2-rc1
d105e9ad548,drm/i915/icl: Apply a recommended rc6 threshold,2019-04-10 13:59:18,v5.2-rc1
a79208de65f,drm/i915: Use dedicated rc6 enabling sequence for gen11,2019-04-10 13:59:17,v5.2-rc1
4690985e00a,drm/i915/icl: Fix port disable sequence for mipi-dsi,2019-03-25 16:56:42,v5.1-rc5
20eea462bf2,drm/i915/icl: Ungate ddi clocks before IO enable,2019-03-25 16:56:41,v5.1-rc5
8455dad7ba8,drm/i915/icl: Don't warn on spurious interrupts,2019-04-10 16:21:24,v5.2-rc1
a087bafeeac,drm/i915/icl: Handle rps interrupts without irq lock,2019-04-10 16:21:23,v5.2-rc1
942d1cf48ea,drm/i915/icl: Fix port disable sequence for mipi-dsi,2019-03-25 16:56:42,v5.2-rc1
c5b81a32526,drm/i915/icl: Ungate ddi clocks before IO enable,2019-03-25 16:56:41,v5.2-rc1
99fa4bc26d7,drm/i915/icl: Simplify release of encoder power refs,2019-04-05 18:36:57,v5.2-rc1
patches series of drm/i915: Finish the GAMMA_LUT stuff,,,
1/7 320d41b33ad ADDED!,drm/i915: Extract ilk_lut_10(),2019-04-01 23:02:25,v5.2-rc1
2/7 5bda1aca5d9,drm/i915: Don't use split gamma when we don't have to,2019-04-01 23:02:26,v5.2-rc1
3/7 c21ce2effc5 ADDED!,drm/i915: Implement split/10bit gamma for ivb/hsw,2019-04-01 23:02:27,v5.2-rc1
4/7 514462caf75 ADDED!,drm/i915: Add 10bit LUT for ilk/snb,2019-04-01 23:02:28,v5.2-rc1
5/7 e262568eb58 ADDED!,drm/i915: Add "10.6" LUT mode for i965+,2019-04-01 23:02:29,v5.2-rc1
6/7 821062478ce ADDED!,drm/i915: Expose the legacy LUT via the GAMMA_LUT/GAMMA_LUT_SIZE props on gen2/3,2019-04-01 23:02:30,v5.2-rc1
7/7 795f672b88b ADDED!,drm/i915: Expose full 1024 LUT entries on ivb+,2019-04-03 22:16:33,v5.2-rc1
patches series of drm/i915: Ensure minimum CDCLK requirement for audio,,,
1/4 905801fe723 ADDED!,drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled,2019-03-20 15:54:36,v5.2-rc1
2/4 48d9f87ddd2 ADDED!,drm/i915: Save the old CDCLK atomic state,2019-03-20 15:54:37,v5.2-rc1
3/4 2b21dfbeee7 ADDED!,drm/i915: Remove redundant store of logical CDCLK state,2019-03-20 15:54:38,v5.2-rc1
4/4 59f9e9cab3a,drm/i915: Skip modeset for cdclk changes if possible,2019-03-27 12:13:21,v5.2-rc1
f722b8c1e2a,drm/i915/ehl: All EHL ports are combo phys,2019-03-20 14:15:46,v5.2-rc1
a145b5b0e48,drm/i915: Always backoff after a drm_modeset_lock() deadlock,2019-03-29 16:51:52,v5.1-rc4
patches series of Device id consolidation,,,
1/4 86d35d4e762 ADDED!,drm/i915: Split Pineview device info into desktop and mobile,2019-03-26 07:40:54,v5.2-rc1
2/4 e08891a5b7e,drm/i915: Remove redundant device id from IS_IRONLAKE_M macro,2019-03-26 07:40:55,v5.2-rc1
3/4 NOT-IN-UPSTREAM,drm/i915: Split some PCI ids into separate groups,,
4/4 805446c8347,drm/i915: Introduce concept of a sub-platform,2019-03-27 14:23:28,v5.2-rc1
ee6df5694a9,drm/i915: Always backoff after a drm_modeset_lock() deadlock,2019-03-29 16:51:52,v5.2-rc1
patches series of drm/i915: Clean up intel_color_check(),,,
01/10 e0510da0519 ADDED!,drm/i915: Extract check_luts(),2019-03-27 17:50:36,v5.2-rc1
02/10 9d9cb9c18c7 ADDED!,drm/i915: Turn intel_color_check() into a vfunc,2019-03-27 17:50:37,v5.2-rc1
03/10 e98f35624ca ADDED!,drm/i915: Extract i9xx_color_check(),2019-03-27 17:50:38,v5.2-rc1
04/10 3cdd5174cfc ADDED!,drm/i915: Extract chv_color_check(),2019-03-27 17:50:39,v5.2-rc1
05/10 1b386cf8493,drm/i915: Extract icl_color_check(),2019-03-27 17:50:40,v5.2-rc1
06/10 fbeb4f36221 ADDED!,drm/i915: Extract glk_color_check(),2019-03-27 17:50:41,v5.2-rc1
07/10 1eb63156112 ADDED!,drm/i915: Extract bdw_color_check(),2019-03-27 17:50:42,v5.2-rc1
08/10 f65d5528c02 ADDED!,drm/i915: Extract ilk_color_check(),2019-03-27 17:50:43,v5.2-rc1
09/10 c25abff511a ADDED!,drm/i915: Drop the pointless linear legacy LUT load on CHV,2019-03-27 17:50:44,v5.2-rc1
10/10 c4128ce7d59,drm/i915: Skip the linear degamma LUT load on ICL+,2019-03-27 17:50:45,v5.2-rc1
26cdaac4793,drm/i915/icl: Fix VEBOX mismatch BUG_ON(),2019-03-26 16:02:23,v5.1-rc3
547fcf9b1c6,drm/i915/icl: Fix VEBOX mismatch BUG_ON(),2019-03-26 16:02:23,v5.2-rc1
patches series of Do not re-read dpll registers,,,
1/5 947f4417468 ADDED!,drm/i915/skl: use previous pll hw readout,2019-03-22 15:37:47,v5.2-rc1
2/5 47c9877e9be ADDED!,drm/i915/bxt: make bxt_calc_pll_link() similar to skl,2019-03-22 15:37:48,v5.2-rc1
3/5 5e65216d8dd,drm/i915/cnl: use previous pll hw readout,2019-03-22 15:37:49,v5.2-rc1
4/5 02c99d26f52,drm/i915/icl: use previous pll hw readout,2019-03-22 15:37:50,v5.2-rc1
5/5 077973c8c37,drm/i915/icl: reduce pll_id scope and use enum type,2019-03-22 15:37:51,v5.2-rc1
4b225248dad,drm/i915/ehl: Add Support for DMC on EHL,2019-03-22 10:58:47,v5.2-rc1
9b7598a99ab,drm/i915/ehl: Set proper eu slice/subslice parameters for EHL,2019-03-22 10:58:46,v5.2-rc1
759c9ab55b5,drm/i915/ehl: EHL outputs are different from ICL,2019-03-22 10:58:45,v5.2-rc1
e547f2a2fc1,drm/i915/ehl: Add dpll mgr,2019-03-22 10:58:44,v5.2-rc1
897f296152c,drm/i915/ehl: Add ElkhartLake platform,2019-03-22 10:58:43,v5.2-rc1
29f3863d33d,drm/i915/ehl: Add EHL platform info and PCI IDs,2019-03-22 10:58:42,v5.2-rc1
69903dfae03,drm/i915/icl: Fix the TRANS_DDI_FUNC_CTL2 bitfield macro,2019-03-19 15:18:47,v5.1-rc3
7264aebb81d,drm/i915/icl: Fix the TRANS_DDI_FUNC_CTL2 bitfield macro,2019-03-19 15:18:47,v5.2-rc1
patches series of 96cb7cde1a3,,,
1/9 3cf963cfe3a ADDED!,drm/i915: Accept alloc_size == blocks,2019-03-12 22:58:36,v5.2-rc1
2/9 67155a69968 ADDED!,drm/i915: Don't pass plane state to skl_compute_plane_wm(),2019-03-12 22:58:37,v5.2-rc1
3/9 c92558aa417 ADDED!,drm/i915: Extract skl_compute_wm_params(),2019-03-12 22:58:38,v5.2-rc1
4/9 df331de3f8a ADDED!,drm/i915: Allocate enough DDB for the cursor,2019-03-19 18:03:11,v5.2-rc1
5/9 10a7e07b68b ADDED!,drm/i915: Make sure cursor has enough ddb for the selected wm level,2019-03-12 22:58:40,v5.2-rc1
6/9 a301cb0fca2 ADDED!,drm/i915: Keep plane watermarks enabled more aggressively,2019-03-12 22:58:41,v5.2-rc1
7/9 5e6037c88ad ADDED!,drm/i915: Move some variables to tighter scope,2019-03-12 22:58:42,v5.2-rc1
8/9 96cb7cde1a3,drm/i915: Don't pass pipe_wm around so much,2019-03-12 22:58:43,v5.2-rc1
9/9 NOT-IN-UPSTREAM,drm/i915: Inline skl_build_pipe_wm() into its only caller,,
06dd94cccdd,drm/i915: Fix PSR2 selective update corruption after PSR1 setup,2019-03-14 16:01:13,v5.2-rc1
patches series of dc41e918d15,,,
01/13 da3739070c9 ADDED!,drm/i915: Don't pass crtc to intel_find_shared_dpll(),2019-02-07 19:32:18,v5.2-rc1
02/13 cc089e8abea ADDED!,drm/i915: Don't pass crtc to intel_get_shared_dpll() and .get_dpll(),2019-02-07 19:32:19,v5.2-rc1
03/13 98b6072c2a3 ADDED!,drm/i915: Pass crtc_state down to skl dpll funcs,2019-02-07 19:32:20,v5.2-rc1
04/13 15dc88a8776 ADDED!,drm/i915: Remove redundant on stack dpll_hw_state from skl_get_dpll(),2019-02-07 19:32:21,v5.2-rc1
05/13 e40396d015b ADDED!,drm/i915: Pass crtc_state down to bxt dpll funcs,2019-02-07 19:32:22,v5.2-rc1
06/13 67de42e8d52 ADDED!,drm/i915: Remove redundant on stack dpll_hw_state from bxt_get_dpll(),2019-02-07 19:32:23,v5.2-rc1
07/13 e7251d71d4d ADDED!,drm/i915: Pass crtc_state down to cnl dpll funcs,2019-02-07 19:32:24,v5.2-rc1
08/13 2cf9cd820a2 ADDED!,drm/i915: Remove redundant on stack dpll_hw_state from cnl_get_dpll(),2019-02-07 19:32:25,v5.2-rc1
09/13 3d1ed35182a,drm/i915: Pass crtc_state down to icl dpll funcs,2019-02-07 19:32:26,v5.2-rc1
10/13 dc41e918d15,drm/i915: Remove redundant on stack dpll_hw_state from icl_get_dpll(),2019-02-07 19:32:27,v5.2-rc1
11/13 2ee7fd1efe6 ADDED!,drm/i915: Fix readout for cnl DPLL kdiv==3,2019-02-07 19:32:28,v5.2-rc1
12/13 ad40f8b314a,drm/i915: Nuke icl_calc_dp_combo_pll_link(),2019-02-07 19:32:29,v5.2-rc1
13/13 4631dc3b7c7 ADDED!,drm/i915: Remove the fragile array index -> link rate mapping,2019-02-07 19:32:30,v5.2-rc1
patches series of 5a0404408d3,,,
1/2 5a0404408d3,drm/i915: Fix legacy gamma mode for ICL,2019-03-15 21:54:44,v5.2-rc1
2/2 7c1200456cb ADDED!,drm/i915: Turn off the CUS when turning off a HDR plane,2019-03-15 21:54:45,v5.2-rc1
patches series of drm/i915: Clean up ilk+ csc stuff,,,
1/7 a1f1e61bfb0 ADDED!,drm/i915: Readout and check csc_mode,2019-02-18 21:31:31,v5.2-rc1
2/7 NOT-IN-UPSTREAM,drm/i915: Preocmpute/readout/check CHV CGM mode,,
3/7 386ba08fb59 ADDED!,drm/i915: Extract ilk_csc_limited_range(),2019-02-18 21:31:33,v5.2-rc1
4/7 d2c19b06d6e,drm/i915: Clean up ilk/icl pipe/output CSC programming,2019-02-18 21:31:34,v5.2-rc1
5/7 c9e235aa0f9 ADDED!,drm/i915: Extract ilk_csc_convert_ctm(),2019-02-18 21:31:35,v5.2-rc1
6/7 b281264f8b8 ADDED!,drm/i915: Clean the csc limited range/identity programming,2019-02-18 21:31:36,v5.2-rc1
7/7 f19d90eed64,drm/i915: Split ilk vs. icl csc matrix handling,2019-02-18 21:31:37,v5.2-rc1
daeaaef5ef3,drm/i915/icl: remove intel_dpll_is_combophy(),2019-03-08 19:57:27,v5.2-rc1
2f3ee43cb9f,drm/i915/icl: split combo and tbt pll funcs,2019-03-08 19:57:26,v5.2-rc1
9be8644a14c,drm/i915/icl: split combo and mg pll disable,2019-03-08 19:57:25,v5.2-rc1
036f8d567b6,drm/i915/icl: split pll enable in three steps,2019-03-08 19:57:24,v5.2-rc1
d2ab5ebf46b,drm/i915/icl: split combo and mg pll enable,2019-03-08 19:57:23,v5.2-rc1
29b43ae2a61,drm/i915: Also use new comparative stuff for more ICP+ stuff,2019-03-13 14:43:07,v5.2-rc1
8a9a5608a31,drm/i915/icl+: Always use TPS2 or TPS3 when exiting PSR1,2019-03-12 12:57:43,v5.2-rc1
patches series of 2dd24a9c2c8,,,
1/3 2dd24a9c2c8,drm/i915/gen11+: First assume next platforms will inherit stuff,2019-03-08 13:42:58,v5.2-rc1
2/3 fba84ad28e3 ADDED!,drm/i915: Move PCH_NOP to -1,2019-03-08 13:42:59,v5.2-rc1
3/3 c6c30b917d4 ADDED!,drm/i915: Start using comparative INTEL_PCH_TYPE,2019-03-08 13:43:00,v5.2-rc1
patches series of Support 64 bpp half float formats,,,
1/3 88ab9c76d19 ADDED!,drm/fourcc: Add 64 bpp half float formats,2019-03-12 17:38:30,v5.2-rc1
2/3 42fd20edf68,drm/i915: Refactor icl_is_hdr_plane,2019-03-12 17:38:31,v5.2-rc1
3/3 a94bed60cb7,drm/i915/icl: Implement half float formats,2019-03-12 17:38:32,v5.2-rc1
26eeea15068,drm/i915/icl: Fix CRC mismatch error for DP link layer compliance,2019-03-06 18:14:12,v5.2-rc1
a89c09624f6,drm/i915: Acquire breadcrumb ref before cancelling,2019-03-04 11:41:13,v5.1-rc1
209d73530d7,drm/i915/icl: Prevent incorrect DBuf enabling,2019-03-07 12:32:35,v5.2-rc1
2909bf05626,drm/i915/icl: Remove alpha support protection,2019-03-05 14:11:53,v5.2-rc1
d846325ad0e,drm/i915/icl: Default to Thread Group preemption for compute workloads,2019-03-05 13:48:26,v5.2-rc1
patches series of Enable P0xx (planar), Y2xx/Y4xx (packed) pixel formats,,,
1/6 e1312211552 ADDED!,"drm/i915: Add P010, P012, P016 plane control definitions",2019-03-04 17:26:30,v5.2-rc1
2/6 df7d4156fe7 ADDED!,"drm/i915: Preparations for enabling P010, P012, P016 formats",2019-03-04 17:26:31,v5.2-rc1
3/6 095b1d0706b ADDED!,"drm/i915: Enable P010, P012, P016 formats for primary and sprite planes",2019-03-04 17:26:32,v5.2-rc1
4/6 50bf5d7d595 ADDED!,drm: Add Y2xx and Y4xx (xx:10/12/16) format definitions and fourcc,2019-03-04 17:26:33,v5.2-rc1
5/6 696fa001524,drm/i915/icl: Add Y2xx and Y4xx (xx:10/12/16) plane control definitions,2019-03-04 17:26:34,v5.2-rc1
6/6 296e9b19eff,drm/i915/icl: Enabling Y2xx and Y4xx (xx:10/12/16) formats for universal planes,2019-03-04 17:26:35,v5.2-rc1
3e1d87ddcf6,drm/i915: Fix the state checker for ICL Y planes,2019-03-04 15:12:17,v5.2-rc1
e781a7a3235,drm/i915: Acquire breadcrumb ref before cancelling,2019-03-04 11:41:13,v5.2-rc1
510a75a5d2b,drm/i915/icl: move MG pll hw_state readout,2019-02-22 15:23:22,v5.2-rc1
c384afe3520,drm/i915: Finalize Wa_1408961008:icl,2019-02-28 19:36:39,v5.2-rc1
37fc7845df7,drm/i915: Call MG_DP_MODE() macro with the right parameters order,2019-02-22 12:24:37,v5.2-rc1
2a3902bd5c1,drm/i915/icl: Drop redundant gamma mode mask,2019-02-21 00:35:19,v5.2-rc1
patches series of bfe0cd28518,,,
1/3 bfe0cd28518,Revert "drm/i915: W/A for underruns with WM1+ disabled on icl",2019-02-13 18:54:22,v5.2-rc1
2/3 2ed8e1f560e ADDED!,drm/i915: Include "ignore lines" in skl+ wm state,2019-02-13 18:54:23,v5.2-rc1
3/3 290248c27c9 ADDED!,drm/i915: Implement new w/a for underruns with wm1+ disabled,2019-02-13 18:54:24,v5.2-rc1
9194e42a183,drm/i915: Make combo PHY DDI macro definitions consistent for ICL and CNL,2019-01-28 14:00:11,v5.2-rc1
e6ed078d6dd,drm/i915/icl: Add degamma and gamma lut size to gen11 caps,2019-02-11 19:20:25,v5.2-rc1
a91de580541,drm/i915/icl: Enable pipe output csc,2019-02-11 19:20:24,v5.2-rc1
255fcfbc3c1,drm/i915/icl: Enable ICL Pipe CSC block,2019-02-11 19:20:23,v5.2-rc1
13717cef4c1,drm/i915/icl: Add icl pipe degamma and gamma support,2019-02-11 19:20:22,v5.2-rc1
patches series of 16eb0f34cdf,,,
1/3 fc89a38d99d ADDED!,drm/i915/opregion: fix version check,2019-02-08 20:42:52,v5.0-rc7
2/3 16eb0f34cdf,drm/i915/opregion: rvda is relative from opregion base in opregion 2.1+,2019-02-08 20:42:53,v5.0-rc7
3/3 NOT-IN-UPSTREAM,HACK: drm/i915/opregion: ICL should have opregion 2.1+ and relative rvda,,
3b91a935973,drm/i915/cnl: Fix CNL macros for Voltage Swing programming,2019-01-10 15:08:44,v5.0-rc7
9659c1af451,drm/i915/icl: combo port vswing programming changes per BSPEC,2018-12-17 14:13:47,v5.0-rc7
a0f52c3d357,drm/i915/opregion: rvda is relative from opregion base in opregion 2.1+,2019-02-08 20:42:53,v5.2-rc1
d7e449a858e,drm/i915: Just use icl+ definition for PLANE_WM blocks field,2019-02-05 22:50:56,v5.1-rc1
c7e716b8617,drm/i915: Bump skl+ wm blocks to 11 bits,2019-02-05 22:50:55,v5.1-rc1
patches series of bf002c10074,,,
1/4 0aded171e20 ADDED!,drm/i915: Fix wm latency==0 disable on skl+,2019-02-05 17:50:53,v5.1-rc1
2/4 NOT-IN-UPSTREAM,drm/i915: Extract skl_set_pipe_chicken(),,
3/4 108d14bdaef,drm/i915: Setup PIPE_CHICKEN for fastsets too,2019-02-04 22:22:14,v5.1-rc1
4/4 bf002c10074,drm/i915: W/A for underruns with WM1+ disabled on icl,2019-02-04 22:22:32,v5.1-rc1
d16221195ae,drm/i915: Extract icl_set_pipe_chicken(),2019-02-04 22:21:39,v5.1-rc1
2a121030d4e,drm/i915: always return something on DDI clock selection,2019-01-25 14:24:42,v5.0-rc6
e46c2e99f60,drm/i915: Expose RPCS (SSEU) configuration to userspace (Gen11 only),2019-02-05 09:50:31,v5.1-rc1
ec431eae8fc,drm/i915/perf: lock powergating configuration to default when active,2019-02-05 09:50:29,v5.1-rc1
patches series of restore WaEnableFloatBlendOptimization,,,
1/3 69b768f2bc6 ADDED!,drm/i915: Move workaround infrastructure code up,2019-01-31 17:08:42,v5.1-rc1
2/3 ae598b0d6b5 ADDED!,drm/i915: Save some lines of source code in workarounds,2019-01-31 17:08:43,v5.1-rc1
3/3 0b904c890ac,drm/i915/icl: restore WaEnableFloatBlendOptimization,2019-01-31 17:08:44,v5.1-rc1
patches series of 2b34e562361,,,
1/3 e9d49bb718f ADDED!,drm/i915/ddi: Move DDI port detection to the corresponding helper,2018-12-20 15:26:02,v5.1-rc1
2/3 3f2e9ed0b26,drm/i915/icl: Detect port F presence via VBT,2018-12-20 15:26:03,v5.1-rc1
3/3 2b34e562361,drm/i915/icl: Work around broken VBTs for port F detection,2018-12-20 17:52:11,v5.1-rc1
828ccb31cf4,drm/i915/icl: Add TypeC ports only if VBT is present,2019-01-28 13:42:42,v5.1-rc1
8aae2b1cdf4,drm/i915: Pick the first unused PLL once again,2019-01-30 20:13:59,v5.1-rc1
ad3e7b824c1,drm/i915: Don't use the second dbuf slice on icl,2019-01-30 17:51:10,v5.1-rc1
patches series of skl+ watermark stuff,,,
1/9 b52c273be68 ADDED!,drm/i915: Don't ignore level 0 lines watermark for glk+,2018-12-21 19:14:28,v5.1-rc1
2/9 692927f4e90 ADDED!,drm/i915: Reinstate an early latency==0 check for skl+,2018-12-21 19:14:29,v5.1-rc1
3/9 17b16054b11 ADDED!,drm/i915: Fix bits vs. bytes mixup in dbuf block size computation,2018-12-21 19:14:30,v5.1-rc1
4/9 b19c9bcaa20 ADDED!,drm/i915: Fix > vs >= mismatch in watermark/ddb calculations,2018-12-21 19:14:31,v5.1-rc1
5/9 961d95e09c0,drm/i915: Account for minimum ddb allocation restrictions,2018-12-21 19:14:32,v5.1-rc1
6/9 60e983ff187 ADDED!,drm/i915: Pass dev_priv to skl_needs_memory_bw_wa(),2018-12-21 19:14:33,v5.1-rc1
7/9 ff61a97499f ADDED!,drm/i915: Drop the definite article in front of SAGV,2018-12-21 19:14:34,v5.1-rc1
8/9 ff58c11cdbe ADDED!,drm/i915: Drop the pointless linetime==0 check,2018-12-21 19:14:35,v5.1-rc1
9/9 717671c610f ADDED!,drm/i915: Use IS_GEN9_LP() for the linetime w/a check,2018-12-21 19:14:36,v5.1-rc1
5b0bd14dcc6,drm/i915/icl: keep track of unused pll while looping,2019-01-25 14:24:44,v5.1-rc1
20fd2ab7be4,drm/i915/icl: remove dpll from clk_sel,2019-01-25 14:24:43,v5.1-rc1
7a61a6dec3d,drm/i915: always return something on DDI clock selection,2019-01-25 14:24:42,v5.1-rc1
584fca111d0,drm/i915/icl: use tc_port in MG_PLL macros,2019-01-25 14:24:41,v5.1-rc1
patches series of Define MOCS table for Icelake,,,
1/7 NOT-IN-UPSTREAM,"drm/i915: keep track of used entries in MOCS table",,
2/7 7f92e6c2aec ADDED!,drm/i915: initialize unused MOCS entries to PTE,2019-01-23 16:05:58,v5.1-rc1
3/7 66f996052f9 ADDED!,drm/i915/skl: Rework MOCS tables to keep common part in a define,2019-01-23 16:06:00,v5.1-rc1
4/7 828f3150204 ADDED!,drm/i915: use a macro to define MOCS entries,2019-01-23 16:06:01,v5.1-rc1
5/7 1878fce8de2 ADDED!,drm/i915: keep track of used entries in MOCS table,2019-01-23 16:06:02,v5.1-rc1
6/7 5029537f4fb,drm/i915: cache number of MOCS entries,2019-01-23 16:06:03,v5.1-rc1
7/7 b3c316b0b86,drm/i915/icl: Define MOCS table for Icelake,2019-01-23 16:06:04,v5.1-rc1
85e2d61e497,drm/i915: Validate userspace-provided color management LUT's (v4),2018-12-18 09:51:58,v5.1-rc1
c25f0c6a042,drm/i915/icl: do a posting read after irq install,2019-01-22 18:32:27,v5.1-rc1
293f8c0f2bb,drm/i915: Use b->irq_enable() as predicate for mock engine,2019-01-18 11:22:25,v5.1-rc1
1b4bd5c4a66,drm/i915: Limit the for_each_set_bit() to the valid range,2019-01-16 15:54:21,v5.1-rc1
b14c06ec024,drm/i915/cnl: Fix CNL macros for Voltage Swing programming,2019-01-10 15:08:44,v5.1-rc1
patches series of More watermarks improvements,,,
01/11 a5b79d34000,drm/i915: don't apply Display WAs 1125 and 1126 to GLK/CNL+,2018-11-13 17:24:32,v5.1-rc1
02/11 eeba5b5cdea ADDED!,drm/i915: remove padding from struct skl_wm_level,2018-10-16 15:01:24,v5.0-rc1
03/11 NOT-IN-UPSTREAM,drm/i915: fix handling of invisible planes in watermarks code,,
04/11 NOT-IN-UPSTREAM,drm/i915: remove useless memset() for watermarks parameters,,
05/11 NOT-IN-UPSTREAM,drm/i915: simplify wm->is_planar assignment,,
06/11 NOT-IN-UPSTREAM,drm/i915: refactor skl_write_plane_wm(),,
07/11 NOT-IN-UPSTREAM,drm/i915: move ddb_blocks to be a watermark parameter,,
08/11 NOT-IN-UPSTREAM,drm/i915: reorganize the error message for invalid watermarks,,
09/11 NOT-IN-UPSTREAM,drm/i915: make skl_needs_memory_bw_wa() take dev_priv instead of state,,
10/11 NOT-IN-UPSTREAM,drm/i915: add pipe_htotal to struct skl_wm_params,,
11/11 NOT-IN-UPSTREAM,drm/i915: pass dev_priv instead of cstate to skl_compute_transition_wm(),,
patches series of drm/i915/icl: Fix TypeC Legacy HPD handling,,,
1/4 f0236a852cd,drm/i915/icl: Add a debug print for TypeC port disconnection,2018-12-14 20:27:00,v5.1-rc1
2/4 38b3416f3c2 ADDED!,drm/i915/bios: Parse the VBT TypeC and Thunderbolt port flags,2018-12-14 20:27:01,v5.1-rc1
3/4 f6bff60e927,drm/i915/icl: Fix HPD handling for TypeC legacy ports,2018-12-14 20:27:02,v5.1-rc1
4/4 2a041c97c3b,drm/i915/icl: Add fallback detection method for TypeC legacy ports,2018-12-14 20:27:03,v5.1-rc1
b265a2a6255,drm/i915/icl: combo port vswing programming changes per BSPEC,2018-12-17 14:13:47,v5.1-rc1
f513ac76530,drm/i915/icl: Mind the SFC units when resetting VD or VEBox engines,2018-12-13 09:15:22,v5.1-rc1
57b19d55189,drm/i915/icl: Record the valid VDBoxes with SFC capability,2018-12-13 09:15:21,v5.1-rc1
d8f50531171,drm/i915/icl: Forcibly evict stale csb entries,2018-12-05 15:46:12,v5.1-rc1
90098efacc4,drm/i915: Introduce per-engine workarounds,2018-12-05 11:33:24,v5.0-rc1
patches series of d15f9cdd59b,,,
1/9 1035f4a65f5 ADDED!,drm/i915: Disable PSR in Apple panels,2018-12-03 16:33:55,v5.0-rc2
2/9 60cae44251e ADDED!,drm/i915/psr: Don't tell sink that main link will be active while is active PSR2,2018-12-03 16:33:56,v5.1-rc1
3/9 de570946c0e ADDED!,drm/i915/psr: Set PSR CRC verification bit in sink inside PSR1 block,2018-12-03 16:33:57,v5.1-rc1
4/9 98751b8cd60 ADDED!,drm/i915/psr: Enable sink to trigger a interruption on PSR2 CRC mismatch,2018-12-03 16:33:58,v5.1-rc1
5/9 d15f9cdd59b,drm/i915/icl: Do not change reserved registers related to PSR2,2018-12-03 16:33:59,v5.1-rc1
6/9 227939a1c46 ADDED!,drm/i915: Remove old PSR2 FIXME about frontbuffer tracking,2018-12-03 16:34:00,v5.1-rc1
7/9 NOT-IN-UPSTREAM,drm: Add the PSR SU granularity registers offsets,,
8/9 bef5e5b3bee ADDED!,drm/i915/psr: Check if resolution is supported by default SU granularity,2018-12-03 16:34:02,v5.1-rc1
9/9 8c0d2c29083 ADDED!,drm/i915/psr: Check if source supports sink specific SU granularity,2018-12-03 16:34:03,v5.1-rc1
0716931a82b,drm/i915/icl: fix transcoder state readout,2018-12-04 12:19:26,v5.0-rc1
patches series of Restore workarounds after engine reset and unify their handling,,,
1/7 009367791f3 ADDED!,drm/i915: Record GT workarounds in a list,2018-12-05 11:33:23,v5.0-rc1
2/7 4a15c75c424,drm/i915: Introduce per-engine workarounds,2018-12-03 13:33:41,v5.0-rc1
3/7 094304beb4e ADDED!,drm/i915: Verify GT workaround state after GPU init,2018-12-03 12:50:10,v5.0-rc1
4/7 28d6ccce73b ADDED!,drm/i915/selftests: Add tests for GT and engine workaround verification,2018-12-03 12:50:11,v5.0-rc1
5/7 69bcdecf1af ADDED!,drm/i915: Move register white-listing to the common workaround framework,2018-12-03 12:50:12,v5.0-rc1
6/7 452420d22d5 ADDED!,drm/i915: Fuse per-context workaround handling with the common framework,2018-12-03 13:33:57,v5.0-rc1
7/7 4d8d9fc7050 ADDED!,drm/i915: Trim unused workaround list entries,2018-12-03 12:50:14,v5.0-rc1
949fc52af19,drm/i915/icl: add pll mapping for DSI,2018-12-03 11:43:26,v5.0-rc1
1026bea0038,drm/i915/icl: Ungate DSI clocks,2018-11-29 16:12:34,v5.0-rc1
32250c8e0ef,drm/i915/icl: Gate clocks for DSI,2018-11-29 16:12:33,v5.0-rc1
690c318ed8e,drm/i915/icl: add dummy DSI GPIO element execution function,2018-11-29 16:12:32,v5.0-rc1
56b7b1aa13b,drm/i915/icl: Define display GPIO pins for DSI,2018-11-29 16:12:31,v5.0-rc1
f4ff2120301,drm/i915/icl: Define Panel power ctrl register,2018-11-29 16:12:30,v5.0-rc1
05f2f03dd20,drm/i915/icl: Define missing bitfield for shortplug reg,2018-11-29 16:12:29,v5.0-rc1
2eae5d6bfa5,drm/i915/icl: Get pipe timings for DSI,2018-11-29 16:12:28,v5.0-rc1
2ca711caeca,drm/i915/icl: Consider DSI for getting transcoder state,2018-11-29 16:12:27,v5.0-rc1
5a8507b5aa8,drm/i915/icl: Configure DSI Dual link mode,2018-11-29 16:12:26,v5.0-rc1
d04afb15017,drm/i915/icl: Add DSI encoder compute config hook,2018-11-29 16:12:25,v5.0-rc1
ab8411483a3,drm/i915/icl: Get HW state for DSI encoder,2018-11-29 16:12:24,v5.0-rc1
8327af281d2,drm/i915/icl: Add get config functionality for DSI,2018-11-29 16:12:23,v5.0-rc1
c5f9c934936,drm/i915/icl: Allocate DSI hosts and imlement host transfer,2018-11-29 16:12:22,v5.0-rc1
972d607c59e,drm/i915/icl: Fill DSI ports info,2018-11-29 16:12:21,v5.0-rc1
95f2f4dbb19,drm/i915/icl: Use the same pll functions for dsi,2018-11-29 16:12:20,v5.0-rc1
e2758048732,drm/i915/icl: Allocate DSI encoder/connector,2018-11-29 16:12:19,v5.0-rc1
70a057b7d42,drm/i915/icl: Calculate DPLL params for DSI,2018-11-29 16:12:18,v5.0-rc1
1dd07e56a3f,drm/i915/icl: Sanitize DDI port clock gating for DSI ports,2018-11-29 16:12:17,v5.0-rc1
3b8c0d5bc9f,drm/i915/icl: push pll to port mapping/unmapping to ddi encoder hooks,2018-11-29 16:12:16,v5.0-rc1
f545425a014,drm/i915/icl: Remove Wa_1604302699,2018-11-29 13:46:30,v5.0-rc1
91ba2c8be4b,drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI,2018-11-28 12:26:18,v5.0-rc1
patches series of drm/i915: Program SKL+ watermarks/ddb more carefully,,,
01/13 83234d13f9f ADDED!,drm/i915: Reorganize plane register writes to make them more atomic,2018-11-14 23:07:17,v5.0-rc1
02/13 019575a58c8 ADDED!,drm/i915: Move single buffered plane register writes to the end,2018-11-14 23:07:18,v5.0-rc1
03/13 afbd8a722bd,drm/i915: Introduce crtc_state->update_planes bitmask,2018-11-27 18:37:42,v5.0-rc1
04/13 0dd14be30d4 ADDED!,drm/i915: Pass the new crtc_state to ->disable_plane(),2018-11-14 23:07:20,v5.0-rc1
05/13 ce110ec311e ADDED!,drm/i915: Fix latency==0 handling for level 0 watermark on skl+,2018-11-14 23:07:21,v5.0-rc1
06/13 14a43062b90 ADDED!,drm/i915: Remove some useless zeroing on skl+ wm calculations,2018-11-14 23:07:22,v5.0-rc1
07/13 6a3c910b081 ADDED!,drm/i915: Pass the entire skl_plane_wm to skl_compute_transition_wm(),2018-11-14 23:07:23,v5.0-rc1
08/13 8315847bf4d,drm/i915: Clean up skl+ vs. icl+ watermark computation,2018-11-27 18:57:26,v5.0-rc1
09/13 51de9c6d255 ADDED!,drm/i915: Don't pass dev_priv around so much,2018-11-14 23:07:25,v5.0-rc1
10/13 ff43bc379e1 ADDED!,drm/i915: Move ddb/wm programming into plane update/disable hooks on skl+,2018-11-27 18:59:00,v5.0-rc1
11/13 5f2e511205b ADDED!,drm/i915: Commit skl+ planes in an order that avoids ddb overlaps,2018-11-14 23:07:27,v5.0-rc1
12/13 45bee430b84 ADDED!,drm/i915: Rename the confusing 'plane_id' to 'color_plane',2018-11-14 23:07:28,v5.0-rc1
13/13 1fdee7582cc,drm/i915: Pass the plane to icl_program_input_csc_coeff(),2018-11-14 23:07:29,v5.0-rc1
patches series of c6e1f8cc885,,,
1/3 6233016484c,drm/i915/icl: replace check for combo phy,2018-11-13 17:15:07,v5.0-rc1
2/3 c6e1f8cc885,drm/i915/icl: reverse uninit order,2018-11-13 17:15:08,v5.0-rc1
3/3 56d4eac0a1e ADDED!,drm/i195: spell out reverse on for_each macros,2018-11-13 17:15:09,v5.0-rc1
a22612301ae,drm/i915/icl: Drop spurious register read from icl_dbuf_slices_update,2018-11-09 16:09:23,v5.0-rc1
745aa6cdee6,drm/i915: Fix icl workarounds whitespaces,2018-11-09 16:53:33,v5.0-rc1
85f04aa569a,drm/i915: Deduplicate register definition for GAMW_ECO_DEV_RW_IA,2018-11-09 16:53:32,v5.0-rc1
8577c319b65,drm/i915/icl: Drop spurious register read from icl_dbuf_slices_update,2018-11-09 16:09:23,v5.0-rc1
patches series of 228a5cf381f,,,
1/3 af4de6adb49 ADDED!,drm/i915/cnp+: update to the new RAWCLK_FREQ recommendations,2018-11-12 15:23:11,v5.0-rc1
2/3 228a5cf381f,drm/i915: rename CNP_RAWCLK_FRAC to CNP_RAWCLK_DEN,2018-11-12 15:23:12,v5.0-rc1
3/3 704e504bd61,drm/i915: add ICP support to cnp_rawclk() and kill icp_rawclk(),2018-11-12 15:23:13,v5.0-rc1
c4f224076d0,drm/i915/icl: Fix power well 2 wrt. DC-off toggling order,2018-11-02 20:22:00,v5.0-rc1
def40774f63,drm/i915/gvt: not to touch undefined MOCS registers,2018-10-29 14:18:25,v5.0-rc1
patches series of 62819dfd859,,,
1/4 26f9ec9a9a4 ADDED!,drm/i915/psr: Use intel_psr_exit() in intel_psr_disable_source(),2018-11-06 11:08:40,v5.0-rc1
2/4 b2fc2252ce4 ADDED!,drm/i915/psr: Always wait for idle state when disabling PSR,2018-11-06 11:08:41,v5.0-rc1
3/4 62819dfd859,drm/i915/icl: Reset PSR interruptions,2018-11-06 11:08:42,v5.0-rc1
4/4 2ee936e3a2f ADDED!,drm/i915/psr: Move intel_psr_disable_source() code to intel_psr_disable_locked(),2018-11-06 11:08:43,v5.0-rc1
patches series of 30f5ccfa8c8,,,
1/2 9199c322ec8 ADDED!,drm/i915/ddi: Add more sanity check to the encoder HW readout,2018-11-07 22:08:35,v5.0-rc1
2/2 30f5ccfa8c8,drm/i915/icl: Fix PLL mapping sanitization for DP ports,2018-11-07 22:08:36,v5.0-rc1
patches series of drm/i915/icl: Fix combo PHY HW context loss,,,
1/5 1e0e9c8a85a,drm/i915/icl: Fix combo PHY uninit,2018-11-06 18:06:17,v5.0-rc1
2/5 c45198b163f ADDED!,drm/i915/cnl+: Move the combo PHY init/uninit code to a new file,2018-11-06 18:06:18,v5.0-rc1
3/5 eef519e2d07,drm/i915/cnl+: Verify combo PHY HW state during PHY uninit,2018-11-06 18:06:19,v5.0-rc1
4/5 bc458c1174e,drm/i915/icl: Skip init for an already enabled combo PHY,2018-11-06 18:06:20,v5.0-rc1
5/5 602438ead30,drm/i915/icl: Fix port B combo PHY context loss after DC transitions,2018-11-06 18:06:21,v5.0-rc1
a33e1ece777,drm/i915/icl: Fix power well 2 wrt. DC-off toggling order,2018-11-02 20:22:00,v5.0-rc1
e528c2affcf,drm/i915/icl: Fix the macros for DFLEXDPMLE register bits,2018-10-23 12:12:47,v5.0-rc1
76271ef2638,drm/i915: Fix VIDEO_DIP_CTL bit shifts,2018-10-05 11:56:42,v5.0-rc1
bfe60a0272d,drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion,2018-11-02 00:40:20,v5.0-rc1
6a255da783c,drm/i915/icl: Define Plane Input CSC Coefficient Registers,2018-11-02 00:40:19,v5.0-rc1
93b662d329d,drm/i915/icl: Configure MG DP mode for HDMI ports too,2018-11-02 21:26:56,v5.0-rc1
cb9ff519439,drm/i915/icl: Configure MG PHY gating for HDMI ports too,2018-11-02 21:26:55,v5.0-rc1
18cde299df3,drm/i915/icl: Fix DSS_CTL register names,2018-11-01 14:42:16,v5.0-rc1
patches series of drm/i915/icl: Fix HDMI on TypeC static ports,,,
1/8 15d248ae374,drm/i915: Move intel_aux_ch() to intel_bios.c,2018-11-01 16:04:20,v5.0-rc1
2/8 563d22a0394,drm/i915: Move aux_ch to intel_digital_port,2018-11-01 16:04:21,v5.0-rc1
3/8 ac897d6bd70,drm/i915: Init aux_ch for HDMI ports too,2018-11-01 16:04:22,v5.0-rc1
4/8 337837ac3a7,drm/i915: Use a helper to get the aux power domain,2018-11-01 16:04:23,v5.0-rc1
5/8 bdaa29b6bea,drm/i915: Enable AUX power earlier,2018-11-01 16:04:24,v5.0-rc1
6/8 8e4a3ad9b81,drm/i915: Enable AUX power for HDMI DDI/TypeC main link too,2018-11-01 16:04:25,v5.0-rc1
7/8 c7375d9542f ADDED!,drm/i915: Configure AUX_CH_CTL when enabling the AUX power domain,2018-11-01 16:04:26,v5.0-rc1
8/8 70332ac539c,drm/i915/icl+: Sanitize port to PLL mapping,2018-11-01 16:04:27,v5.0-rc1
f57f9371e28,drm/i915/icl: WaAllowUMDToModifySamplerMode,2018-10-30 01:45:04,v5.0-rc1
6a00b8feb86,drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7,2018-10-30 01:45:03,v5.0-rc1
22dae8a0cc5,drm/i915/icl: Implement Display WA_1405510057,2018-10-30 01:45:02,v5.0-rc1
622b3f68139,drm/i915/icl: Add WaEnable32PlaneMode,2018-10-30 01:45:01,v5.0-rc1
3b6ac43b485,drm/i915/icl: Fix DC9 Suspend for ICL.,2018-10-31 13:27:26,v5.0-rc1
8b1b558d690,drm/i915/icl: Add DSS_CTL Registers,2018-10-30 13:56:35,v5.0-rc1
f968c85bcef,drm/i915/icl: Don't wait for empty FIFO,2018-10-30 13:56:42,v5.0-rc1
bf4d57ff411,drm/i915/icl: Find DSI presence for ICL,2018-10-30 13:56:23,v5.0-rc1
808517e2c37,drm/i915/icl: Add DSI packet payload/header registers,2018-10-30 13:56:26,v5.0-rc1
03ad7d8821e,drm/i915/ICL: Add pre_pll_enable hook for ICL and set DFLEXDPMLE in this hook,2018-10-23 12:12:48,v5.0-rc1
b4335ec0a3e,drm/i915/icl: Fix the macros for DFLEXDPMLE register bits,2018-10-23 12:12:47,v5.0-rc1
patches series of d1b5973c877,,,
1/5 3e037f9b0ab ADDED!,drm/i915/debugfs: Do not print cached information of a disconnected sink,2018-10-30 14:57:46,v5.0-rc1
2/5 b298ba5f51f,drm/i915/icl: Set TC type to unknown in the disconnection flow,2018-10-30 14:57:47,v5.0-rc1
3/5 d1b5973c877,drm/i915/icl: Set TC type to unknown when a sudden disconnection happen,2018-10-30 14:57:48,v5.0-rc1
4/5 36b80aa36b6 ADDED!,drm/i915: Initialize panel_vdd_work only for eDP ports,2018-10-30 14:57:49,v5.0-rc1
5/5 17a3b15ac6a,drm/i915/icl: Fix crash when getting DPLL of a MST encoder in TC ports,2018-10-30 14:57:50,v5.0-rc1
5a4712f472b,drm/i915/icl: Program HS_TX_TIMEOUT/LP_RX_TIMEOUT/TA_TIMEOUT registers,2018-10-30 13:56:22,v5.0-rc1
8bffd204ded,drm/i915/icl: Define DSI timeout registers,2018-10-30 13:56:21,v5.0-rc1
0f0fe8497d9,drm/i915/icl: Disable DSI IO power,2018-10-30 13:56:20,v5.0-rc1
019cec36f37,drm/i915/icl: Disable DSI ports,2018-10-30 13:56:19,v5.0-rc1
9c83ab1bb38,drm/i915/icl: Disable portsync mode,2018-10-30 13:56:18,v5.0-rc1
7aa32f7c47c,drm/i915/icl: Disable DDI function,2018-10-30 13:56:17,v5.0-rc1
4769b598b94,drm/i915/icl: Put DSI link in ULPS,2018-10-30 13:56:16,v5.0-rc1
522cc3f717a,drm/i915/icl: Power down DSI panel,2018-10-30 13:56:15,v5.0-rc1
4e123bd3039,drm/i915/icl: Disable DSI transcoders,2018-10-30 13:56:14,v5.0-rc1
d9d996b6ca4,drm/i915/icl: Turn OFF panel backlight,2018-10-30 13:56:13,v5.0-rc1
208013157a6,drm/i915/icl: Turn ON panel backlight,2018-10-30 13:56:12,v5.0-rc1
32bbc3d450d,drm/i915/icl: Wait for header/payload credits release,2018-10-30 13:56:11,v5.0-rc1
c2661638e88,drm/i915/icl: Power on DSI panel,2018-10-30 13:56:10,v5.0-rc1
bfee32bfca8,drm/i915/icl: Set max return packet size for DSI panel,2018-10-30 13:56:09,v5.0-rc1
0d90c61ab9b,drm/i915/dsi: move connector mode functions to common file,2018-10-30 13:56:08,v5.0-rc1
8e54d4fe79f,drm/i915/icl: Move dsi host init code to common file,2018-10-30 13:56:07,v5.0-rc1
3e68928b7d4,drm/i915/icl: Enable DC9 as lowest possible state during screen-off,2018-10-29 15:14:10,v5.0-rc1
patches series of 77cac774b2f,,,
1/2 2a11b1b4b68 ADDED!,drm/i915: Add function to check for linear surfaces,2018-10-26 12:38:04,v5.0-rc1
2/2 77cac774b2f,drm/i915: Do not program aux plane offsets on gen11+,2018-10-26 12:38:05,v5.0-rc1
patches series of 09209662618,,,
1/2 09209662618,drm/i915: Fix VIDEO_DIP_CTL bit shifts,2018-10-05 11:56:42,v5.0-rc1
2/2 a670be33050 ADDED!,drm/i915: Move VIDEO_DIP_CTL definitions to their right place.,2018-10-05 11:56:43,v5.0-rc1
patches series of 9e7833758b9,,,
1/2 9e7833758b9,drm/i915: Prefer IS_GEN<n> check with bitmask.,2018-10-26 12:51:42,v5.0-rc1
2/2 5bc0e89ff1b ADDED!,drm/i915: Kill GEN_FOREVER,2018-10-26 12:51:43,v5.0-rc1
9213e4f5444,drm/i915/icl: Store available engine masks in INTEL_INFO,2018-10-18 11:41:06,v5.0-rc1
b5a209ca183,drm/i915: Mark skl_update_plane and skl_disable_plane as static,2018-10-24 11:54:02,v5.0-rc1
26ee5bc3901,"drm/i915/gen11: Expose planar format support on gen11, v2.",2018-10-22 15:45:14,v5.0-rc1
1e364f9008a,"drm/i915/gen11: Program the Y and UV plane for planar mode correctly, v3.",2018-10-18 13:51:33,v5.0-rc1
cb2458baf8b,drm/i915/gen11: Program the chroma upsampler for HDR planes.,2018-10-18 13:51:32,v5.0-rc1
b1554e23ccb,"drm/i915/gen11: Program the scalers correctly for planar formats, v3.",2018-10-18 13:51:31,v5.0-rc1
b048a00b3d9,"drm/i915/gen11: Handle watermarks correctly for separate Y/UV planes, v2.",2018-10-18 13:51:30,v5.0-rc1
1ab554b0099,"drm/i915/gen11: Link nv12 Y and UV planes in the atomic state, v5.",2018-10-22 15:51:52,v5.0-rc1
6711bd730b3,drm/i915/gen11: Enable 6 sprites on gen11,2018-10-18 13:51:28,v5.0-rc1
24719e94ca2,"drm/i915: Fix unsigned overflow when calculating total data rate, v2.",2018-10-22 12:20:00,v5.0-rc1
patches series of Sorting "if" blocks and statements from newer to older platform,,,
1/5 fdec4df43ca ADDED!,drm/i915: ddi_clock_get sort platforms newer-to-older.,2018-10-22 10:15:22,v5.0-rc1
2/5 36c1f02875c ADDED!,drm/i915: compute_min_voltage_level sort platforms newer-to-older,2018-10-22 10:15:23,v5.0-rc1
3/5 210126bd807,drm/i915: digital_port_connected sort platforms newer-to-older,2018-10-22 10:15:24,v5.0-rc1
4/5 fb72deaefe5 ADDED!,drm/i915: power_domains_init sort platforms newer-to-older,2018-10-22 10:15:25,v5.0-rc1
5/5 ac128918482 ADDED!,drm/i915: uncore_fw_domains_init sort platforms newer-to-older,2018-10-22 10:15:26,v5.0-rc1
60230aacd52,drm/i915/icl: Define DSI panel programming registers,2018-10-15 17:28:06,v5.0-rc1
303e347cebc,drm/i915/icl: Enable DSI transcoders,2018-10-15 17:28:05,v5.0-rc1
372610f3c81,drm/i915/icl: Define TRANS_CONF register for DSI,2018-10-15 17:28:04,v5.0-rc1
d1aeb5f399d,drm/i915/icl: Configure DSI transcoder timings,2018-10-15 17:28:03,v5.0-rc1
7b56caf3637,drm/i915/icl: Define DSI transcoder timing registers,2018-10-15 17:28:02,v5.0-rc1
70f4f502c47,drm/i915/icl: Program TRANS_DDI_FUNC_CTL registers,2018-10-15 17:28:01,v5.0-rc1
49edbd49786,drm/i915/icl: Define TRANS_DDI_FUNC_CTL DSI registers,2018-10-15 17:28:00,v5.0-rc1
d364dc66e2d,drm/i915/icl: Configure DSI transcoders,2018-10-15 17:27:59,v5.0-rc1
5ffce254623,drm/i915/icl: Define TRANS_DSI_FUNC_CONF register,2018-10-15 17:27:58,v5.0-rc1
292272ee7e9,drm/i915/icl: Add macros for MMIO of DSI transcoder registers,2018-10-15 17:27:57,v5.0-rc1
ca8fc99f2ac,drm/i915/icl: Get DSI transcoder for a given port,2018-10-15 17:27:56,v5.0-rc1
5fea8645585,drm/i915/icl: Program TA_TIMING_PARAM registers,2018-10-15 17:27:55,v5.0-rc1
e72cce53101,drm/i915/icl: Program DSI clock and data lane timing params,2018-10-15 17:27:54,v5.0-rc1
b687c1984c4,drm/i915/icl: Make common DSI functions available,2018-10-15 17:27:53,v5.0-rc1
67551a70354,drm/i915/dsi: abstract dphy parameter init,2018-10-15 17:27:51,v5.0-rc1
2bf3f59daee,drm/i915/dsi: refactor bitrate calculations in intel_dsi_vbt_init(),2018-10-15 17:27:50,v5.0-rc1
835fe6d75d1,firmware/dmc/icl: Add missing MODULE_FIRMWARE() for Icelake.,2018-10-04 15:36:13,v5.0-rc1
b4ec5f39e4a,drm/i915/icl: Fix signal_levels,2018-10-17 14:56:52,v5.0-rc1
83db3738530,drm/i915/icl: Fix DDI/TC port clk_off bits,2018-10-15 19:37:52,v5.0-rc1
a9b84b44927,drm/i915/icl: create function to identify combophy port,2018-10-04 14:20:43,v5.0-rc1
61cdfb9e194,drm/i915/icl: Fix signal_levels,2018-10-17 14:56:52,v5.0-rc1
bb1c7edc6d4,drm/i915/icl: Fix DDI/TC port clk_off bits,2018-10-15 19:37:52,v5.0-rc1
4e53840fdfd,drm/i915/icl: Introduce new macros to get combophy registers,2018-10-15 19:35:17,v5.0-rc1
d72e84ccba2,drm/i915/icl: Combine all port/combophy macros at one place,2018-10-12 16:47:17,v5.0-rc1
a54270d3a91,drm/i915/icl: Refactor icl pll functions,2018-10-03 12:52:00,v5.0-rc1
8ea59e67399,drm/i915/icl: Use helper functions to classify the ports,2018-10-03 12:51:59,v5.0-rc1
cb6caf7e399,drm/i915/icl: Refactor get_ddi_pll using helper func,2018-10-03 12:51:58,v5.0-rc1
c0aa834404b,drm/i915/icl: use combophy/TC helper functions during display detection,2018-10-03 12:51:57,v5.0-rc1
176597a12d6,drm/i915/icl: create function to identify combophy port,2018-10-04 14:20:43,v5.0-rc1
ffd7e32d95d,drm/i915/icl: apply Display WA #1178 to fix type C dongles,2018-10-12 14:57:58,v5.0-rc1
patches series of drm/i915: Remove low hanging crtc->config fruit, part 2.,,,
02/10 4c35475485c ADDED!,drm/i915: Make intel_dp_set_m_n take crtc_state,2018-10-11 12:04:49,v5.0-rc1
03/10 92d54b078fe ADDED!,drm/i915: Remove crtc->config references in vlv_prepare_pll,2018-10-11 12:04:50,v5.0-rc1
05/10 f2bdd112685 ADDED!,drm/i915: Pass crtc_state to update_scanline_offset,2018-10-11 12:04:52,v5.0-rc1
06/10 1b52ad46162 ADDED!,drm/i915: Remove crtc->config dereferences in intel_sanitize_crtc,2018-10-11 12:04:53,v5.0-rc1
07/10 91d78197629 ADDED!,drm/i915: Remove crtc->config dereferences in intel_modeset_setup_hw_state,2018-10-11 12:04:54,v5.0-rc1
08/10 c5b36facfad,drm/i915: Pass crtc_state to lpt_program_iclkip,2018-10-11 12:04:55,v5.0-rc1
09/10 b0b62d845e4 ADDED!,drm/i915: Pass crtc_state to ivybridge_update_fdi_bc_bifurcation,2018-10-11 12:04:56,v5.0-rc1
1/10 138bdac8918 ADDED!,drm/i915: Remove crtc->config dereference from drrs_ctl,2018-10-11 12:04:48,v5.0-rc1
10/10 NOT-IN-UPSTREAM,drm/i915: Remove crtc->active from crtc_enable callbacks,,
4/10 NOT-IN-UPSTREAM,drm/i915: Always read out M2_N2 in intel_cpu_transcoder_get_m_n,,
patches series of 95b0e7c14c5,,,
1/3 4376b9c965c ADDED!,drm/i915/gen8: Disable master intr before reading,2018-10-15 17:14:38,v5.0-rc1
2/3 95b0e7c14c5,drm/i915/icl: No need to ack intr through master control,2018-10-15 17:14:39,v5.0-rc1
3/3 81067b71c1d,drm/i915/icl: Disable master intr before reading,2018-10-15 17:14:40,v5.0-rc1
04c388d4295,drm/i915/icl: enable SAGV for ICL platform,2018-10-11 15:57:25,v5.0-rc1
27d7aaae0fd,drm/i915/csr Added DC5 and DC6 counter register for ICL in debugfs entry.,2018-10-05 14:08:46,v5.0-rc1
71ffd49cc9b,drm/i915/icl:Add Wa_1606682166,2018-10-04 11:29:39,v5.0-rc1
0c7d2aedf51,drm/i915/icl: Add Wa_1406609255,2018-10-04 11:29:38,v5.0-rc1
fc6ff9dc9ec,drm/i915/psr: Make MASK_DISP_REG_WRITE reserved in PSR_MASK for ICL,2018-10-03 13:50:26,v5.0-rc1
00e5d8b1eb4,firmware/dmc/icl: Add missing MODULE_FIRMWARE() for Icelake.,2018-10-04 15:36:13,v5.0-rc1
443d5e3973e,drm/i915/icl: MBUS B credit change,2018-10-04 08:18:14,v5.0-rc1
patches series of drm/i915: First cleanup pass to get rid of more crtc->config users.,,,
02/13 b2562712d7d ADDED!,drm/i915: Make panel fitter functions take state,2018-10-04 11:45:53,v5.0-rc1
03/13 44fe7f35528 ADDED!,drm/i915: Make intel_set_pipe_timings/src_size take a pointer to crtc_state,2018-10-04 11:45:54,v5.0-rc1
05/13 15cbe5d0926 ADDED!,drm/i915: Make skl_detach_scalers take crtc_state,2018-10-04 11:45:56,v5.0-rc1
06/13 b2354c78b12 ADDED!,"drm/i915: Make pll functions take crtc_state, v2.",2018-10-04 11:45:57,v5.0-rc1
07/13 5e1cdf541b2 ADDED!,drm/i915: Make ironlake_pch_transcoder_set_timings take crtc_state,2018-10-04 11:45:58,v5.0-rc1
08/13 NOT-IN-UPSTREAM,drm/i915: Make shared dpll functions take crtc_state,,
09/13 0e5fa64610f,drm/i915: Get rid of crtc->config from icl_pll_to_ddi_pll_sel,2018-10-04 11:46:00,v5.0-rc1
1/13 fdf73510ca8 ADDED!,"drm/i915: Remove dereferences of crtc->config in set_pipeconf/misc functions, v2.",2018-10-04 11:45:52,v5.0-rc1
10/13 6e3d9dd0ae0 ADDED!,drm/i915: Use crtc->state in intel_fbdev_init_bios,2018-10-04 11:46:01,v5.0-rc1
11/13 f56f6648404 ADDED!,drm/i915: Get rid of crtc->config dereference in intel_dp_retrain_link,2018-10-04 11:46:02,v5.0-rc1
12/13 958bb4528d1 ADDED!,drm/i915: Get rid of crtc->config in chv_data_lane_soft_reset,2018-10-04 11:46:03,v5.0-rc1
13/13 6f405638c2a ADDED!,"drm/i915: Get rid of intel_crtc->config in crtc_enable/disable functions, v2.",2018-10-04 11:46:04,v5.0-rc1
4/13 7efd90fb488 ADDED!,drm/i915: Use crtc_state in ironlake_enable_pch_transcoder,2018-10-04 11:45:55,v5.0-rc1
b2081525569,"drm/i915: Add plane alpha blending support, v2.",2018-08-15 12:34:05,v5.0-rc1
7569bf95310,drm/i915/csr: Added ICL Stepping info,2018-09-05 13:42:27,v5.0-rc1
4ca8ca9fe7d,drm/i915: Avoid compiler warning for maybe unused gu_misc_iir,2018-09-26 11:47:18,v5.0-rc1
35c37ade79c,drm/i915/icl: Define TA_TIMING_PARAM registers,2018-09-16 16:23:30,v5.0-rc1
33868a91c1d,drm/i915/icl: Define data/clock lanes dphy timing registers,2018-09-16 16:23:28,v5.0-rc1
7a90938332d,drm/i915: Avoid compiler warning for maybe unused gu_misc_iir,2018-09-26 11:47:18,v5.0-rc1
0a3c561da12,drm/i915: Enable RGB565 90/270 plane rotation for gen11 onwards.,2018-08-27 15:37:53,v5.0-rc1
70a7b83628f,drm/i915/icl: Program T_INIT_MASTER registers,2018-09-16 16:23:27,v5.0-rc1
ba3df888be9,drm/i915/icl: Enable DDI Buffer,2018-09-16 16:23:26,v5.0-rc1
3f4b9d9d02c,drm/i915/icl: DSI vswing programming sequence,2018-09-16 16:23:25,v5.0-rc1
fc41001d970,drm/i915/icl: Configure lane sequencing of combo phy transmitter,2018-09-16 16:23:24,v5.0-rc1
patches series of drm/i915: Preparations for adding gen11 planar formats.,,,
1/8 a1cccdcf330 ADDED!,drm/i915: Clean up casts to crtc_state in intel_atomic_commit_tail(),2018-09-20 12:27:04,v5.0-rc1
2/8 c249c5f6433 ADDED!,"drm/i915: Handle cursor updating active_planes correctly, v2.",2018-09-20 12:27:05,v5.0-rc1
3/8 62ef0dd3cc0,"drm/i915: Unconditionally clear plane visibility, v2.",2018-09-20 12:27:06,v5.0-rc1
4/8 f59e9701dbd,series,HASH(0x558b30e1bb98),v5.0-rc1
5/8 6c246b81f93 ADDED!,"drm/i915: Replace call to commit_planes_on_crtc with internal update, v2.",2018-09-20 12:27:08,v5.0-rc1
6/8 NOT-IN-UPSTREAM,drm/i915: Clean up scaler setup.,,
7/8 2a2777990a3 ADDED!,drm/i915: Move programming plane scaler to its own function.,2018-11-14 13:49:23,v5.0-rc1
8/8 945ac78928f ADDED!,"drm/i915: Force planar YUV coordinates to be a multiple of 2, v2.",2018-09-20 12:27:11,v5.0-rc1
9e3b5ce948f,drm/i915/psr: Enable AUX-A IO power well on ICL for PSR,2018-09-13 17:18:22,v5.0-rc1
4445930f1c4,firmware/dmc/icl: load v1.07 on icelake.,2018-08-27 17:38:44,v5.0-rc1
146cdf3fad9,drm/i915/icl: Define T_INIT_MASTER registers,2018-07-10 15:10:05,v5.0-rc1
b84d9ab0b72,drm/i915/guc: Update GuC power domain states,2018-09-10 10:41:49,v5.0-rc1
5f521722a2a,"drm/i915: Missed interrupt simulation is no more, tell the world",2018-09-07 12:28:51,v5.0-rc1
b212f0a470e,drm/i915/icl: Fix context RPCS programming,2018-09-03 12:30:07,v5.0-rc1
9f9d594d952,drm/i915: Fix ICL+ HDMI clock readout,2018-09-03 17:28:41,v5.0-rc1
a64f8887493,drm/i915/intel_csr.c Fix DMC FW Loading issue on ICL.,2018-08-31 02:00:23,v5.0-rc1
patches series of b45649fbd5b,,,
1/2 18563409b13 ADDED!,drm/i915: Clean up skl_plane_has_planar(),2018-08-27 15:56:24,v5.0-rc1
2/2 b45649fbd5b,drm/i915: Do not advertize support for NV12 on ICL yet.,2018-08-24 13:38:56,v5.0-rc1
39d1e234e1e,drm/i915/icl: implement the tc/legacy HPD {dis,}connect flows,2018-08-01 10:34:41,v5.0-rc1
a61d904fd6f,drm/i915: Simplify condition to keep DMC active during S0ix,2018-08-22 14:26:02,v5.0-rc1
7b19f544ed9,drm/i915/icl: Get DDI clock for ICL for MG PLL and TBT PLL,2018-08-17 14:52:09,v5.0-rc1
bcaad532974,drm/i915/icl: Implement HSDIV_RATIO of MG_CLKTOP2_HSCLKCTL_PORT reg as separate divider value defines,2018-08-17 14:52:08,v5.0-rc1
ee435831ec8,drm/i915/icl: account for context save/restore removed bits,2018-08-09 16:58:52,v5.0-rc1
patches series of drm/i915: Clean up power well descriptors,,,
01/10 ae9b06ca067,drm/i915/icl: Fix power well anonymous union initializers,2018-08-06 12:58:34,v5.0-rc1
02/10 48a287ed9d6 ADDED!,drm/i915: Rename intel_power_domains_fini() to intel_power_domains_fini_hw(),2018-08-06 12:58:35,v5.0-rc1
03/10 3ae27f7e103 ADDED!,drm/i915/vlv: Remove redundant power well ID asserts,2018-08-06 12:58:36,v5.0-rc1
04/10 f28ec6f4ea4 ADDED!,drm/i915: Constify power well descriptors,2018-08-06 12:58:37,v5.0-rc1
05/10 d13dd05a1f2 ADDED!,drm/i915/vlv: Use power well CTL IDX instead of ID,2018-08-06 12:58:38,v5.0-rc1
06/10 75e39688f35,drm/i915/ddi: Use power well CTL IDX instead of ID,2018-08-06 12:58:39,v5.0-rc1
07/10 4739a9d2438,drm/i915: Remove redundant power well IDs,2018-08-06 12:58:40,v5.0-rc1
08/10 2183b49933f ADDED!,drm/i915: Make power well ID names more uniform,2018-08-06 12:58:41,v5.0-rc1
09/10 d9fcdc8d1f8,drm/i915: Use existing power well IDs where possible,2018-08-06 12:58:42,v5.0-rc1
10/10 1a260e1117a,drm/i915/icl: Add missing power gate enums,2018-08-06 12:58:43,v5.0-rc1
497bfb70684,Revert "drm/i915/icl: WaEnableFloatBlendOptimization",2018-07-30 15:06:36,v5.0-rc1
08e3e21a24d,drm/i915: kill resource streamer support,2018-08-03 16:24:43,v5.0-rc1
48928d4b5d6,drm/i915/icl: move has_resource_streamer to GEN11_FEATURES,2018-07-19 10:05:56,v5.0-rc1
12a6c931bef,drm/i915/icl: avoid unclaimed PLANE_NV12_BUF_CFG register,2018-07-31 17:46:14,v5.0-rc1
c358514ba8d,Revert "drm/i915/icl: WaEnableFloatBlendOptimization",2018-07-30 15:06:36,v5.0-rc1
6f211ed4343,drm/i915/icl: Set TBT IO in Aux transaction,2018-07-26 16:35:15,v5.0-rc1
2b7edeb0085,drm/i915/icl: Add TBT checks for PLL calculations,2018-07-26 16:35:14,v5.0-rc1
c50dfe79ec3,drm/i915/icl: don't set CNL_DDI_CLOCK_REG_ACCESS_ON anymore,2018-07-25 17:12:29,v5.0-rc1
bc334d914ee,drm/i915/icl: toggle PHY clock gating around link training,2018-07-24 17:28:13,v5.0-rc1
340a44bef23,drm/i915/icl: program MG_DP_MODE,2018-07-24 17:28:12,v5.0-rc1
db7295c2c4e,drm/i915/icl: Update FIA supported lane count for hpd.,2018-07-24 17:28:11,v5.0-rc1
6075546f57f,drm/i915/icl: store the port type for TC ports,2018-07-24 17:28:10,v5.0-rc1
b9fcddab4af,drm/i915/icl: implement icl_digital_port_connected(),2018-07-25 12:59:27,v5.0-rc1
07685c827b2,drm/i915/icl: Implement voltage swing programming sequence for MG PHY DDI,2018-06-28 15:35:44,v5.0-rc1
a38bb309c2c,drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI,2018-07-13 12:43:13,v5.0-rc1
f7a738fca03,drm/i915/icl: compute the TBT PLL registers,2018-07-11 14:59:02,v5.0-rc1
7af2be6d54d,drm/i915/icl: Add VIDEO_DIP registers,2018-07-17 14:10:58,v5.0-rc1
patches series of 60a94324541,,,
1/3 9dd1a981a22 ADDED!,drm/i915/selftests: Include the start of each subtest in the GEM trace,2018-07-13 21:35:27,v5.0-rc1
2/3 9701975e851 ADDED!,drm/i915: Do not short-circuit tasklets during reset,2018-07-13 21:35:28,v5.0-rc1
3/3 60a94324541,drm/i915/execlists: Drop clear_gtiir() on GPU reset,2018-07-13 21:35:29,v5.0-rc1
185441e03aa,drm/i915: use the ICL stolen memory,2018-05-04 13:32:52,v5.0-rc1
d61d1b3bbba,drm/i915/icl: Define AUX lane registers for Port A/B,2018-07-05 19:19:38,v5.0-rc1
45f09f7adc8,drm/i915/icl: Power down unused DSI lanes,2018-07-05 19:19:37,v5.0-rc1
166869b390b,drm/i915/icl: Define PORT_CL_DW_10 register,2018-07-05 19:19:36,v5.0-rc1
b1cb21a5f1c,drm/i915/icl: Enable DSI IO power,2018-07-05 19:19:35,v5.0-rc1
21652f3b0d4,drm/i915/icl: Define DSI mode ctl register,2018-07-05 19:19:34,v5.0-rc1
fcfe0bdcb19,drm/i915/icl: Program DSI Escape clock Divider,2018-07-05 19:19:33,v5.0-rc1
patches series of e518634b436,,,
1/3 ca3589c1181,drm/i915/dsi: rename the current DSI files based on first platform,2018-07-05 16:25:07,v5.0-rc1
2/3 e518634b436,drm/i915/dsi: use vlv and bxt prefixes for the global DSI functions,2018-07-05 16:25:08,v5.0-rc1
3/3 012bf847d13 ADDED!,drm/i915/dsi: update some of the platform based checks,2018-07-05 16:25:09,v5.0-rc1
27efd2566cb,drm/i915/icl: Define register for DSI PLL,2018-07-05 18:31:48,v5.0-rc1
3160422251b,drm/i915/icp: Add Interrupt Support,2018-06-26 13:52:23,v5.0-rc1
67ca07e7ac1,drm/i915/icl: Add power well support,2018-06-26 17:22:32,v5.0-rc1
525280552b2,drm/i915/ddi: Get AUX power domain for DP main link too,2018-06-21 21:44:49,v5.0-rc1
e16a3750863,drm/i915: Enable hw workaround to bypass alpha,2018-06-21 20:43:56,v5.0-rc1
bd99ce085f1,drm/i915/icl: Do read-modify-write as needed during MG PLL programming,2018-06-19 19:41:15,v5.0-rc1
9fc59bae0f4,drm/i915/icl: Fix MG PLL setup when refclk is 38.4MHz,2018-06-15 17:39:10,v5.0-rc1
cd9e11a8bf2,drm/i915/icl: Add 10-bit support for hdmi,2018-05-21 17:25:51,v5.0-rc1
0fdb3f75a35,drm/i915/psr: Adds psrwake options for all platforms,2018-06-18 11:42:06,v5.0-rc1
b796b9710fd,drm/i915/icl: Handle hotplug interrupts for DP over TBT,2018-06-15 17:05:30,v5.0-rc1
121e758ee57,drm/i915/icl: Support for TC North Display interrupts,2018-06-15 17:05:29,v5.0-rc1
df0d28c185a,drm/i915/icl: GSE interrupt moves from DE_MISC to GU_MISC,2018-06-15 17:05:28,v5.0-rc1
patches series of f677bd558de,,,
25/24 af1f1b81130,drm/i915/icl: fix gmbus gpio pin mapping,2018-06-11 17:25:11,v5.0-rc1
26/24 46b527d19c4,drm/i915/icl: Add allowed DP rates for Icelake,2018-06-11 15:26:54,v5.0-rc1
27/24 2edd5327212 ADDED!,drm/i915/dp: Add support for HBR3 and TPS4 during link training,2018-06-11 15:26:55,v5.0-rc1
28/24 9378985eb05,drm/i915/icl: implement DVFS for ICL,2018-06-14 15:10:17,v5.0-rc1
29/24 bb187e93e48,drm/i915/icl: DP_AUX_E is valid on ICL+,2018-06-11 17:25:12,v5.0-rc1
30/24 f677bd558de,drm/i915/icl: update VBT's child_device_config flags2 field,2018-06-14 15:10:18,v5.0-rc1
1fa11ee2d9d,drm/i915/icl: start adding the TBT pll,2018-05-21 17:25:48,v5.0-rc1
00c92d929ac,drm/i915/icl: unconditionally init DDI for every port,2018-05-21 17:25:47,v5.0-rc1
970888e7d13,drm/i915/icl: add icelake_get_ddi_pll(),2018-05-21 17:25:44,v5.0-rc1
patches series of drm/i915/icl: Fix HDMI infoframe setting,,,
1/5 24a28179ecc ADDED!,drm/i915/ddi: s/crtc->config/old_crtc_state in haswell_crtc_disable(),2018-06-13 20:07:06,v5.0-rc1
2/5 afb2c4437da,drm/i915/ddi: Push pipe clock enabling to encoders,2018-06-13 20:27:46,v5.0-rc1
3/5 8fc0aa6eaa5 ADDED!,drm/i915/ddi: Check transcoder instead of port when setting HDMI infoframe,2018-06-13 20:07:08,v5.0-rc1
4/5 c737376442e,drm/i915/ddi: Set HDMI infoframes with pipe clocks enabled,2018-06-13 20:07:09,v5.0-rc1
5/5 3b567bb059b ADDED!,drm/i915/ddi: Removed unused var from hsw_write_infoframe(),2018-06-13 20:07:10,v5.0-rc1
dccc7228b5d,drm/i915/icl: Add DDI HDMI level selection for ICL,2018-05-21 17:25:41,v5.0-rc1
patches series of 2b9a820318e,,,
1/2 9904b1560e4 ADDED!,drm/i915/perf: use the lrc_desc to get the ctx hw id in gen8-10,2018-06-04 16:32:49,v5.0-rc1
2/2 2b9a820318e,drm/i915/perf: fix gen11 engine class shift,2018-06-04 16:32:50,v5.0-rc1
197af5f2131,drm/i915/icl: Don't update enabled dbuf slices struct until updated in hw,2018-05-17 18:56:26,v5.0-rc1
2f08b23d703,drm/i915/icl: fix icl_unmap/map_plls_to_ports,2018-05-25 08:52:38,v5.0-rc1
6ceb7277173,drm/i915/icl: Don't update enabled dbuf slices struct until updated in hw,2018-05-17 18:56:26,v5.0-rc1
patches series of drm/i915/perf: fix context filtering with GuC & ICL,,,
1/2 218b5000982 ADDED!,drm/i915: drop one bit on the hw_id when using guc,2018-06-02 12:29:45,v5.0-rc1
2/2 61d5676b556,drm/i915/perf: fix ctx_id read with GuC & ICL,2018-06-02 12:29:46,v5.0-rc1
5428bf5a9a9,drm/i915/icl: Calculate link clock using the new registers,2018-05-21 17:25:46,v5.0-rc1
51c83cfaf96,drm/i915/icl: Get DDI clock for ICL based on PLLs.,2018-05-23 15:44:44,v5.0-rc1
f17ca5010c3,drm/i915/icl: Add Icelake PCH detection,2018-05-21 17:25:43,v5.0-rc1
3937eb1a076,drm/i915/icl: Map VBT DDC Pin to BSpec DDC Pin,2018-05-21 17:25:42,v5.0-rc1
a2bc69a1a9d,drm/i915/icl: Add register definition for DFLEXDPMLE,2018-05-25 12:03:52,v5.0-rc1
ac213c1b45f,drm/i915/icl: introduce tc_port,2018-05-21 17:25:37,v5.0-rc1
9bb635d9e7d,drm/i915/icl: Extend AUX F interrupts to ICL,2018-05-21 17:25:35,v5.0-rc1
c46ef57d200,drm/i915/icl: fix icl_unmap/map_plls_to_ports,2018-05-25 08:52:38,v5.0-rc1
4ece66b149a,drm/i915/icl: Wa_1406463099,2018-05-25 15:05:39,v5.0-rc1
0bf059f3532,drm/i915/icl: WaEnableFloatBlendOptimization,2018-05-25 15:05:32,v5.0-rc1
b1f88820f4d,drm/i915/icl: Wa_2006665173,2018-05-25 15:05:31,v5.0-rc1
f63c7b4880a,drm/i915/icl: WaEnableStateCacheRedirectToCS,2018-05-25 15:05:30,v5.0-rc1
3c7ab278968,drm/i915/icl: WaDisableImprovedTdlClkGating,2018-05-25 15:05:29,v5.0-rc1
d78fa508f08,drm/i915/icl: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads,2018-05-18 15:40:32,v5.0-rc1
1e40d4aea57,drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads,2018-05-18 15:39:57,v5.0-rc1
c894d63c6b3,drm/i915/icl: Disable pipe CSC and gamma in cursor plane,2018-05-18 13:15:47,v5.0-rc1
c8af5274c3c,drm/i915: enable the pipe/transcoder/planes later on HSW+,2018-05-02 14:58:51,v5.0-rc1
6b7a6a7b4ba,drm/i915/icl: Read the correct Gen11 interrupt registers,2018-05-10 14:59:55,v5.0-rc1
73f4e8a338d,drm/i915/icl: WaForwardProgressSoftReset,2018-05-08 14:29:35,v5.0-rc1
5ba700c73a8,drm/i915/icl: Wa_1406838659,2018-05-08 14:29:34,v5.0-rc1
5215eef35fc,drm/i915/icl: Wa_1604302699,2018-05-08 14:29:33,v5.0-rc1
36204d80bac,drm/i915/icl: Wa_1406680159,2018-05-08 14:29:32,v5.0-rc1
0a437d49816,drm/i915/icl: Wa_1405779004,2018-05-08 14:29:31,v5.0-rc1
908ae051736,drm/i915/icl: WaDisCtxReload,2018-05-08 14:29:30,v5.0-rc1
6b967dc3920,drm/i915/icl: WaCL2SFHalfMaxAlloc,2018-05-08 14:29:29,v5.0-rc1
5246ae4bdb4,drm/i915/icl: WaDisableCleanEvicts,2018-05-08 14:29:28,v5.0-rc1
f4a357140a5,drm/i915/icl: WaModifyGamTlbPartitioning,2018-05-08 14:29:27,v5.0-rc1
d41bab68799,drm/i915/icl: WaL3BankAddressHashing,2018-05-08 14:29:26,v5.0-rc1
5bcebe76704,drm/i915/icl: WaGAPZPriorityScheme,2018-05-08 14:29:25,v5.0-rc1
d65dc3e40b8,drm/i915/icl: Enable Sampler DFR,2018-05-08 14:29:24,v5.0-rc1
cc38cae7c4e,drm/i915/icl: Introduce initial Icelake Workarounds,2018-05-08 14:29:23,v5.0-rc1
145ef0d17d5,drm/i915/icl: compute the MG PLL registers,2018-03-28 14:58:01,v5.0-rc1
bb82139b4bb,drm/i915/icl: compute the combo PHY (DPLL) DP registers,2018-03-28 14:58:00,v5.0-rc1
febafb93181,drm/i915/icl: compute the combo PHY (DPLL) HDMI registers,2018-03-28 14:57:59,v5.0-rc1
c27e917e2bd,drm/i915/icl: add basic support for the ICL clocks,2018-04-27 16:14:36,v5.0-rc1
74ba22ead59,drm/i915/icl: Add configuring MOCS in new Icelake engines,2018-05-02 15:31:42,v5.0-rc1
36cf89f53b0,drm/i915/icl: Fix the DP Max Voltage for ICL,2018-03-28 14:58:03,v5.0-rc1
fb5c8e9d435,drm/i915/icl: Implement voltage swing programming sequence for Combo PHY DDI,2018-03-28 14:58:02,v5.0-rc1
78b60ce7b96,drm/i915/icl: add definitions for the ICL PLL registers,2018-03-28 14:57:57,v5.0-rc1
37cde11ba72,drm/i915/icl: update ddb entry start/end mask during hw ddb readout,2018-04-26 19:55:17,v5.0-rc1
aa9664ffe86,drm/i915/icl: Enable 2nd DBuf slice only when needed,2018-04-26 19:55:16,v5.0-rc1
74bd8004e47,drm/i915/icl: track dbuf slice-2 status,2018-04-26 19:55:15,v5.0-rc1
077ef1f09c2,drm/i915/icl: Don't set pipe CSC/Gamma in PLANE_COLOR_CTL,2018-03-28 14:57:56,v5.0-rc1
ff047a87cfa,drm/i915/icl: Correctly clear lost ctx-switch interrupts across reset for Gen11,2018-04-24 14:39:55,v5.0-rc1
2b2874efe24,drm/i915/icl: Enable RC6 and RPS in Gen11,2018-04-05 17:00:52,v5.0-rc1
96606f3beb8,drm/i915/icl: Deal with GT INT DW correctly,2018-04-06 12:32:37,v5.0-rc1
d02b98b8e28,drm/i915/icl: Handle RPS interrupts correctly for Gen11,2018-04-05 17:00:50,v5.0-rc1
f744dbc2a64,"drm/i915/icl: Use hw engine class, instance to find irq handler",2018-04-06 12:31:45,v5.0-rc1
e34b0345e6a,drm/i915/icl: Add reset control register changes,2018-04-05 17:00:48,v5.0-rc1
1de401c08fa,drm/i915/perf: enable perf support on ICL,2018-03-26 14:39:48,v5.0-rc1
d775a7b1840,drm/i915/gen11: add support for reading the timestamp frequency,2018-01-09 21:28:35,v5.0-rc1
323301af974,drm/i915/icl: Added 5k source scaling support for Gen11 platform,2018-03-23 10:24:18,v5.0-rc1
96ae48311eb,drm/i915/icl: HPD pin for port F,2018-03-23 10:24:17,v5.0-rc1
cd96bea7ba9,drm/i915/icl: Add Voltage swing table for MG PHY DDI Buffer,2018-03-23 10:24:16,v5.0-rc1
c92f47b5ec9,drm/i915/icl: Add register defs for voltage swing sequences for MG PHY DDI,2018-03-23 10:24:15,v5.0-rc1
19b904f8df5,drm/i915/icl: Add Combo PHY DDI Buffer translation tables for Icelake.,2018-03-23 10:24:14,v5.0-rc1
5bb975de3f2,drm/i915/icl: Add register definitions for Combo PHY vswing sequences.,2018-03-23 10:24:13,v5.0-rc1
8b5eb5e2b5d,"drm/i915/icl: Added ICL 11 slice, subslice and EU fuse detection",2018-03-20 12:45:21,v5.0-rc1
d3d57927995,drm/i915/icl: Update subslice define for ICL 11,2018-03-16 14:14:51,v5.0-rc1
d53d5ffb9b9,drm/i915/icl: Enable the extra video decode and enhancement boxes for Icelake 11,2018-03-16 14:14:50,v5.0-rc1
26376a7e74d,drm/i915/icl: Check for fused-off VDBOX and VEBOX instances,2018-03-16 14:14:49,v5.0-rc1
84d4ebdb6c7,drm/i915/icl: do not save DDI A/E sharing bit for ICL,2018-03-06 12:41:55,v5.0-rc1
patches series of 210060edc21,,,
1/4 80b216b98b0 ADDED!,drm/i915: store all mmio bases in intel_engines,2018-03-14 11:26:50,v5.0-rc1
2/4 74419daaae6 ADDED!,drm/i915: add a selftest for the mmio_bases table,2018-03-14 11:26:51,v5.0-rc1
3/4 210060edc21,drm/i915: use engine->irq_keep_mask when resetting irqs,2018-03-14 11:26:52,v5.0-rc1
4/4 fa6f071d54f ADDED!,drm/i915: move gen8 irq shifts to intel_lrc.c,2018-03-14 11:26:53,v5.0-rc1
1e6aa7e55c2,drm/i915/icl: do not save DDI A/E sharing bit for ICL,2018-03-06 12:41:55,v5.0-rc1
a89a70a8b50,drm/i915/icl: Gen11 forcewake support,2018-03-02 18:15:01,v5.0-rc1
fd034c77b52,drm/i915/icl: Add Indirect Context Offset for Gen11,2018-03-02 18:15:00,v5.0-rc1
05f0addd9b1,drm/i915/icl: Enhanced execution list support,2018-03-02 18:14:59,v5.0-rc1
ac52da6af82,drm/i915/icl: new context descriptor support,2018-03-02 18:14:58,v5.0-rc1
5f79e7c6754,drm/i915/icl: Correctly initialize the Gen11 engines,2018-03-02 18:14:57,v5.0-rc1
d4ccceb0559,drm/i915/icl: Ringbuffer interrupt handling,2018-03-02 18:14:56,v5.0-rc1
3d2011cfa41,drm/i915/icl: remove port A/E lane sharing limitation.,2018-02-06 11:38:55,v5.0-rc1
51951ae7ed0,drm/i915/icl: Interrupt handling,2018-02-28 12:11:53,v5.0-rc1
022d3093a91,drm/i915/icl: Prepare for more rings,2018-02-28 12:11:52,v5.0-rc1
80d893501bb,drm/i915/icl: Show interrupt registers in debugfs,2018-02-20 17:37:53,v5.0-rc1
d55cb4fa2cf,drm/i915/icl: Add the ICL PCI IDs,2018-02-20 17:37:52,v5.0-rc1
patches series of 32ea06b67eb,,,
1/7 32ea06b67eb,drm/i915: Don't set cursor pipe select bits on g4x+,2018-01-30 22:38:01,v5.0-rc1
2/7 c154d1e0aab ADDED!,drm/i915: Set the primary plane pipe select bits on gen4,2018-01-30 22:38:02,v5.0-rc1
3/7 eade6c89449 ADDED!,drm/i915: Have plane->get_hw_state() return the current pipe,2018-01-30 22:38:03,v5.0-rc1
4/7 b99b9ec1d37 ADDED!,drm/i915: Clean up cursor defines,2018-01-31 16:37:09,v5.0-rc1
5/7 e876b78c5fb ADDED!,drm/i915: Disable trickle feed for SNB/IVB cursors,2018-01-30 22:38:05,v5.0-rc1
6/7 9171433100c ADDED!,drm/i915: Drop WaDoubleCursorLP3Latency:ivb,2018-01-30 22:38:06,v5.0-rc1
7/7 6380db61c54 ADDED!,drm/i915: s/plane/i9xx_plane/,2018-01-30 22:38:07,v5.0-rc1
c3cc39c539d,drm/i915/icl: program mbus during pipe enable,2018-02-05 15:21:31,v5.0-rc1
4cb4585e5a7,drm/i915/icl: initialize MBus during display init,2018-02-05 13:40:45,v5.0-rc1
746edf8f66e,drm/i915/icl: Enable both DBuf slices during init,2018-02-05 13:40:44,v5.0-rc1
ad186f3fd98,drm/i915/icl: implement the display init/uninit sequences,2018-02-05 13:40:43,v5.0-rc1
186a277e317,drm/i915/icl: add the main CDCLK functions,2018-02-06 17:33:46,v5.0-rc1
62d4a5e1495,drm/i915/icl: add ICL support to cnl_set_procmon_ref_values,2018-02-05 13:40:41,v5.0-rc1
31dade7df46,"drm/i915: Ignore minimum lines for level 0 in skl_compute_plane_wm, v2.",2018-02-05 11:58:41,v5.0-rc1
164daaf23c9,drm/i915/icl: allow the reg_read ioctl to read the RCS TIMESTAMP register,2018-01-30 11:49:18,v5.0-rc1
225701fc20e,drm/i915/icl: Set graphics mode register for gen11,2018-01-30 11:49:17,v5.0-rc1
b597277643f,drm/i915/icl: Handle expanded PLANE_CTL_FORMAT field,2018-01-30 11:49:16,v5.0-rc1
4357ce07e6b,drm/i915/gen11: fix the SAGV block time for gen11,2018-01-30 11:49:15,v5.0-rc1
7800549716f,drm/i915/icl: Introduce MBus related registers,2018-01-30 11:49:14,v5.0-rc1
234059da0f3,drm/i915/icl: NV12 y-plane ddb is not in same plane,2018-01-30 11:49:13,v5.0-rc1
5b695aff3af,drm/i915/icl: Fail flip if ddb allocated are less than min display buffer needed,2018-01-30 11:49:12,v5.0-rc1
df8ee19087d,drm/i915/icl: Do not fix dbuf block size to 512,2018-01-30 11:49:11,v5.0-rc1
9a9e3dfd6f8,drm/i915/icl: Don't allocate fixed bypass path blocks for ICL,2018-01-30 11:49:10,v5.0-rc1
517aaffe0c1,drm/i915/execlists: Inhibit context save/restore for the fake preempt context,2018-01-23 21:04:12,v5.0-rc1
b86aa4458ac,drm/i915/icl: Gen11 render context size,2018-01-11 14:55:07,v5.0-rc1
a6358dda29a,drm/i915/icl: Icelake interrupt register addresses and bits,2018-01-09 21:23:13,v5.0-rc1
patches series of ICP initial support,,,
1/8 841b5ed7aae ADDED!,drm/i915/cnl: Add Port F definition.,2018-01-11 16:00:03,v5.0-rc1
2/8 412310019a2,drm/i915/icl: Add initial Icelake definitions.,2018-01-11 16:00:04,v5.0-rc1
3/8 0b58436f2d9,drm/i915/icp: Introduce Ice Lake PCH,2018-01-11 16:00:05,v5.0-rc1
4/8 4ef99abd07e,drm/i915/icp: Get/set proper Raw clock frequency on ICP,2018-01-11 16:00:06,v5.0-rc1
5/8 b0d6a0f27e2,drm/i915/icp: Add Panel Power Sequencing Support,2018-01-11 16:00:07,v5.0-rc1
6/8 ccf6e0d9774,drm/i915/icp: Add backlight Support for ICP,2018-01-19 16:48:12,v5.0-rc1
7/8 5c749c522fa,drm/i915/icp: add ICP gmbus and gpio support,2018-01-11 16:00:09,v5.0-rc1
8/8 5c8ea01830b,drm/i915/icp: Add the ID for ICL PCH - ICP,2018-01-11 16:00:10,v5.0-rc1