| 2018-10-09 14:49:31 |
Manoj Iyer |
description |
[IMPACT]
=======
The ARM architecture defines several events as part of the Performance Monitor Unit (PMU)
Extension. In addition, Cavium has added "implementation defined" pmu core events, which Cavium deems most useful for analyzing performance. Currently perf does not list these "implementation defined" events.
[FIX]
====
b9b77222d4ff perf vendor events arm64: Update ThunderX2 implementation defined pmu core events
[TEST]
====
With the patch applied perf lists the additional PMU events.
ubuntu@starbuck:~$ perf list
List of pre-defined events (to be used in -e):
armv8_pmuv3_0/br_immed_retired/ [Kernel PMU event]
armv8_pmuv3_0/br_mis_pred/ [Kernel PMU event]
armv8_pmuv3_0/br_mis_pred_retired/ [Kernel PMU event]
armv8_pmuv3_0/br_pred/ [Kernel PMU event]
armv8_pmuv3_0/br_retired/ [Kernel PMU event]
armv8_pmuv3_0/br_return_retired/ [Kernel PMU event]
armv8_pmuv3_0/bus_access/ [Kernel PMU event]
armv8_pmuv3_0/bus_cycles/ [Kernel PMU event]
armv8_pmuv3_0/cid_write_retired/ [Kernel PMU event]
armv8_pmuv3_0/cpu_cycles/ [Kernel PMU event]
armv8_pmuv3_0/exc_return/ [Kernel PMU event]
armv8_pmuv3_0/exc_taken/ [Kernel PMU event]
armv8_pmuv3_0/inst_retired/ [Kernel PMU event]
armv8_pmuv3_0/inst_spec/ [Kernel PMU event]
armv8_pmuv3_0/l1d_cache/ [Kernel PMU event]
armv8_pmuv3_0/l1d_cache_allocate/ [Kernel PMU event]
armv8_pmuv3_0/l1d_cache_refill/ [Kernel PMU event]
armv8_pmuv3_0/l1d_cache_wb/ [Kernel PMU event]
armv8_pmuv3_0/l1d_tlb/ [Kernel PMU event]
armv8_pmuv3_0/l1d_tlb_refill/ [Kernel PMU event]
armv8_pmuv3_0/l1i_cache/ [Kernel PMU event]
armv8_pmuv3_0/l1i_cache_refill/ [Kernel PMU event]
armv8_pmuv3_0/l1i_tlb/ [Kernel PMU event]
armv8_pmuv3_0/l1i_tlb_refill/ [Kernel PMU event]
armv8_pmuv3_0/l2d_cache/ [Kernel PMU event]
armv8_pmuv3_0/l2d_cache_allocate/ [Kernel PMU event]
armv8_pmuv3_0/l2d_cache_refill/ [Kernel PMU event]
armv8_pmuv3_0/l2d_cache_wb/ [Kernel PMU event]
armv8_pmuv3_0/l2d_tlb/ [Kernel PMU event]
armv8_pmuv3_0/l2d_tlb_refill/ [Kernel PMU event]
armv8_pmuv3_0/ld_retired/ [Kernel PMU event]
armv8_pmuv3_0/mem_access/ [Kernel PMU event]
armv8_pmuv3_0/st_retired/ [Kernel PMU event]
armv8_pmuv3_0/stall_backend/ [Kernel PMU event]
armv8_pmuv3_0/stall_frontend/ [Kernel PMU event]
armv8_pmuv3_0/sw_incr/ [Kernel PMU event]
armv8_pmuv3_0/ttbr_write_retired/ [Kernel PMU event]
armv8_pmuv3_0/unaligned_ldst_retired/ [Kernel PMU event]
core imp def:
bus_access_rd
[Bus access read]
bus_access_wr
[Bus access write]
exc_dabort
[Exception taken, Data Abort and SError]
exc_fiq
[Exception taken, FIQ]
exc_hvc
[Exception taken, Hypervisor Call]
exc_irq
[Exception taken, IRQ]
exc_pabort
[Exception taken, Instruction Abort]
exc_smc
[Exception taken, Secure Monitor Call]
exc_svc
[Exception taken, Supervisor Call]
exc_trap_dabort
[Exception taken, Data Abort or SError not taken locally]
exc_trap_fiq
[Exception taken, FIQ not taken locally]
exc_trap_irq
[Exception taken, IRQ not taken locally]
exc_trap_other
[Exception taken, Other traps not taken locally]
exc_trap_pabort
[Exception taken, Instruction Abort not taken locally]
exc_undef
[Exception taken, Other synchronous]
l1d_cache_inval
[L1D cache invalidate]
l1d_cache_rd
[L1D cache access, read]
l1d_cache_refill_inner
[L1D cache refill, inner]
l1d_cache_refill_outer
[L1D cache refill, outer]
l1d_cache_refill_rd
[L1D cache refill, read]
l1d_cache_refill_wr
[L1D cache refill, write]
l1d_cache_wb_clean
[L1D cache Write-Back, cleaning and coherency]
l1d_cache_wb_victim
[L1D cache Write-Back, victim]
l1d_cache_wr
[L1D cache access, write]
l1d_tlb_rd
[L1D tlb access, read]
l1d_tlb_refill_rd
[L1D tlb refill, read]
l1d_tlb_refill_wr
[L1D tlb refill, write]
l1d_tlb_wr
[L1D tlb access, write]
l2d_tlb_rd
[L2D cache access, read]
l2d_tlb_refill_rd
[L2D cache refill, read]
l2d_tlb_refill_wr
[L2D cache refill, write]
l2d_tlb_wr
[L2D cache access, write]
mem_access_rd
[Data memory access, read]
mem_access_wr
[Data memory access, write]
unaligned_ld_spec
[Unaligned access, read]
unaligned_ldst_spec
[Unaligned access]
unaligned_st_spec
[Unaligned access, write]
rNNN [Raw hardware event descrip
cpu/t1=v1[,t2=v2,t3 ...]/modifier [Raw hardware event descrip
(see 'man perf-list' on how to encode it)
mem:<addr>[/len][:access] [Hardware breakpoint]
ubuntu@starbuck:~$
[REGRESSION POTENTIAL]
======================
The patch is limited to ARM64, ThunderX2 PMU core definitions json file. No regression potential for any kernel subsystems. |
[IMPACT]
=======
The ARM architecture defines several events as part of the Performance Monitor Unit (PMU) Extension. In addition, Cavium has added "implementation defined" pmu core events, which Cavium deems most useful for analyzing performance. Currently perf does not list these "implementation defined" events.
[FIX]
====
b9b77222d4ff perf vendor events arm64: Update ThunderX2 implementation defined pmu core events
[TEST]
====
With the patch applied perf lists the additional PMU events.
ubuntu@starbuck:~$ perf list
List of pre-defined events (to be used in -e):
armv8_pmuv3_0/br_immed_retired/ [Kernel PMU event]
armv8_pmuv3_0/br_mis_pred/ [Kernel PMU event]
armv8_pmuv3_0/br_mis_pred_retired/ [Kernel PMU event]
armv8_pmuv3_0/br_pred/ [Kernel PMU event]
armv8_pmuv3_0/br_retired/ [Kernel PMU event]
armv8_pmuv3_0/br_return_retired/ [Kernel PMU event]
armv8_pmuv3_0/bus_access/ [Kernel PMU event]
armv8_pmuv3_0/bus_cycles/ [Kernel PMU event]
armv8_pmuv3_0/cid_write_retired/ [Kernel PMU event]
armv8_pmuv3_0/cpu_cycles/ [Kernel PMU event]
armv8_pmuv3_0/exc_return/ [Kernel PMU event]
armv8_pmuv3_0/exc_taken/ [Kernel PMU event]
armv8_pmuv3_0/inst_retired/ [Kernel PMU event]
armv8_pmuv3_0/inst_spec/ [Kernel PMU event]
armv8_pmuv3_0/l1d_cache/ [Kernel PMU event]
armv8_pmuv3_0/l1d_cache_allocate/ [Kernel PMU event]
armv8_pmuv3_0/l1d_cache_refill/ [Kernel PMU event]
armv8_pmuv3_0/l1d_cache_wb/ [Kernel PMU event]
armv8_pmuv3_0/l1d_tlb/ [Kernel PMU event]
armv8_pmuv3_0/l1d_tlb_refill/ [Kernel PMU event]
armv8_pmuv3_0/l1i_cache/ [Kernel PMU event]
armv8_pmuv3_0/l1i_cache_refill/ [Kernel PMU event]
armv8_pmuv3_0/l1i_tlb/ [Kernel PMU event]
armv8_pmuv3_0/l1i_tlb_refill/ [Kernel PMU event]
armv8_pmuv3_0/l2d_cache/ [Kernel PMU event]
armv8_pmuv3_0/l2d_cache_allocate/ [Kernel PMU event]
armv8_pmuv3_0/l2d_cache_refill/ [Kernel PMU event]
armv8_pmuv3_0/l2d_cache_wb/ [Kernel PMU event]
armv8_pmuv3_0/l2d_tlb/ [Kernel PMU event]
armv8_pmuv3_0/l2d_tlb_refill/ [Kernel PMU event]
armv8_pmuv3_0/ld_retired/ [Kernel PMU event]
armv8_pmuv3_0/mem_access/ [Kernel PMU event]
armv8_pmuv3_0/st_retired/ [Kernel PMU event]
armv8_pmuv3_0/stall_backend/ [Kernel PMU event]
armv8_pmuv3_0/stall_frontend/ [Kernel PMU event]
armv8_pmuv3_0/sw_incr/ [Kernel PMU event]
armv8_pmuv3_0/ttbr_write_retired/ [Kernel PMU event]
armv8_pmuv3_0/unaligned_ldst_retired/ [Kernel PMU event]
core imp def:
bus_access_rd
[Bus access read]
bus_access_wr
[Bus access write]
exc_dabort
[Exception taken, Data Abort and SError]
exc_fiq
[Exception taken, FIQ]
exc_hvc
[Exception taken, Hypervisor Call]
exc_irq
[Exception taken, IRQ]
exc_pabort
[Exception taken, Instruction Abort]
exc_smc
[Exception taken, Secure Monitor Call]
exc_svc
[Exception taken, Supervisor Call]
exc_trap_dabort
[Exception taken, Data Abort or SError not taken locally]
exc_trap_fiq
[Exception taken, FIQ not taken locally]
exc_trap_irq
[Exception taken, IRQ not taken locally]
exc_trap_other
[Exception taken, Other traps not taken locally]
exc_trap_pabort
[Exception taken, Instruction Abort not taken locally]
exc_undef
[Exception taken, Other synchronous]
l1d_cache_inval
[L1D cache invalidate]
l1d_cache_rd
[L1D cache access, read]
l1d_cache_refill_inner
[L1D cache refill, inner]
l1d_cache_refill_outer
[L1D cache refill, outer]
l1d_cache_refill_rd
[L1D cache refill, read]
l1d_cache_refill_wr
[L1D cache refill, write]
l1d_cache_wb_clean
[L1D cache Write-Back, cleaning and coherency]
l1d_cache_wb_victim
[L1D cache Write-Back, victim]
l1d_cache_wr
[L1D cache access, write]
l1d_tlb_rd
[L1D tlb access, read]
l1d_tlb_refill_rd
[L1D tlb refill, read]
l1d_tlb_refill_wr
[L1D tlb refill, write]
l1d_tlb_wr
[L1D tlb access, write]
l2d_tlb_rd
[L2D cache access, read]
l2d_tlb_refill_rd
[L2D cache refill, read]
l2d_tlb_refill_wr
[L2D cache refill, write]
l2d_tlb_wr
[L2D cache access, write]
mem_access_rd
[Data memory access, read]
mem_access_wr
[Data memory access, write]
unaligned_ld_spec
[Unaligned access, read]
unaligned_ldst_spec
[Unaligned access]
unaligned_st_spec
[Unaligned access, write]
rNNN [Raw hardware event descrip
cpu/t1=v1[,t2=v2,t3 ...]/modifier [Raw hardware event descrip
(see 'man perf-list' on how to encode it)
mem:<addr>[/len][:access] [Hardware breakpoint]
ubuntu@starbuck:~$
[REGRESSION POTENTIAL]
======================
The patch is limited to ARM64, ThunderX2 PMU core definitions json file. No regression potential for any kernel subsystems. |
|
