| 2017-10-04 18:22:22 |
dann frazier |
bug |
|
|
added bug |
| 2017-10-04 18:22:33 |
dann frazier |
nominated for series |
|
Ubuntu Zesty |
|
| 2017-10-04 18:22:33 |
dann frazier |
bug task added |
|
linux (Ubuntu Zesty) |
|
| 2017-10-04 18:22:53 |
dann frazier |
linux (Ubuntu Zesty): status |
New |
Confirmed |
|
| 2017-10-04 18:22:59 |
dann frazier |
linux (Ubuntu Zesty): assignee |
|
dann frazier (dannf) |
|
| 2017-11-03 16:50:16 |
dann frazier |
description |
[Impact]
A ~12% performance gain can be achieved with the iperf benchmark by allowing the ixgbe driver to take advantage of PCIe Relaxed Ordering, as observed on the HiSilicon D05 system.
[Test Case]
iperf command TBD
[Regression Risk]
The patchset is careful to only enable Relaxed Ordering if advertised up through the root port. However, it is possible that enabling RO on hardware that supports it could actually regress performance, or that there is hw out there that advertises RO, but has bugs in the implementation. The patch series includes quirks for HW where RO is advertised but known to have issues[*] - but this list maybe incomplete. This would only impact devices w/ drivers that take advantage of RO - currently cxgb4 and (not yet upstream) ixgbe.
Also, there is a possibility of a crash caused by a coding error. One such issue has already been found and fixed upstream [**], and is part of this series.
The risk of both of these regressions is reduced by the fact that this code is now in an upstream release (v4.13) and has therefore gotten a lot more testing that has not resulted in regressions reports.
[*]
commit 077fa19c5dfa06a6ae04fb1661680940ff837612
Author: dingtianhong <dingtianhong@huawei.com>
Date: Tue Aug 15 11:23:25 2017 +0800
PCI: Disable Relaxed Ordering Attributes for AMD A110
commit 87e09cdec4dae08acdb4aa49beb793c19d73e73e
Author: dingtianhong <dingtianhong@huawei.com>
Date: Tue Aug 15 11:23:24 2017 +0800
PCI: Disable Relaxed Ordering for some Intel processors
[**]
commit 0e405232871d67bf1b238d56b6b3d500e69ebbf3
Author: dingtianhong <dingtianhong@huawei.com>
Date: Tue Aug 15 23:24:48 2017 +0800
PCI: fix oops when try to find Root Port for a PCI device |
[Impact]
A signficant performance gain can be achieved with the iperf benchmark by allowing the ixgbe driver to take advantage of PCIe Relaxed Ordering, as observed on the HiSilicon D05 system.
[Test Case]
= server =
taskset -c 0-15 iperf -s -B 192.168.80.11
taskset -c 16-31 iperf -s -B 192.168.90.11
= client =
taskset -c 0-15 iperf -c 192.168.80.11 -i 3 -t 600 -P 8 &
taskset -c 16-31 iperf -c 192.168.90.11 -i 3 -t 600 -P 8 &
Without these patches, we observe an aggregate performance of 8.54 Gbit/sec. With these patches, we observe an aggregate performance of 18.82 Gbit/sec.
[Regression Risk]
The following risk assessment applies to both artful and zesty - but note that the bulk of these changes are *already in artful*. The proposed SRU for artful would just allow an additional driver to take advantage of it. For zesty, an SRU would need to both introduce this feature and enable it for both the cxgb4 and ixgbe drivers.
The patchset is careful to only enable Relaxed Ordering if advertised up through the root port. However, it is possible that enabling RO on hardware that supports it could actually regress performance, or that there is hw out there that advertises RO, but has bugs in the implementation. The patch series includes quirks for HW where RO is advertised but known to have issues[*] - but this list maybe incomplete. This would only impact devices w/ drivers that take advantage of RO - currently cxgb4 and (not yet upstream) ixgbe.
Also, there is a possibility of a crash caused by a coding error. One such issue has already been found and fixed upstream [**], and is part of this series.
The risk of both of these regressions is reduced by the fact that this code is now in an upstream release (v4.13) and has therefore gotten a lot more testing that has not resulted in regressions reports.
[*]
commit 077fa19c5dfa06a6ae04fb1661680940ff837612
Author: dingtianhong <dingtianhong@huawei.com>
Date: Tue Aug 15 11:23:25 2017 +0800
PCI: Disable Relaxed Ordering Attributes for AMD A110
commit 87e09cdec4dae08acdb4aa49beb793c19d73e73e
Author: dingtianhong <dingtianhong@huawei.com>
Date: Tue Aug 15 11:23:24 2017 +0800
PCI: Disable Relaxed Ordering for some Intel processors
[**]
commit 0e405232871d67bf1b238d56b6b3d500e69ebbf3
Author: dingtianhong <dingtianhong@huawei.com>
Date: Tue Aug 15 23:24:48 2017 +0800
PCI: fix oops when try to find Root Port for a PCI device |
|
| 2017-11-03 16:58:50 |
dann frazier |
nominated for series |
|
Ubuntu Artful |
|
| 2017-11-03 16:58:50 |
dann frazier |
bug task added |
|
linux (Ubuntu Artful) |
|
| 2017-11-03 16:58:58 |
dann frazier |
linux (Ubuntu): status |
Fix Released |
Confirmed |
|
| 2017-11-03 16:59:12 |
dann frazier |
summary |
PCIe: Allow drivers to use Relaxed Ordering on capable root ports |
ixgbe/PCIe: Allow drivers to use Relaxed Ordering on capable root ports |
|
| 2017-11-03 16:59:17 |
dann frazier |
linux (Ubuntu): status |
Confirmed |
In Progress |
|
| 2017-11-03 16:59:25 |
dann frazier |
linux (Ubuntu Artful): status |
New |
In Progress |
|
| 2017-11-03 16:59:28 |
dann frazier |
linux (Ubuntu Artful): assignee |
|
dann frazier (dannf) |
|
| 2017-11-03 16:59:33 |
dann frazier |
linux (Ubuntu): assignee |
|
dann frazier (dannf) |
|
| 2017-11-03 16:59:54 |
dann frazier |
linux (Ubuntu Zesty): importance |
Undecided |
Medium |
|
| 2017-11-03 16:59:57 |
dann frazier |
linux (Ubuntu Artful): importance |
Undecided |
Medium |
|
| 2017-11-03 17:02:13 |
dann frazier |
description |
[Impact]
A signficant performance gain can be achieved with the iperf benchmark by allowing the ixgbe driver to take advantage of PCIe Relaxed Ordering, as observed on the HiSilicon D05 system.
[Test Case]
= server =
taskset -c 0-15 iperf -s -B 192.168.80.11
taskset -c 16-31 iperf -s -B 192.168.90.11
= client =
taskset -c 0-15 iperf -c 192.168.80.11 -i 3 -t 600 -P 8 &
taskset -c 16-31 iperf -c 192.168.90.11 -i 3 -t 600 -P 8 &
Without these patches, we observe an aggregate performance of 8.54 Gbit/sec. With these patches, we observe an aggregate performance of 18.82 Gbit/sec.
[Regression Risk]
The following risk assessment applies to both artful and zesty - but note that the bulk of these changes are *already in artful*. The proposed SRU for artful would just allow an additional driver to take advantage of it. For zesty, an SRU would need to both introduce this feature and enable it for both the cxgb4 and ixgbe drivers.
The patchset is careful to only enable Relaxed Ordering if advertised up through the root port. However, it is possible that enabling RO on hardware that supports it could actually regress performance, or that there is hw out there that advertises RO, but has bugs in the implementation. The patch series includes quirks for HW where RO is advertised but known to have issues[*] - but this list maybe incomplete. This would only impact devices w/ drivers that take advantage of RO - currently cxgb4 and (not yet upstream) ixgbe.
Also, there is a possibility of a crash caused by a coding error. One such issue has already been found and fixed upstream [**], and is part of this series.
The risk of both of these regressions is reduced by the fact that this code is now in an upstream release (v4.13) and has therefore gotten a lot more testing that has not resulted in regressions reports.
[*]
commit 077fa19c5dfa06a6ae04fb1661680940ff837612
Author: dingtianhong <dingtianhong@huawei.com>
Date: Tue Aug 15 11:23:25 2017 +0800
PCI: Disable Relaxed Ordering Attributes for AMD A110
commit 87e09cdec4dae08acdb4aa49beb793c19d73e73e
Author: dingtianhong <dingtianhong@huawei.com>
Date: Tue Aug 15 11:23:24 2017 +0800
PCI: Disable Relaxed Ordering for some Intel processors
[**]
commit 0e405232871d67bf1b238d56b6b3d500e69ebbf3
Author: dingtianhong <dingtianhong@huawei.com>
Date: Tue Aug 15 23:24:48 2017 +0800
PCI: fix oops when try to find Root Port for a PCI device |
[Impact]
A signficant performance gain can be achieved with the iperf benchmark by allowing the ixgbe driver to take advantage of PCIe Relaxed Ordering, as observed on the HiSilicon D05 system.
[Test Case]
= server =
taskset -c 0-15 iperf -s -B 192.168.80.11
taskset -c 16-31 iperf -s -B 192.168.90.11
= client =
taskset -c 0-15 iperf -c 192.168.80.11 -i 3 -t 600 -P 8 &
taskset -c 16-31 iperf -c 192.168.90.11 -i 3 -t 600 -P 8 &
Without these patches, we observe an aggregate performance of 8.54 Gbit/sec. With these patches, we observe an aggregate performance of 18.82 Gbit/sec.
[Regression Risk]
The following risk assessment applies to both artful and zesty - but note that the bulk of these changes are *already in artful*. The proposed SRU for artful would just allow an additional driver to take advantage of it. For zesty, an SRU would need to both introduce this feature and enable it for both the cxgb4 and ixgbe drivers.
The patchset is careful to only enable Relaxed Ordering if advertised up through the root port. However, it is possible that enabling RO on hardware that supports it could actually regress performance, or that there is hw out there that advertises RO, but has bugs in the implementation. The patch series includes quirks for HW where RO is advertised but known to have issues[*] - but this list maybe incomplete. This would only impact devices w/ drivers that take advantage of RO - currently cxgb4 and (not yet upstream) ixgbe.
Also, there is a possibility of a crash caused by a coding error. One such issue has already been found and fixed upstream [**], and is part of this series.
The risk of both of these regressions is reduced by the fact that this code is upstream, and has therefore gotten a lot more testing that has not resulted in regressions reports.
[*]
commit 077fa19c5dfa06a6ae04fb1661680940ff837612
Author: dingtianhong <dingtianhong@huawei.com>
Date: Tue Aug 15 11:23:25 2017 +0800
PCI: Disable Relaxed Ordering Attributes for AMD A110
commit 87e09cdec4dae08acdb4aa49beb793c19d73e73e
Author: dingtianhong <dingtianhong@huawei.com>
Date: Tue Aug 15 11:23:24 2017 +0800
PCI: Disable Relaxed Ordering for some Intel processors
[**]
commit 0e405232871d67bf1b238d56b6b3d500e69ebbf3
Author: dingtianhong <dingtianhong@huawei.com>
Date: Tue Aug 15 23:24:48 2017 +0800
PCI: fix oops when try to find Root Port for a PCI device |
|
| 2017-11-03 17:02:52 |
dann frazier |
description |
[Impact]
A signficant performance gain can be achieved with the iperf benchmark by allowing the ixgbe driver to take advantage of PCIe Relaxed Ordering, as observed on the HiSilicon D05 system.
[Test Case]
= server =
taskset -c 0-15 iperf -s -B 192.168.80.11
taskset -c 16-31 iperf -s -B 192.168.90.11
= client =
taskset -c 0-15 iperf -c 192.168.80.11 -i 3 -t 600 -P 8 &
taskset -c 16-31 iperf -c 192.168.90.11 -i 3 -t 600 -P 8 &
Without these patches, we observe an aggregate performance of 8.54 Gbit/sec. With these patches, we observe an aggregate performance of 18.82 Gbit/sec.
[Regression Risk]
The following risk assessment applies to both artful and zesty - but note that the bulk of these changes are *already in artful*. The proposed SRU for artful would just allow an additional driver to take advantage of it. For zesty, an SRU would need to both introduce this feature and enable it for both the cxgb4 and ixgbe drivers.
The patchset is careful to only enable Relaxed Ordering if advertised up through the root port. However, it is possible that enabling RO on hardware that supports it could actually regress performance, or that there is hw out there that advertises RO, but has bugs in the implementation. The patch series includes quirks for HW where RO is advertised but known to have issues[*] - but this list maybe incomplete. This would only impact devices w/ drivers that take advantage of RO - currently cxgb4 and (not yet upstream) ixgbe.
Also, there is a possibility of a crash caused by a coding error. One such issue has already been found and fixed upstream [**], and is part of this series.
The risk of both of these regressions is reduced by the fact that this code is upstream, and has therefore gotten a lot more testing that has not resulted in regressions reports.
[*]
commit 077fa19c5dfa06a6ae04fb1661680940ff837612
Author: dingtianhong <dingtianhong@huawei.com>
Date: Tue Aug 15 11:23:25 2017 +0800
PCI: Disable Relaxed Ordering Attributes for AMD A110
commit 87e09cdec4dae08acdb4aa49beb793c19d73e73e
Author: dingtianhong <dingtianhong@huawei.com>
Date: Tue Aug 15 11:23:24 2017 +0800
PCI: Disable Relaxed Ordering for some Intel processors
[**]
commit 0e405232871d67bf1b238d56b6b3d500e69ebbf3
Author: dingtianhong <dingtianhong@huawei.com>
Date: Tue Aug 15 23:24:48 2017 +0800
PCI: fix oops when try to find Root Port for a PCI device |
[Impact]
A signficant performance gain can be achieved with the iperf benchmark by allowing the ixgbe driver to take advantage of PCIe Relaxed Ordering, as observed on the HiSilicon D05 system.
[Test Case]
Setup two servers with dual ixgbe 10G ports, wired back-to-back.
= server =
taskset -c 0-15 iperf -s -B 192.168.80.11
taskset -c 16-31 iperf -s -B 192.168.90.11
= client =
taskset -c 0-15 iperf -c 192.168.80.11 -i 3 -t 600 -P 8 &
taskset -c 16-31 iperf -c 192.168.90.11 -i 3 -t 600 -P 8 &
Without these patches, we observe an aggregate performance of 8.54 Gbit/sec. With these patches, we observe an aggregate performance of 18.82 Gbit/sec.
[Regression Risk]
The following risk assessment applies to both artful and zesty - but note that the bulk of these changes are *already in artful*. The proposed SRU for artful would just allow an additional driver to take advantage of it. For zesty, an SRU would need to both introduce this feature and enable it for both the cxgb4 and ixgbe drivers.
The patchset is careful to only enable Relaxed Ordering if advertised up through the root port. However, it is possible that enabling RO on hardware that supports it could actually regress performance, or that there is hw out there that advertises RO, but has bugs in the implementation. The patch series includes quirks for HW where RO is advertised but known to have issues[*] - but this list maybe incomplete. This would only impact devices w/ drivers that take advantage of RO - currently cxgb4 and (not yet upstream) ixgbe.
Also, there is a possibility of a crash caused by a coding error. One such issue has already been found and fixed upstream [**], and is part of this series.
The risk of both of these regressions is reduced by the fact that this code is upstream, and has therefore gotten a lot more testing that has not resulted in regressions reports.
[*]
commit 077fa19c5dfa06a6ae04fb1661680940ff837612
Author: dingtianhong <dingtianhong@huawei.com>
Date: Tue Aug 15 11:23:25 2017 +0800
PCI: Disable Relaxed Ordering Attributes for AMD A110
commit 87e09cdec4dae08acdb4aa49beb793c19d73e73e
Author: dingtianhong <dingtianhong@huawei.com>
Date: Tue Aug 15 11:23:24 2017 +0800
PCI: Disable Relaxed Ordering for some Intel processors
[**]
commit 0e405232871d67bf1b238d56b6b3d500e69ebbf3
Author: dingtianhong <dingtianhong@huawei.com>
Date: Tue Aug 15 23:24:48 2017 +0800
PCI: fix oops when try to find Root Port for a PCI device |
|
| 2017-11-03 17:04:35 |
dann frazier |
description |
[Impact]
A signficant performance gain can be achieved with the iperf benchmark by allowing the ixgbe driver to take advantage of PCIe Relaxed Ordering, as observed on the HiSilicon D05 system.
[Test Case]
Setup two servers with dual ixgbe 10G ports, wired back-to-back.
= server =
taskset -c 0-15 iperf -s -B 192.168.80.11
taskset -c 16-31 iperf -s -B 192.168.90.11
= client =
taskset -c 0-15 iperf -c 192.168.80.11 -i 3 -t 600 -P 8 &
taskset -c 16-31 iperf -c 192.168.90.11 -i 3 -t 600 -P 8 &
Without these patches, we observe an aggregate performance of 8.54 Gbit/sec. With these patches, we observe an aggregate performance of 18.82 Gbit/sec.
[Regression Risk]
The following risk assessment applies to both artful and zesty - but note that the bulk of these changes are *already in artful*. The proposed SRU for artful would just allow an additional driver to take advantage of it. For zesty, an SRU would need to both introduce this feature and enable it for both the cxgb4 and ixgbe drivers.
The patchset is careful to only enable Relaxed Ordering if advertised up through the root port. However, it is possible that enabling RO on hardware that supports it could actually regress performance, or that there is hw out there that advertises RO, but has bugs in the implementation. The patch series includes quirks for HW where RO is advertised but known to have issues[*] - but this list maybe incomplete. This would only impact devices w/ drivers that take advantage of RO - currently cxgb4 and (not yet upstream) ixgbe.
Also, there is a possibility of a crash caused by a coding error. One such issue has already been found and fixed upstream [**], and is part of this series.
The risk of both of these regressions is reduced by the fact that this code is upstream, and has therefore gotten a lot more testing that has not resulted in regressions reports.
[*]
commit 077fa19c5dfa06a6ae04fb1661680940ff837612
Author: dingtianhong <dingtianhong@huawei.com>
Date: Tue Aug 15 11:23:25 2017 +0800
PCI: Disable Relaxed Ordering Attributes for AMD A110
commit 87e09cdec4dae08acdb4aa49beb793c19d73e73e
Author: dingtianhong <dingtianhong@huawei.com>
Date: Tue Aug 15 11:23:24 2017 +0800
PCI: Disable Relaxed Ordering for some Intel processors
[**]
commit 0e405232871d67bf1b238d56b6b3d500e69ebbf3
Author: dingtianhong <dingtianhong@huawei.com>
Date: Tue Aug 15 23:24:48 2017 +0800
PCI: fix oops when try to find Root Port for a PCI device |
[Impact]
A signficant performance gain can be achieved with the iperf benchmark by allowing the ixgbe driver to take advantage of PCIe Relaxed Ordering, as observed on the HiSilicon D05 system.
[Test Case]
Setup two servers with dual-port PCIe ixgbe cards, connected back-to-back.
= server =
taskset -c 0-15 iperf -s -B 192.168.80.11
taskset -c 16-31 iperf -s -B 192.168.90.11
= client =
taskset -c 0-15 iperf -c 192.168.80.11 -i 3 -t 600 -P 8 &
taskset -c 16-31 iperf -c 192.168.90.11 -i 3 -t 600 -P 8 &
Without these patches, we observe an aggregate performance of 8.54 Gbit/sec. With these patches, we observe an aggregate performance of 18.82 Gbit/sec.
[Regression Risk]
The following risk assessment applies to both artful and zesty - but note that the bulk of these changes are *already in artful*. The proposed SRU for artful would just allow an additional driver to take advantage of it. For zesty, an SRU would need to both introduce this feature and enable it for both the cxgb4 and ixgbe drivers.
The patchset is careful to only enable Relaxed Ordering if advertised up through the root port. However, it is possible that enabling RO on hardware that supports it could actually regress performance, or that there is hw out there that advertises RO, but has bugs in the implementation. The patch series includes quirks for HW where RO is advertised but known to have issues[*] - but this list maybe incomplete. This would only impact devices w/ drivers that take advantage of RO - currently cxgb4 and (not yet upstream) ixgbe.
Also, there is a possibility of a crash caused by a coding error. One such issue has already been found and fixed upstream [**], and is part of this series.
The risk of both of these regressions is reduced by the fact that this code is upstream, and has therefore gotten a lot more testing that has not resulted in regressions reports.
[*]
commit 077fa19c5dfa06a6ae04fb1661680940ff837612
Author: dingtianhong <dingtianhong@huawei.com>
Date: Tue Aug 15 11:23:25 2017 +0800
PCI: Disable Relaxed Ordering Attributes for AMD A110
commit 87e09cdec4dae08acdb4aa49beb793c19d73e73e
Author: dingtianhong <dingtianhong@huawei.com>
Date: Tue Aug 15 11:23:24 2017 +0800
PCI: Disable Relaxed Ordering for some Intel processors
[**]
commit 0e405232871d67bf1b238d56b6b3d500e69ebbf3
Author: dingtianhong <dingtianhong@huawei.com>
Date: Tue Aug 15 23:24:48 2017 +0800
PCI: fix oops when try to find Root Port for a PCI device |
|
| 2017-11-07 22:16:31 |
dann frazier |
description |
[Impact]
A signficant performance gain can be achieved with the iperf benchmark by allowing the ixgbe driver to take advantage of PCIe Relaxed Ordering, as observed on the HiSilicon D05 system.
[Test Case]
Setup two servers with dual-port PCIe ixgbe cards, connected back-to-back.
= server =
taskset -c 0-15 iperf -s -B 192.168.80.11
taskset -c 16-31 iperf -s -B 192.168.90.11
= client =
taskset -c 0-15 iperf -c 192.168.80.11 -i 3 -t 600 -P 8 &
taskset -c 16-31 iperf -c 192.168.90.11 -i 3 -t 600 -P 8 &
Without these patches, we observe an aggregate performance of 8.54 Gbit/sec. With these patches, we observe an aggregate performance of 18.82 Gbit/sec.
[Regression Risk]
The following risk assessment applies to both artful and zesty - but note that the bulk of these changes are *already in artful*. The proposed SRU for artful would just allow an additional driver to take advantage of it. For zesty, an SRU would need to both introduce this feature and enable it for both the cxgb4 and ixgbe drivers.
The patchset is careful to only enable Relaxed Ordering if advertised up through the root port. However, it is possible that enabling RO on hardware that supports it could actually regress performance, or that there is hw out there that advertises RO, but has bugs in the implementation. The patch series includes quirks for HW where RO is advertised but known to have issues[*] - but this list maybe incomplete. This would only impact devices w/ drivers that take advantage of RO - currently cxgb4 and (not yet upstream) ixgbe.
Also, there is a possibility of a crash caused by a coding error. One such issue has already been found and fixed upstream [**], and is part of this series.
The risk of both of these regressions is reduced by the fact that this code is upstream, and has therefore gotten a lot more testing that has not resulted in regressions reports.
[*]
commit 077fa19c5dfa06a6ae04fb1661680940ff837612
Author: dingtianhong <dingtianhong@huawei.com>
Date: Tue Aug 15 11:23:25 2017 +0800
PCI: Disable Relaxed Ordering Attributes for AMD A110
commit 87e09cdec4dae08acdb4aa49beb793c19d73e73e
Author: dingtianhong <dingtianhong@huawei.com>
Date: Tue Aug 15 11:23:24 2017 +0800
PCI: Disable Relaxed Ordering for some Intel processors
[**]
commit 0e405232871d67bf1b238d56b6b3d500e69ebbf3
Author: dingtianhong <dingtianhong@huawei.com>
Date: Tue Aug 15 23:24:48 2017 +0800
PCI: fix oops when try to find Root Port for a PCI device |
[Impact]
A signficant performance gain can be achieved with the iperf benchmark by allowing the ixgbe driver to take advantage of PCIe Relaxed Ordering, as observed on the HiSilicon D05 system.
[Test Case]
Setup two servers with dual-port PCIe ixgbe cards, connected back-to-back.
= server =
taskset -c 0-15 iperf -s -B 192.168.80.11 &
taskset -c 16-31 iperf -s -B 192.168.90.11 &
= client =
taskset -c 0-15 iperf -c 192.168.80.11 -i 3 -t 600 -P 8 &
taskset -c 16-31 iperf -c 192.168.90.11 -i 3 -t 600 -P 8 &
Without these patches, we observe an aggregate performance of 8.54 Gbit/sec. With these patches, we observe an aggregate performance of 18.82 Gbit/sec.
[Regression Risk]
The following risk assessment applies to both artful and zesty - but note that the bulk of these changes are *already in artful*. The proposed SRU for artful would just allow an additional driver to take advantage of it. For zesty, an SRU would need to both introduce this feature and enable it for both the cxgb4 and ixgbe drivers.
The patchset is careful to only enable Relaxed Ordering if advertised up through the root port. However, it is possible that enabling RO on hardware that supports it could actually regress performance, or that there is hw out there that advertises RO, but has bugs in the implementation. The patch series includes quirks for HW where RO is advertised but known to have issues[*] - but this list maybe incomplete. This would only impact devices w/ drivers that take advantage of RO - currently cxgb4 and (not yet upstream) ixgbe.
Also, there is a possibility of a crash caused by a coding error. One such issue has already been found and fixed upstream [**], and is part of this series.
The risk of both of these regressions is reduced by the fact that this code is upstream, and has therefore gotten a lot more testing that has not resulted in regressions reports.
[*]
commit 077fa19c5dfa06a6ae04fb1661680940ff837612
Author: dingtianhong <dingtianhong@huawei.com>
Date: Tue Aug 15 11:23:25 2017 +0800
PCI: Disable Relaxed Ordering Attributes for AMD A110
commit 87e09cdec4dae08acdb4aa49beb793c19d73e73e
Author: dingtianhong <dingtianhong@huawei.com>
Date: Tue Aug 15 11:23:24 2017 +0800
PCI: Disable Relaxed Ordering for some Intel processors
[**]
commit 0e405232871d67bf1b238d56b6b3d500e69ebbf3
Author: dingtianhong <dingtianhong@huawei.com>
Date: Tue Aug 15 23:24:48 2017 +0800
PCI: fix oops when try to find Root Port for a PCI device |
|
| 2017-11-07 23:02:03 |
dann frazier |
linux (Ubuntu Zesty): status |
Confirmed |
In Progress |
|
| 2017-11-15 16:40:19 |
dann frazier |
summary |
ixgbe/PCIe: Allow drivers to use Relaxed Ordering on capable root ports |
Allow drivers to use Relaxed Ordering on capable root ports |
|
| 2017-11-20 10:52:08 |
Stefan Bader |
linux (Ubuntu Artful): status |
In Progress |
Fix Committed |
|
| 2017-11-29 15:16:19 |
Khaled El Mously |
tags |
|
verification-needed-artful |
|
| 2017-12-01 22:49:37 |
dann frazier |
tags |
verification-needed-artful |
verification-done-artful |
|
| 2017-12-01 23:00:35 |
dann frazier |
linux (Ubuntu Zesty): status |
In Progress |
Won't Fix |
|
| 2017-12-01 23:00:42 |
dann frazier |
linux (Ubuntu): status |
In Progress |
Fix Committed |
|
| 2017-12-07 17:42:36 |
Launchpad Janitor |
linux (Ubuntu Artful): status |
Fix Committed |
Fix Released |
|
| 2017-12-07 17:42:36 |
Launchpad Janitor |
cve linked |
|
2017-1000405 |
|
| 2018-01-10 01:35:55 |
Launchpad Janitor |
linux (Ubuntu): status |
Fix Committed |
Fix Released |
|
| 2018-01-10 01:35:55 |
Launchpad Janitor |
cve linked |
|
2017-16995 |
|
| 2018-01-10 01:35:55 |
Launchpad Janitor |
cve linked |
|
2017-17862 |
|
| 2018-01-10 01:35:55 |
Launchpad Janitor |
cve linked |
|
2017-17863 |
|
| 2018-01-10 01:35:55 |
Launchpad Janitor |
cve linked |
|
2017-17864 |
|
| 2018-01-10 01:35:55 |
Launchpad Janitor |
cve linked |
|
2017-5754 |
|
