| 2022-11-30 20:35:41 |
Brad Figg |
description |
There are a set of patches on linux-next upstream that are required as part of NVIDIA SOC enablement. These patches need to be integrated into the Optimized linux-nvidia-5.19 kernel. |
There are a set of patches on linux-next upstream that are required as part of NVIDIA SOC enablement. These patches need to be integrated into the Optimized linux-nvidia-5.19 kernel.
ARM Performance Monitoring Unit Table describes the properties of PMU
support in ARM-based system. The APMT table contains a list of nodes,
each represents a PMU in the system that conforms to ARM CoreSight PMU
architecture. The properties of each node include information required
to access the PMU (e.g. MMIO base address, interrupt number) and also
identification. For more detailed information, please refer to the
specification below:
* APMT: https://developer.arm.com/documentation/den0117/latest
* ARM Coresight PMU:
https://developer.arm.com/documentation/ihi0091/latest
The initial support adds the detection of APMT table and generic
infrastructure to create platform devices for ARM CoreSight PMUs.
Similar to IORT the root pointer of APMT is preserved during runtime
and each PMU platform device is given a pointer to the corresponding
APMT node. |
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