libverilog-perl 3.412-1 source package in Ubuntu
Changelog
libverilog-perl (3.412-1) unstable; urgency=medium [ أحمد المحمودي (Ahmed El-Mahmoudy) ] * New upstream release. * Update copyright years. * Update my email address. [ gregor herrmann ] * Mark package as autopkgtest-able. -- أحمد المحمودي (Ahmed El-Mahmoudy) <email address hidden> Wed, 29 Apr 2015 13:41:26 +0200
Upload details
- Uploaded by:
- Debian Perl Group
- Uploaded to:
- Sid
- Original maintainer:
- Debian Perl Group
- Architectures:
- any
- Section:
- perl
- Urgency:
- Medium Urgency
See full publishing history Publishing
| Series | Published | Component | Section |
|---|
Downloads
| File | Size | SHA-256 Checksum |
|---|---|---|
| libverilog-perl_3.412-1.dsc | 2.4 KiB | 2c54591f8a95935d5428b34fa74661883a757504b934f5e43c7b8c0c1556ab3a |
| libverilog-perl_3.412.orig.tar.gz | 545.1 KiB | 38cce8c7817c8c07c61441ca1d5f1f92e26c55c937388b76dcbe400fcf5296eb |
| libverilog-perl_3.412-1.debian.tar.xz | 7.2 KiB | f6505b05c7d987d8910c40cef7f00324c783e95d1aa961d2bd9c510634f7d3e8 |
Available diffs
- diff from 3.406-1 to 3.412-1 (310.4 KiB)
No changes file available.
Binary packages built by this source
- libverilog-perl: No summary available for libverilog-perl in ubuntu wily.
No description available for libverilog-perl in ubuntu wily.
- libverilog-perl-dbgsym: debug symbols for package libverilog-perl
Verilog is a Perl framework providing Verilog support in the Perl language.
It includes:
.
* Verilog::Getopt, which parses command line options similar to C++ and VCS
* Verilog::Language, which knows the language keywords and parses numbers.
* Verilog::Netlist, which builds netlists out of Verilog files. This allows
easy scripts to determine things such as the hierarchy of modules.
* Verilog::Parser, which invokes callbacks for language tokens
* Verilog::Preproc, preprocesses the language, and allows reading
post-processed files right from Perl without temporary files.
.
It also includes a variety of useful utilities:
.
* vpassert inserts PLIish warnings and assertions for any simulator
* vppreproc preprocesses the complete Verilog 2001 and SystemVerilog
language
* vrename renames and cross-references Verilog symbols. It creates Verilog
cross references and makes it easy to rename signal and module names over
multiple files.
