libverilog-perl 3.312-1 source package in Ubuntu
Changelog
libverilog-perl (3.312-1) unstable; urgency=low
* New upstream release.
libverilog-perl (3.311-1) unstable; urgency=low
[ Salvatore Bonaccorso ]
* debian/copyright: Replace DEP5 Format-Specification URL from
svn.debian.org to anonscm.debian.org URL.
[ أحمد المحمودي (Ahmed El-Mahmoudy) ]
* New upstream release.
* debian/copyright: Updated copyright format.
-- Ubuntu Archive Auto-Sync <email address hidden> Wed, 02 Nov 2011 12:50:57 +0000
Upload details
- Uploaded by:
- Ubuntu Archive Auto-Sync
- Uploaded to:
- Precise
- Original maintainer:
- Debian Perl Group
- Architectures:
- any
- Section:
- perl
- Urgency:
- Low Urgency
See full publishing history Publishing
| Series | Published | Component | Section |
|---|
Downloads
| File | Size | SHA-256 Checksum |
|---|---|---|
| libverilog-perl_3.312.orig.tar.gz | 526.3 KiB | d088be1b830d4042b0373a487c34c41c137ada82b3e27e121386ce63b3aec570 |
| libverilog-perl_3.312-1.debian.tar.gz | 6.0 KiB | 7c70241d5630f3a1d32b79040653b324322db5147ed6022580ba6e8543b087b3 |
| libverilog-perl_3.312-1.dsc | 2.1 KiB | 635da21ca88e212eae488af03695e51d32862f62f4473f82c23aa47e05b60c12 |
Available diffs
- diff from 3.310-1 to 3.312-1 (271.9 KiB)
Binary packages built by this source
- libverilog-perl: framework providing Verilog support
Verilog is a Perl framework providing Verilog support in the Perl language.
It includes:
.
* Verilog::Getopt, which parses command line options similar to C++ and VCS
* Verilog::Language, which knows the language keywords and parses numbers.
* Verilog::Netlist, which builds netlists out of Verilog files. This allows
easy scripts to determine things such as the hierarchy of modules.
* Verilog::Parser, which invokes callbacks for language tokens
* Verilog::Preproc, preprocesses the language, and allows reading
post-processed files right from Perl without temporary files.
.
It also includes a variety of useful utilities:
.
* vpassert inserts PLIish warnings and assertions for any simulator
* vppreproc preprocesses the complete Verilog 2001 and SystemVerilog
language
* vrename renames and cross-references Verilog symbols. It creates Verilog
cross references and makes it easy to rename signal and module names over
multiple files.
