diff -Nru libpfm4-4.11.1+git32-gd0b85fb/debian/changelog libpfm4-4.11.1+git32-gd0b85fb/debian/changelog --- libpfm4-4.11.1+git32-gd0b85fb/debian/changelog 2021-06-16 16:32:36.000000000 +0200 +++ libpfm4-4.11.1+git32-gd0b85fb/debian/changelog 2022-08-29 12:39:14.000000000 +0200 @@ -1,3 +1,10 @@ +libpfm4 (4.11.1+git32-gd0b85fb-1ubuntu0.1) jammy; urgency=medium + + * Add d/p/lp-1960118-s390-Update-counter-definition-for-IBM-z16.patch + to add new CPU-MF counters for new IBM zSystems hardware. + + -- Frank Heimes Mon, 29 Aug 2022 12:39:14 +0200 + libpfm4 (4.11.1+git32-gd0b85fb-1) unstable; urgency=medium * New upstream GIT snapshot. diff -Nru libpfm4-4.11.1+git32-gd0b85fb/debian/control libpfm4-4.11.1+git32-gd0b85fb/debian/control --- libpfm4-4.11.1+git32-gd0b85fb/debian/control 2021-06-16 16:32:36.000000000 +0200 +++ libpfm4-4.11.1+git32-gd0b85fb/debian/control 2022-08-29 12:39:14.000000000 +0200 @@ -1,7 +1,8 @@ Source: libpfm4 Section: libs Priority: optional -Maintainer: Debian HPC Team +Maintainer: Ubuntu Developers +XSBC-Original-Maintainer: Debian HPC Team Uploaders: Vincent Danjean , Andreas Beckmann , diff -Nru libpfm4-4.11.1+git32-gd0b85fb/debian/patches/lp-1960118-s390-Update-counter-definition-for-IBM-z16.patch libpfm4-4.11.1+git32-gd0b85fb/debian/patches/lp-1960118-s390-Update-counter-definition-for-IBM-z16.patch --- libpfm4-4.11.1+git32-gd0b85fb/debian/patches/lp-1960118-s390-Update-counter-definition-for-IBM-z16.patch 1970-01-01 01:00:00.000000000 +0100 +++ libpfm4-4.11.1+git32-gd0b85fb/debian/patches/lp-1960118-s390-Update-counter-definition-for-IBM-z16.patch 2022-08-29 09:12:27.000000000 +0200 @@ -0,0 +1,639 @@ +From b03a81ea006658b3aa478e22f4d0b7741cf7346f Mon Sep 17 00:00:00 2001 +From: Thomas Richter +Date: Tue, 31 May 2022 05:47:23 -0700 +Subject: [PATCH] s390: Update counter definition for IBM z16 + +This patch updates the libpfm4 s390 counter definitions to the +latest documentation: + +SA23-2261-07:The CPU-Measurement Facility Extended Counters + Definition for z10, z196/z114, zEC12/zBC12, z13/z13s, + z14, z15 and z16 + April 29, 2022 + +https://www.ibm.com/support/pages/cpu-measurement-facility-extended-counters-definition-z10-z196z114-zec12zbc12-z13z13s-z14-z15-and-z16 + +This includes updated counter description for existing counters +and the complete counter definition for IBM z16. + +Signed-off-by: Thomas Richter +Acked-by: Sumanth Korikkar +Origin: upstream, https://sourceforge.net/p/perfmon2/libpfm4/ci/b03a81ea006658b3aa478e22f4d0b7741cf7346f +Bug-Ubuntu: https://bugs.launchpad.net/bugs/1960118 +Last-Update: 2022-08-29 + +--- + lib/events/s390x_cpumf_events.h | 580 ++++++++++++++++++++++++++++++++ + lib/pfmlib_s390x_cpumf.c | 5 + + 2 files changed, 585 insertions(+) + +diff --git a/lib/events/s390x_cpumf_events.h b/lib/events/s390x_cpumf_events.h +index 965fe61..0eeeb7e 100644 +--- a/lib/events/s390x_cpumf_events.h ++++ b/lib/events/s390x_cpumf_events.h +@@ -2263,6 +2263,586 @@ static const pme_cpumf_ctr_t cpumcf_z15_counters[] = { + }, + }; + ++static const pme_cpumf_ctr_t cpumcf_z16_counters[] = { ++ { ++ .ctrnum = 128, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "L1D_RO_EXCL_WRITES", ++ .desc = "A directory write to the Level-1 Data cache where" ++ " the line was originally in a Read-Only state in the" ++ " cache but has been updated to be in the Exclusive" ++ " state that allows stores to the cache line.", ++ }, ++ { ++ .ctrnum = 129, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "DTLB2_WRITES", ++ .desc = "A translation has been written into The Translation" ++ " Lookaside Buffer 2 (TLB2) and the request was made" ++ " by the Level-1 Data cache. This is a replacement" ++ " for what was provided for the DTLB on z13 and prior" ++ " machines.", ++ }, ++ { ++ .ctrnum = 130, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "DTLB2_MISSES", ++ .desc = "A TLB2 miss is in progress for a request made by" ++ " the Level-1 Data cache. Incremented by one for" ++ " every TLB2 miss in progress for the Level-1 Data" ++ " cache on this cycle. This is a replacement for what" ++ " was provided for the DTLB on z13 and prior" ++ " machines.", ++ }, ++ { ++ .ctrnum = 131, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "CRSTE_1MB_WRITES", ++ .desc = "A translation entry was written into the Combined" ++ " Region and Segment Table Entry array in the Level-2" ++ " TLB for a one-megabyte page.", ++ }, ++ { ++ .ctrnum = 132, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "DTLB2_GPAGE_WRITES", ++ .desc = "A translation entry for a two-gigabyte page was" ++ " written into the Level-2 TLB.", ++ }, ++ { ++ .ctrnum = 134, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "ITLB2_WRITES", ++ .desc = "A translation entry has been written into the" ++ " Translation Lookaside Buffer 2 (TLB2) and the" ++ " request was made by the instruction cache. This is" ++ " a replacement for what was provided for the ITLB on" ++ " z13 and prior machines.", ++ }, ++ { ++ .ctrnum = 135, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "ITLB2_MISSES", ++ .desc = "A TLB2 miss is in progress for a request made by" ++ " the Level-1 Instruction cache. Incremented by one" ++ " for every TLB2 miss in progress for the Level-1" ++ " Instruction cache in a cycle. This is a replacement" ++ " for what was provided for the ITLB on z13 and prior" ++ " machines.", ++ }, ++ { ++ .ctrnum = 137, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "TLB2_PTE_WRITES", ++ .desc = "A translation entry was written into the Page Table" ++ " Entry array in the Level-2 TLB.", ++ }, ++ { ++ .ctrnum = 138, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "TLB2_CRSTE_WRITES", ++ .desc = "Translation entries were written into the Combined" ++ " Region and Segment Table Entry array and the Page" ++ " Table Entry array in the Level-2 TLB.", ++ }, ++ { ++ .ctrnum = 139, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "TLB2_ENGINES_BUSY", ++ .desc = "The number of Level-2 TLB translation engines busy" ++ " in a cycle.", ++ }, ++ { ++ .ctrnum = 140, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "TX_C_TEND", ++ .desc = "A TEND instruction has completed in a constrained" ++ " transactional-execution mode.", ++ }, ++ { ++ .ctrnum = 141, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "TX_NC_TEND", ++ .desc = "A TEND instruction has completed in a non-" ++ " constrained transactional-execution mode.", ++ }, ++ { ++ .ctrnum = 143, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "L1C_TLB2_MISSES", ++ .desc = "Increments by one for any cycle where a level-1" ++ " cache or level-2 TLB miss is in progress.", ++ }, ++ { ++ .ctrnum = 145, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "DCW_REQ", ++ .desc = "A directory write to the Level-1 Data cache" ++ " directory where the returned cache line was sourced" ++ " from the requestor's Level-2 cache.", ++ }, ++ { ++ .ctrnum = 146, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "DCW_REQ_IV", ++ .desc = "A directory write to the Level-1 Data cache" ++ " directory where the returned cache line was sourced" ++ " from the requestor's Level-2 cache with" ++ " intervention.", ++ }, ++ { ++ .ctrnum = 147, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "DCW_REQ_CHIP_HIT", ++ .desc = "A directory write to the Level-1 Data cache" ++ " directory where the returned cache line was sourced" ++ " from the requestor's Level-2 cache after using" ++ " chip level horizontal persistence, Chip-HP hit.", ++ }, ++ { ++ .ctrnum = 148, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "DCW_REQ_DRAWER_HIT", ++ .desc = "A directory write to the Level-1 Data cache" ++ " directory where the returned cache line was sourced" ++ " from the requestor's Level-2 cache after using" ++ " drawer level horizontal persistence, Drawer-HP hit.", ++ }, ++ { ++ .ctrnum = 149, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "DCW_ON_CHIP", ++ .desc = "A directory write to the Level-1 Data cache" ++ " directory where the returned cache line was sourced" ++ " from an On-Chip Level-2 cache.", ++ }, ++ { ++ .ctrnum = 150, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "DCW_ON_CHIP_IV", ++ .desc = "A directory write to the Level-1 Data cache" ++ " directory where the returned cache line was sourced" ++ " from an On-Chip Level-2 cache with intervention.", ++ }, ++ { ++ .ctrnum = 151, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "DCW_ON_CHIP_CHIP_HIT", ++ .desc = "A directory write to the Level-1 Data cache" ++ " directory where the returned cache line was sourced" ++ " from an On-Chip Level-2 cache after using chip" ++ " level horizontal persistence, Chip-HP hit.", ++ }, ++ { ++ .ctrnum = 152, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "DCW_ON_CHIP_DRAWER_HIT", ++ .desc = "A directory write to the Level-1 Data cache" ++ " directory where the returned cache line was sourced" ++ " from an On-Chip Level-2 cache using drawer level" ++ " horizontal persistence, Drawer-HP hit.", ++ }, ++ { ++ .ctrnum = 153, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "DCW_ON_MODULE", ++ .desc = "A directory write to the Level-1 Data cache" ++ " directory where the returned cache line was sourced" ++ " from an On-Module Level-2 cache.", ++ }, ++ { ++ .ctrnum = 154, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "DCW_ON_DRAWER", ++ .desc = "A directory write to the Level-1 Data cache" ++ " directory where the returned cache line was sourced" ++ " from an On-Drawer Level-2 cache.", ++ }, ++ { ++ .ctrnum = 155, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "DCW_OFF_DRAWER", ++ .desc = "A directory write to the Level-1 Data cache" ++ " directory where the returned cache line was sourced" ++ " from an Off-Drawer Level-2 cache.", ++ }, ++ { ++ .ctrnum = 156, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "DCW_ON_CHIP_MEMORY", ++ .desc = "A directory write to the Level-1 Data cache" ++ " directory where the returned cache line was sourced" ++ " from On-Chip memory.", ++ }, ++ { ++ .ctrnum = 157, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "DCW_ON_MODULE_MEMORY", ++ .desc = "A directory write to the Level-1 Data cache" ++ " directory where the returned cache line was sourced" ++ " from On-Module memory.", ++ }, ++ { ++ .ctrnum = 158, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "DCW_ON_DRAWER_MEMORY", ++ .desc = "A directory write to the Level-1 Data cache" ++ " directory where the returned cache line was sourced" ++ " from On-Drawer memory.", ++ }, ++ { ++ .ctrnum = 159, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "DCW_OFF_DRAWER_MEMORY", ++ .desc = "A directory write to the Level-1 Data cache" ++ " directory where the returned cache line was sourced" ++ " from Off-Drawer memory.", ++ }, ++ { ++ .ctrnum = 160, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "IDCW_ON_MODULE_IV", ++ .desc = "A directory write to the Level-1 Data or Level-1" ++ " Instruction cache directory where the returned" ++ " cache line was sourced from an On-Module Level-2" ++ " cache with intervention.", ++ }, ++ { ++ .ctrnum = 161, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "IDCW_ON_MODULE_CHIP_HIT", ++ .desc = "A directory write to the Level-1 Data or Level-1" ++ " Instruction cache directory where the returned" ++ " cache line was sourced from an On-Module Level-2" ++ " cache using chip horizontal persistence, Chip-HP" ++ " hit.", ++ }, ++ { ++ .ctrnum = 162, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "IDCW_ON_MODULE_DRAWER_HIT", ++ .desc = "A directory write to the Level-1 Data or Level-1" ++ " Instruction cache directory where the returned" ++ " cache line was sourced from an On-Module Level-2" ++ " cache using drawer level horizontal persistence," ++ " Drawer-HP hit.", ++ }, ++ { ++ .ctrnum = 163, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "IDCW_ON_DRAWER_IV", ++ .desc = "A directory write to the Level-1 Data or Level-1" ++ " Instruction cache directory where the returned" ++ " cache line was sourced from an On-Drawer Level-2" ++ " cache with intervention.", ++ }, ++ { ++ .ctrnum = 164, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "IDCW_ON_DRAWER_CHIP_HIT", ++ .desc = "A directory write to the Level-1 Data or Level-1" ++ " instruction cache directory where the returned" ++ " cache line was sourced from an On-Drawer Level-2" ++ " cache using chip level horizontal persistence, Chip-" ++ " HP hit.", ++ }, ++ { ++ .ctrnum = 165, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "IDCW_ON_DRAWER_DRAWER_HIT", ++ .desc = "A directory write to the Level-1 Data or Level-1" ++ " instruction cache directory where the returned" ++ " cache line was sourced from an On-Drawer Level-2" ++ " cache using drawer level horizontal persistence," ++ " Drawer-HP hit.", ++ }, ++ { ++ .ctrnum = 166, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "IDCW_OFF_DRAWER_IV", ++ .desc = "A directory write to the Level-1 Data or Level-1" ++ " instruction cache directory where the returned" ++ " cache line was sourced from an Off-Drawer Level-2" ++ " cache with intervention.", ++ }, ++ { ++ .ctrnum = 167, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "IDCW_OFF_DRAWER_CHIP_HIT", ++ .desc = "A directory write to the Level-1 Data or Level-1" ++ " instruction cache directory where the returned" ++ " cache line was sourced from an Off-Drawer Level-2" ++ " cache using chip level horizontal persistence, Chip-" ++ " HP hit.", ++ }, ++ { ++ .ctrnum = 168, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "IDCW_OFF_DRAWER_DRAWER_HIT", ++ .desc = "A directory write to the Level-1 Data or Level-1" ++ " Instruction cache directory where the returned" ++ " cache line was sourced from an Off-Drawer Level-2" ++ " cache using drawer level horizontal persistence," ++ " Drawer-HP hit.", ++ }, ++ { ++ .ctrnum = 169, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "ICW_REQ", ++ .desc = "A directory write to the Level-1 Instruction cache" ++ " directory where the returned cache line was sourced" ++ " the requestors Level-2 cache.", ++ }, ++ { ++ .ctrnum = 170, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "ICW_REQ_IV", ++ .desc = "A directory write to the Level-1 Instruction cache" ++ " directory where the returned cache line was sourced" ++ " from the requestors Level-2 cache with" ++ " intervention.", ++ }, ++ { ++ .ctrnum = 171, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "ICW_REQ_CHIP_HIT", ++ .desc = "A directory write to the Level-1 Instruction cache" ++ " directory where the returned cache line was sourced" ++ " from the requestors Level-2 cache using chip level" ++ " horizontal persistence, Chip-HP hit.", ++ }, ++ { ++ .ctrnum = 172, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "ICW_REQ_DRAWER_HIT", ++ .desc = "A directory write to the Level-1 Instruction cache" ++ " directory where the returned cache line was sourced" ++ " from the requestor's Level-2 cache using drawer" ++ " level horizontal persistence, Drawer-HP hit.", ++ }, ++ { ++ .ctrnum = 173, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "ICW_ON_CHIP", ++ .desc = "A directory write to the Level-1 Instruction cache" ++ " directory where the returned cache line was sourced" ++ " from an On-Chip Level-2 cache.", ++ }, ++ { ++ .ctrnum = 174, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "ICW_ON_CHIP_IV", ++ .desc = "A directory write to the Level-1 Instruction cache" ++ " directory where the returned cache line was sourced" ++ " an On-Chip Level-2 cache with intervention.", ++ }, ++ { ++ .ctrnum = 175, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "ICW_ON_CHIP_CHIP_HIT", ++ .desc = "A directory write to the Level-1 Instruction cache" ++ " directory where the returned cache line was sourced" ++ " from an On-Chip Level-2 cache using chip level" ++ " horizontal persistence, Chip-HP hit.", ++ }, ++ { ++ .ctrnum = 176, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "ICW_ON_CHIP_DRAWER_HIT", ++ .desc = "A directory write to the Level-1 Instruction cache" ++ " directory where the returned cache line was sourced" ++ " from an On-Chip level 2 cache using drawer level" ++ " horizontal persistence, Drawer-HP hit.", ++ }, ++ { ++ .ctrnum = 177, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "ICW_ON_MODULE", ++ .desc = "A directory write to the Level-1 Instruction cache" ++ " directory where the returned cache line was sourced" ++ " from an On-Module Level-2 cache.", ++ }, ++ { ++ .ctrnum = 178, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "ICW_ON_DRAWER", ++ .desc = "A directory write to the Level-1 Instruction cache" ++ " directory where the returned cache line was sourced" ++ " an On-Drawer Level-2 cache.", ++ }, ++ { ++ .ctrnum = 179, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "ICW_OFF_DRAWER", ++ .desc = "A directory write to the Level-1 Instruction cache" ++ " directory where the returned cache line was sourced" ++ " an Off-Drawer Level-2 cache.", ++ }, ++ { ++ .ctrnum = 180, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "ICW_ON_CHIP_MEMORY", ++ .desc = "A directory write to the Level-1 Instruction cache" ++ " directory where the returned cache line was sourced" ++ " from On-Chip memory.", ++ }, ++ { ++ .ctrnum = 181, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "ICW_ON_MODULE_MEMORY", ++ .desc = "A directory write to the Level-1 Instruction cache" ++ " directory where the returned cache line was sourced" ++ " from On-Module memory.", ++ }, ++ { ++ .ctrnum = 182, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "ICW_ON_DRAWER_MEMORY", ++ .desc = "A directory write to the Level-1 Instruction cache" ++ " directory where the returned cache line was sourced" ++ " from On-Drawer memory.", ++ }, ++ { ++ .ctrnum = 183, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "ICW_OFF_DRAWER_MEMORY", ++ .desc = "A directory write to the Level-1 Instruction cache" ++ " directory where the returned cache line was sourced" ++ " from Off-Drawer memory.", ++ }, ++ { ++ .ctrnum = 224, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "BCD_DFP_EXECUTION_SLOTS", ++ .desc = "Count of floating point execution slots used for" ++ " finished Binary Coded Decimal to Decimal Floating" ++ " Point conversions. Instructions: CDZT, CXZT, CZDT," ++ " CZXT.", ++ }, ++ { ++ .ctrnum = 225, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "VX_BCD_EXECUTION_SLOTS", ++ .desc = "Count of floating point execution slots used for" ++ " finished vector arithmetic Binary Coded Decimal" ++ " instructions. Instructions: VAP, VSP, VMP, VMSP," ++ " VDP, VSDP, VRP, VLIP, VSRP, VPSOP, VCP, VTP, VPKZ," ++ " VUPKZ, VCVB, VCVBG, VCVD, VCVDG.", ++ }, ++ { ++ .ctrnum = 226, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "DECIMAL_INSTRUCTIONS", ++ .desc = "Decimal instruction dispatched. Instructions: CVB," ++ " CVD, AP, CP, DP, ED, EDMK, MP, SRP, SP, ZAP.", ++ }, ++ { ++ .ctrnum = 232, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "LAST_HOST_TRANSLATIONS", ++ .desc = "Last Host Translation done", ++ }, ++ { ++ .ctrnum = 244, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "TX_NC_TABORT", ++ .desc = "A transaction abort has occurred in a non-" ++ " constrained transactional-execution mode.", ++ }, ++ { ++ .ctrnum = 245, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "TX_C_TABORT_NO_SPECIAL", ++ .desc = "A transaction abort has occurred in a constrained" ++ " transactional-execution mode and the CPU is not" ++ " using any special logic to allow the transaction to" ++ " complete.", ++ }, ++ { ++ .ctrnum = 246, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "TX_C_TABORT_SPECIAL", ++ .desc = "A transaction abort has occurred in a constrained" ++ " transactional-execution mode and the CPU is using" ++ " special logic to allow the transaction to complete.", ++ }, ++ { ++ .ctrnum = 248, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "DFLT_ACCESS", ++ .desc = "Cycles CPU spent obtaining access to Deflate unit", ++ }, ++ { ++ .ctrnum = 253, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "DFLT_CYCLES", ++ .desc = "Cycles CPU is using Deflate unit", ++ }, ++ { ++ .ctrnum = 256, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "SORTL", ++ .desc = "Increments by one for every SORT LISTS instruction" ++ " executed.", ++ }, ++ { ++ .ctrnum = 265, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "DFLT_CC", ++ .desc = "Increments by one for every DEFLATE CONVERSION CALL" ++ " instruction executed.", ++ }, ++ { ++ .ctrnum = 266, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "DFLT_CCFINISH", ++ .desc = "Increments by one for every DEFLATE CONVERSION CALL" ++ " instruction executed that ended in Condition Codes" ++ " 0, 1 or 2.", ++ }, ++ { ++ .ctrnum = 267, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "NNPA_INVOCATIONS", ++ .desc = "Increments by one for every Neural Network" ++ " Processing Assist instruction executed.", ++ }, ++ { ++ .ctrnum = 268, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "NNPA_COMPLETIONS", ++ .desc = "Increments by one for every Neural Network" ++ " Processing Assist instruction executed that ended" ++ " in Condition Codes 0, 1 or 2.", ++ }, ++ { ++ .ctrnum = 269, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "NNPA_WAIT_LOCK", ++ .desc = "Cycles CPU spent obtaining access to IBM Z" ++ " Integrated Accelerator for AI.", ++ }, ++ { ++ .ctrnum = 270, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "NNPA_HOLD_LOCK", ++ .desc = "Cycles CPU is using IBM Z Integrated Accelerator" ++ " for AI.", ++ }, ++ { ++ .ctrnum = 448, ++ .ctrset = CPUMF_CTRSET_MT_DIAG, ++ .name = "MT_DIAG_CYCLES_ONE_THR_ACTIVE", ++ .desc = "Cycle count with one thread active", ++ }, ++ { ++ .ctrnum = 449, ++ .ctrset = CPUMF_CTRSET_MT_DIAG, ++ .name = "MT_DIAG_CYCLES_TWO_THR_ACTIVE", ++ .desc = "Cycle count with two threads active", ++ }, ++}; ++ + static const pme_cpumf_ctr_t cpumsf_counters[] = { + { + .ctrnum = 720896, +diff --git a/lib/pfmlib_s390x_cpumf.c b/lib/pfmlib_s390x_cpumf.c +index 2c7e573..d8ce22d 100644 +--- a/lib/pfmlib_s390x_cpumf.c ++++ b/lib/pfmlib_s390x_cpumf.c +@@ -203,6 +203,11 @@ static int pfm_cpumcf_init(void *this) + ext_set = cpumcf_z15_counters; + ext_set_count = LIBPFM_ARRAY_SIZE(cpumcf_z15_counters); + break; ++ case 3931: /* IBM Machine types 3931 and 3932 */ ++ case 3932: ++ ext_set = cpumcf_z16_counters; ++ ext_set_count = LIBPFM_ARRAY_SIZE(cpumcf_z16_counters); ++ break; + default: + /* No extended counter set for this machine type or there + * was an error retrieving the machine type */ +-- +2.25.1 + diff -Nru libpfm4-4.11.1+git32-gd0b85fb/debian/patches/series libpfm4-4.11.1+git32-gd0b85fb/debian/patches/series --- libpfm4-4.11.1+git32-gd0b85fb/debian/patches/series 2021-06-16 16:32:36.000000000 +0200 +++ libpfm4-4.11.1+git32-gd0b85fb/debian/patches/series 2022-08-29 09:12:48.000000000 +0200 @@ -2,3 +2,4 @@ sparc-disable-conflicting-code-4.patch reproducible.patch typos.patch +lp-1960118-s390-Update-counter-definition-for-IBM-z16.patch