iverilog 12.0-2build1 source package in Ubuntu
Changelog
iverilog (12.0-2build1) noble; urgency=medium * No-change rebuild for readline time64 change. -- Matthias Klose <email address hidden> Thu, 14 Mar 2024 02:56:23 +0100
Upload details
- Uploaded by:
- Matthias Klose
- Uploaded to:
- Noble
- Original maintainer:
- Debian Electronics Team
- Architectures:
- any
- Section:
- electronics
- Urgency:
- Medium Urgency
See full publishing history Publishing
| Series | Published | Component | Section |
|---|
Downloads
| File | Size | SHA-256 Checksum |
|---|---|---|
| iverilog_12.0.orig.tar.gz | 2.9 MiB | a68cb1ef7c017ef090ebedb2bc3e39ef90ecc70a3400afb4aa94303bc3beaa7d |
| iverilog_12.0-2build1.debian.tar.xz | 8.1 KiB | 806cc979f09b21aad568974a9e8c3b32111f7f636adcc9d486cc620ee45c06d4 |
| iverilog_12.0-2build1.dsc | 2.0 KiB | c4a95b10337a2922862a5bd7f29a349b702a43c8219b3ac884d63b413a5893e7 |
Available diffs
- diff from 12.0-2 (in Debian) to 12.0-2build1 (302 bytes)
Binary packages built by this source
- iverilog: Icarus verilog compiler
Icarus Verilog is intended to compile all of the Verilog HDL as
described in the IEEE-1364 standard. It is not quite there
yet. It does currently handle a mix of structural and behavioral
constructs.
.
The compiler can target either simulation, or netlist (EDIF).
- iverilog-dbgsym: debug symbols for iverilog
