arachne-pnr 0.1+20190728gitc40fb22-3 source package in Ubuntu
Changelog
arachne-pnr (0.1+20190728gitc40fb22-3) unstable; urgency=medium * Team Upload. * Move yosys Depends to Suggests -- Daniel Gröber <email address hidden> Wed, 16 Nov 2022 19:47:09 +0100
Upload details
- Uploaded by:
- Debian Science Team
- Uploaded to:
- Sid
- Original maintainer:
- Debian Science Team
- Architectures:
- any all
- Section:
- misc
- Urgency:
- Medium Urgency
See full publishing history Publishing
| Series | Published | Component | Section | |
|---|---|---|---|---|
| Oracular | release | universe | misc | |
| Noble | release | universe | misc | |
| Mantic | release | universe | misc | |
| Lunar | release | universe | misc |
Downloads
| File | Size | SHA-256 Checksum |
|---|---|---|
| arachne-pnr_0.1+20190728gitc40fb22-3.dsc | 2.2 KiB | 55795a0c8bcae27004c54c3bd74e8cd2c7f7168486f1654d1ebb743dc5c99e98 |
| arachne-pnr_0.1+20190728gitc40fb22.orig.tar.xz | 71.3 KiB | 811274f6054d50d5baf7c645906eb1c3ed59eda434178a1a3fc68a2ba6227420 |
| arachne-pnr_0.1+20190728gitc40fb22-3.debian.tar.xz | 7.1 KiB | 2025b2b32945fd63c8ee28d2cd40274588887da92e8474b3c3a00ddfaea04588 |
Available diffs
No changes file available.
Binary packages built by this source
- arachne-pnr: Place and route tool for iCE40 family FPGAs
Arachne-pnr implements the place and route step of the hardware compilation
process for FPGAs. It accepts as input a technology-mapped netlist in BLIF
format, as output by the Yosys synthesis suite for example. It currently
targets the Lattice Semiconductor iCE40 family of FPGAs. Its output is a
textual bitstream representation for assembly by the IceStorm icepack command.
The output of icepack is a binary bitstream which can be uploaded to a hardware
device.
.
Together, Yosys, arachne-pnr and IceStorm provide an fully open-source
Verilog-to-bistream tool chain for iCE40 1K and 8K FPGA development.
.
The authors of arachne-pnr have now prepared its successor 'nextpnr'.
- arachne-pnr-chipdb: Chip db files for arachne-pnr
Arachne-pnr implements the place and route step of the hardware compilation
process for FPGAs. It accepts as input a technology-mapped netlist in BLIF
format, as output by the Yosys synthesis suite for example. It currently
targets the Lattice Semiconductor iCE40 family of FPGAs. Its output is a
textual bitstream representation for assembly by the IceStorm icepack command.
The output of icepack is a binary bitstream which can be uploaded to a hardware
device.
.
This package contains the binary versions of the chipdb files needed by
arachne-pnr
- arachne-pnr-dbgsym: debug symbols for arachne-pnr
