On Jammy, the error message is a bit different, test end up with: FAIL: MSR_IA32_LASTBRANCHFROMIP, expected=0x4021ca, actual=0x4021ca PASS: Test that without LBRV enabled, guest LBR state does 'leak' to the host(1) Unhandled exception 6 #UD at ip 000000000040174a error_code=0000 rflags=00010097 cs=00000008 rax=0000000000000000 rcx=00000000000001d9 rdx=0000000000000000 rbx=0000000000414920 rbp=000000000042fa38 rsi=0000000000000003 rdi=0000000000414d98 r8=00000000004176f9 r9=00000000000003f8 r10=000000000000000d r11=0000000000000000 r12=0000000000000000 r13=0000000000000000 r14=0000000000000000 r15=0000000000000000 cr0=0000000080010011 cr2=0000000000000000 cr3=00000000010bf000 cr4=0000000000040020 cr8=0000000000000000 STACK: @40174a 414e48 414e48 414e48 414e48 414e48 414e48 414e48 414e48 414e48 414e48 414e48 414e48 414e48 414e48 414e48 414e48 414e48 414e48 414e48 FAIL svm Full test log: Running '/home/ubuntu/autotest/client/tmp/ubuntu_kvm_unit_tests/src/kvm-unit-tests/tests/svm' BUILD_HEAD=5251136b timeout -k 1s --foreground 90s /usr/bin/qemu-system-x86_64 --no-reboot -nodefaults -device pc-testdev -device isa-debug-exit,iobase=0xf4,iosize=0x4 -vnc none -serial stdio -device pci-testdev -machine accel=kvm -kernel /tmp/tmp.hBww2w4E5j -smp 2 -cpu max,+svm -m 4g -append -pause_filter_test # -initrd /tmp/tmp.oDwPB4oeYV enabling apic smp: waiting for 1 APs enabling apic setup: CPU 1 online paging enabled cr0 = 80010011 cr3 = 10bf000 cr4 = 20 NPT detected - running all tests with NPT enabled PASS: null PASS: vmrun PASS: ioio PASS: vmrun intercept check PASS: rsm PASS: cr3 read intercept PASS: cr3 read nointercept PASS: cr3 read intercept emulate PASS: dr intercept check PASS: next_rip PASS: msr intercept check PASS: mode_switch PASS: asid_zero PASS: sel_cr0_bug PASS: tsc_adjust Latency VMRUN : max: 3002660 min: 3340 avg: 5320 Latency VMEXIT: max: 2998700 min: 2240 avg: 2368 PASS: latency_run_exit Latency VMRUN : max: 2904480 min: 5040 avg: 5306 Latency VMEXIT: max: 2900400 min: 2240 avg: 2373 PASS: latency_run_exit_clean Latency VMLOAD: max: 1813380 min: 240 avg: 267 Latency VMSAVE: max: 1773120 min: 240 avg: 253 Latency STGI: max: 10700 min: 40 avg: 47 Latency CLGI: max: 1700260 min: 40 avg: 48 PASS: latency_svm_insn PASS: exception with vector 2 not injected PASS: divide overflow exception injected PASS: eventinj.VALID cleared PASS: exc_inject PASS: pending_event PASS: pending_event_cli PASS: direct interrupt while running guest PASS: intercepted interrupt while running guest PASS: direct interrupt + hlt PASS: intercepted interrupt + hlt PASS: interrupt PASS: direct NMI while running guest PASS: NMI intercept while running guest PASS: nmi PASS: direct NMI + hlt PASS: NMI intercept while running guest PASS: intercepted NMI + hlt PASS: nmi_hlt PASS: virq_inject PASS: No RIP corruption detected after 10000 timer interrupts PASS: reg_corruption enabling apic setup: CPU 1 online PASS: svm_init_startup_test PASS: host_rflags PASS: CPUID.01H:ECX.XSAVE set before VMRUN PASS: svm_cr4_osxsave_test_guest finished with VMMCALL PASS: CPUID.01H:ECX.XSAVE set after VMRUN PASS: EFER.SVME: 1500 PASS: EFER.SVME: 500 PASS: Test EFER 9:8: 1700 PASS: Test EFER 63:16: 11500 PASS: Test EFER 63:16: 101500 PASS: Test EFER 63:16: 1001500 PASS: Test EFER 63:16: 10001500 PASS: Test EFER 63:16: 100001500 PASS: Test EFER 63:16: 1000001500 PASS: Test EFER 63:16: 10000001500 PASS: Test EFER 63:16: 100000001500 PASS: Test EFER 63:16: 1000000001500 PASS: Test EFER 63:16: 10000000001500 PASS: Test EFER 63:16: 100000000001500 PASS: Test EFER 63:16: 1000000000001500 PASS: EFER.LME=1 (1500), CR0.PG=1 (80010011) and CR4.PAE=0 (40000) PASS: EFER.LME=1 (1500), CR0.PG=1 and CR0.PE=0 (80010010) PASS: EFER.LME=1 (1500), CR0.PG=1 (80010011), CR4.PAE=1 (40020), CS.L=1 and CS.D=1 (699) PASS: Test CR0 CD=1,NW=0: c0010011 PASS: Test CR0 CD=1,NW=1: e0010011 PASS: Test CR0 CD=0,NW=0: 80010011 PASS: Test CR0 CD=0,NW=1: a0010011 PASS: Test CR0 63:32: 180010011 PASS: Test CR0 63:32: 1080010011 PASS: Test CR0 63:32: 10080010011 PASS: Test CR0 63:32: 100080010011 PASS: Test CR0 63:32: 1000080010011 PASS: Test CR0 63:32: 10000080010011 PASS: Test CR0 63:32: 100000080010011 PASS: Test CR0 63:32: 1000000080010011 PASS: Test CR3 63:0: 100000010bf000, wanted exit 0xffffffff, got 0xffffffff PASS: Test CR3 63:0: 200000010bf000, wanted exit 0xffffffff, got 0xffffffff PASS: Test CR3 63:0: 400000010bf000, wanted exit 0xffffffff, got 0xffffffff PASS: Test CR3 63:0: 800000010bf000, wanted exit 0xffffffff, got 0xffffffff PASS: Test CR3 63:0: 1000000010bf000, wanted exit 0xffffffff, got 0xffffffff PASS: Test CR3 63:0: 2000000010bf000, wanted exit 0xffffffff, got 0xffffffff PASS: Test CR3 63:0: 4000000010bf000, wanted exit 0xffffffff, got 0xffffffff PASS: Test CR3 63:0: 8000000010bf000, wanted exit 0xffffffff, got 0xffffffff PASS: Test CR3 63:0: 10000000010bf000, wanted exit 0xffffffff, got 0xffffffff PASS: Test CR3 63:0: 20000000010bf000, wanted exit 0xffffffff, got 0xffffffff PASS: Test CR3 63:0: 40000000010bf000, wanted exit 0xffffffff, got 0xffffffff PASS: Test CR3 63:0: 80000000010bf000, wanted exit 0xffffffff, got 0xffffffff PASS: Test CR3 63:0: 10bf000 PASS: Test CR3 (PCIDE=1) 11:0: 10bf001, wanted exit 0x81, got 0x81 PASS: Test CR3 (PCIDE=1) 11:0: 10bf002, wanted exit 0x81, got 0x81 PASS: Test CR3 (PCIDE=1) 11:0: 10bf004, wanted exit 0x81, got 0x81 PASS: Test CR3 (PCIDE=1) 11:0: 10bf020, wanted exit 0x81, got 0x81 PASS: Test CR3 (PCIDE=1) 11:0: 10bf040, wanted exit 0x81, got 0x81 PASS: Test CR3 (PCIDE=1) 11:0: 10bf080, wanted exit 0x81, got 0x81 PASS: Test CR3 (PCIDE=1) 11:0: 10bf100, wanted exit 0x81, got 0x81 PASS: Test CR3 (PCIDE=1) 11:0: 10bf200, wanted exit 0x81, got 0x81 PASS: Test CR3 (PCIDE=1) 11:0: 10bf400, wanted exit 0x81, got 0x81 PASS: Test CR3 (PCIDE=1) 11:0: 10bf800, wanted exit 0x81, got 0x81 PASS: Test CR3 63:0: 10bf000 PASS: Test CR3 (PCIDE=0) 11:0: 10bf001, wanted exit 0x400, got 0x400 PASS: Test CR3 (PCIDE=0) 11:0: 10bf002, wanted exit 0x400, got 0x400 PASS: Test CR3 (PCIDE=0) 11:0: 10bf004, wanted exit 0x400, got 0x400 PASS: Test CR3 (PCIDE=0) 11:0: 10bf020, wanted exit 0x400, got 0x400 PASS: Test CR3 (PCIDE=0) 11:0: 10bf040, wanted exit 0x400, got 0x400 PASS: Test CR3 (PCIDE=0) 11:0: 10bf080, wanted exit 0x400, got 0x400 PASS: Test CR3 (PCIDE=0) 11:0: 10bf100, wanted exit 0x400, got 0x400 PASS: Test CR3 (PCIDE=0) 11:0: 10bf200, wanted exit 0x400, got 0x400 PASS: Test CR3 (PCIDE=0) 11:0: 10bf400, wanted exit 0x400, got 0x400 PASS: Test CR3 (PCIDE=0) 11:0: 10bf800, wanted exit 0x400, got 0x400 PASS: Test CR3 (PAE) 2:0: 10bf001, wanted exit 0x400, got 0x400 PASS: Test CR3 (PAE) 2:0: 10bf002, wanted exit 0x400, got 0x400 PASS: Test CR3 (PAE) 2:0: 10bf004, wanted exit 0x400, got 0x400 PASS: Test CR4 31:12: 42020, wanted exit 0xffffffff, got 0xffffffff PASS: Test CR4 31:12: 44020, wanted exit 0xffffffff, got 0xffffffff PASS: Test CR4 31:12: 48020, wanted exit 0xffffffff, got 0xffffffff PASS: Test CR4 31:12: c0020, wanted exit 0xffffffff, got 0xffffffff PASS: Test CR4 31:12: 1040020, wanted exit 0xffffffff, got 0xffffffff PASS: Test CR4 31:12: 2040020, wanted exit 0xffffffff, got 0xffffffff PASS: Test CR4 31:12: 4040020, wanted exit 0xffffffff, got 0xffffffff PASS: Test CR4 31:12: 8040020, wanted exit 0xffffffff, got 0xffffffff PASS: Test CR4 31:12: 10040020, wanted exit 0xffffffff, got 0xffffffff PASS: Test CR4 31:12: 20040020, wanted exit 0xffffffff, got 0xffffffff PASS: Test CR4 31:12: 40040020, wanted exit 0xffffffff, got 0xffffffff PASS: Test CR4 31:12: 80040020, wanted exit 0xffffffff, got 0xffffffff PASS: Test CR4 31:12: 42020, wanted exit 0xffffffff, got 0xffffffff PASS: Test CR4 31:12: 44020, wanted exit 0xffffffff, got 0xffffffff PASS: Test CR4 31:12: 48020, wanted exit 0xffffffff, got 0xffffffff PASS: Test CR4 31:12: c0020, wanted exit 0xffffffff, got 0xffffffff PASS: Test CR4 31:12: 1040020, wanted exit 0xffffffff, got 0xffffffff PASS: Test CR4 31:12: 2040020, wanted exit 0xffffffff, got 0xffffffff PASS: Test CR4 31:12: 4040020, wanted exit 0xffffffff, got 0xffffffff PASS: Test CR4 31:12: 8040020, wanted exit 0xffffffff, got 0xffffffff PASS: Test CR4 31:12: 10040020, wanted exit 0xffffffff, got 0xffffffff PASS: Test CR4 31:12: 20040020, wanted exit 0xffffffff, got 0xffffffff PASS: Test CR4 31:12: 40040020, wanted exit 0xffffffff, got 0xffffffff PASS: Test CR4 31:12: 80040020, wanted exit 0xffffffff, got 0xffffffff PASS: Test CR4 63:32: 100040020, wanted exit 0xffffffff, got 0xffffffff PASS: Test CR4 63:32: 1000040020, wanted exit 0xffffffff, got 0xffffffff PASS: Test CR4 63:32: 10000040020, wanted exit 0xffffffff, got 0xffffffff PASS: Test CR4 63:32: 100000040020, wanted exit 0xffffffff, got 0xffffffff PASS: Test CR4 63:32: 1000000040020, wanted exit 0xffffffff, got 0xffffffff PASS: Test CR4 63:32: 10000000040020, wanted exit 0xffffffff, got 0xffffffff PASS: Test CR4 63:32: 100000000040020, wanted exit 0xffffffff, got 0xffffffff PASS: Test CR4 63:32: 1000000000040020, wanted exit 0xffffffff, got 0xffffffff PASS: Test DR6 63:32: 1ffff0ff0 PASS: Test DR6 63:32: 10ffff0ff0 PASS: Test DR6 63:32: 100ffff0ff0 PASS: Test DR6 63:32: 1000ffff0ff0 PASS: Test DR6 63:32: 10000ffff0ff0 PASS: Test DR6 63:32: 100000ffff0ff0 PASS: Test DR6 63:32: 1000000ffff0ff0 PASS: Test DR6 63:32: 10000000ffff0ff0 PASS: Test DR7 63:32: 100000400 PASS: Test DR7 63:32: 1000000400 PASS: Test DR7 63:32: 10000000400 PASS: Test DR7 63:32: 100000000400 PASS: Test DR7 63:32: 1000000000400 PASS: Test DR7 63:32: 10000000000400 PASS: Test DR7 63:32: 100000000000400 PASS: Test DR7 63:32: 1000000000000400 PASS: Test MSRPM address: ffffffffe000 PASS: Test MSRPM address: ffffffffe001 PASS: Test MSRPM address: fffffffff000 PASS: Test MSRPM address: 430000 PASS: Test MSRPM address: 430fff PASS: Test IOPM address: ffffffffc000 PASS: Test IOPM address: ffffffffd000 PASS: Test IOPM address: ffffffffdffe PASS: Test IOPM address: ffffffffe000 PASS: Test IOPM address: fffffffff000 PASS: Test IOPM address: 433000 PASS: Test IOPM address: 433fff PASS: Test FS.base for canonical form: 0 PASS: Test GS.base for canonical form: 534b40 PASS: Test LDTR.base for canonical form: 0 PASS: Test TR.base for canonical form: 53cba0 PASS: Test KERNEL GS.base for canonical form: 0 PASS: Successful VMRUN with noncanonical ES.base PASS: Successful VMRUN with noncanonical CS.base PASS: Successful VMRUN with noncanonical SS.base PASS: Successful VMRUN with noncanonical DS.base PASS: Successful VMRUN with noncanonical GDTR.base PASS: Successful VMRUN with noncanonical IDTR.base PASS: All guest memory tested, no bug found PASS: Test VMLOAD/VMSAVE intercept: Expected VMMCALL #VMEXIT PASS: Test VMLOAD/VMSAVE intercept: Expected VMLOAD #VMEXIT PASS: Test VMLOAD/VMSAVE intercept: Expected VMSAVE #VMEXIT PASS: Test VMLOAD/VMSAVE intercept: Expected VMMCALL #VMEXIT PASS: Test VMLOAD/VMSAVE intercept: Expected VMLOAD #VMEXIT PASS: Test VMLOAD/VMSAVE intercept: Expected VMMCALL #VMEXIT PASS: Test VMLOAD/VMSAVE intercept: Expected VMSAVE #VMEXIT PASS: Test VMLOAD/VMSAVE intercept: Expected VMMCALL #VMEXIT PASS: Test EFLAGS.TF on VMRUN: trap expected after completion of first guest instruction PASS: Test EFLAGS.TF on VMRUN: trap not expected PASS: Test EFLAGS.TF on VMRUN: guest execution completion PASS: fnop with CR0.TS set in L2, #NM is triggered PASS: fnop with CR0.EM set in L2, #NM is triggered PASS: fnop with CR0.TS and CR0.EM unset no #NM excpetion PASS: #BP is handled in L2 exception handler PASS: #OF is generated in L2 exception handler PASS: Basic LBR test FAIL: MSR_IA32_LASTBRANCHFROMIP, expected=0x4021ca, actual=0x4021ca PASS: Test that without LBRV enabled, guest LBR state does 'leak' to the host(1) Unhandled exception 6 #UD at ip 000000000040174a error_code=0000 rflags=00010097 cs=00000008 rax=0000000000000000 rcx=00000000000001d9 rdx=0000000000000000 rbx=0000000000414920 rbp=000000000042fa38 rsi=0000000000000003 rdi=0000000000414d98 r8=00000000004176f9 r9=00000000000003f8 r10=000000000000000d r11=0000000000000000 r12=0000000000000000 r13=0000000000000000 r14=0000000000000000 r15=0000000000000000 cr0=0000000080010011 cr2=0000000000000000 cr3=00000000010bf000 cr4=0000000000040020 cr8=0000000000000000 STACK: @40174a 414e48 414e48 414e48 414e48 414e48 414e48 414e48 414e48 414e48 414e48 414e48 414e48 414e48 414e48 414e48 414e48 414e48 414e48 414e48 FAIL svm