AArch64 EXT instruction for V register does not clear MSB side bits
Bug #1863247 reported by
Kentaro Kawakami
This bug affects 1 person
Affects | Status | Importance | Assigned to | Milestone | |
---|---|---|---|---|---|
QEMU |
Fix Released
|
Undecided
|
Richard Henderson |
Bug Description
On AArch64 CPU with SVE register, there seems to be a bug in the operation when executing EXT instruction to V registers. Bits above the 128 bits of the SVE register must be cleared to 0, but qemu-aarch64 seems to hold the value.
Example
ext v0.16b, v1.16b v2.16b, 8
After executing above instruction, (N-1) to 128 bits of z0 register must be 0, where N is SVE register width.
Changed in qemu: | |
status: | Fix Committed → Fix Released |
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Yep.