Comment 4 for bug 1836078

In the ieee6 test case it is attempting to write OFE, bit [10] which:

    This bit is RW only if the implementation supports the trapping of floating-point exceptions. In an implementation that does not support floating-point exception trapping, this bit is RAZ/WI.

    When this bit is RW, it applies only to floating-point operations. Advanced SIMD operations always use untrapped floating-point exception handling in AArch32 state

This might be a broken test.