target-mips/dsp_helper.c: two possible bad shifts

[dcb]

target-mips/dsp_helper.c:3480:1: error: V629 Consider inspecting the '0x01 << (size + 1)' expression. Bit shifting of the 32-bit value with a subsequent expansion to the 64-bit type.

Source code is

        temp = temp & ((0x01 << (size + 1)) - 1);

If size >= 32, then better code might be

        temp = temp & ((0x01UL << (size + 1)) - 1);

target-mips/dsp_helper.c:3509:1: error: V629 Consider inspecting the '0x01 << (size + 1)' expression. Bit shifting of the 32-bit value with a subsequent expansion to the 64-bit type.

Duplicate

[Thomas Huth (th-huth)]

Fix has been committed:
http://git.qemu.org/?p=qemu.git;a=commitdiff;h=e6e2784cacd4cfec149

[Thomas Huth (th-huth)]

Released with version 2.8