EDIF netlists lose first two chars of net names
Affects | Status | Importance | Assigned to | Milestone | |
---|---|---|---|---|---|
pcb |
New
|
Undecided
|
Unassigned |
Bug Description
When loading a netlist in EDIF format, then saving the PCB file, the first two characters are lost from every net name. Initially after loading the netlist, the net names look correct in the netlist window, but the characters are lost at save and will remain lost when loading the PCB file in the future.
This is a problem because it creates ambiguous net names and loses information. For example, the nets "GND" and "VDD" both become "D".
Versions affected: 20110908, 20100929, 20091103, maybe more
Steps to recreate:
1. Start PCB.
2. Load an EDIF netlist (see attached "EDIF_import_
3. Open the netlist window and see that the nets have the correct names ("VDD" and "GND" for the example)
4. Save the .pcb file.
5. Inspect the contents of the .pcb file saved in step 4 and see that both nets are now named "D".
6. (optional) "Revert", go to the netlist window, and see that both nets are now named "D".
Cause of the bug:
Net names are stored internally prefixed with two characters that indicate status information (two spaces by default). The EDIF netlist importer does not prepend these spaces. When the PCB is saved, these two status characters are dropped. This causes the first two characters of EDIF net names to be lost.
Fix:
The EDIF importer needs to prepend the two blanks. A patch is enclosed.
Changed in geda-project: | |
importance: | Undecided → High |