Gap around trace in filled polygon disappears when copied
The clearance around a trace which is inside a copper filled polygon sometimes disappears when the trace and polygon are copied. The problem does not seem to be repeatable on-demand, but may crop up when panelizing a board that routes a few traces on its ground plane. It is observable in the GUI display and in rendered Gerber files, as the solid polygon with the ends of the trace poking through the via clearances. Only the copy seems to have the problem ; the original is fine.
I have had this happen twice. In at least one case, saving and reloading the .pcb file made the problem go away. I do not believe the design rule checker or optimize rats nest functions were able to diagnose the problem.
Observed in the Fedora 12 pcb-0.20091103-