DRC "minspace between pad and polygon" not triggerd!
Bug #699245 reported by
ferch
This bug affects 2 people
Affects | Status | Importance | Assigned to | Milestone | |
---|---|---|---|---|---|
pcb |
Fix Released
|
Medium
|
Chad Parker |
Bug Description
Look at the attached picture. A package SO8 and a line, surrounded by a polygon. You can see, that i have defined a minspace of 6.3 mil.
The space between pad and polygon is less than 5mil. (Defined in the SO8-package)
This should raise a DRC-error, but i get a "No DRC problems found".
Workaround: Select all pads at the pcb and execute:
ChangeClearSize
PS:
Look also ID #1843179 (DRC misses odd trace/poly clearance error).
I use the cvs-version updateted today (10. Feb 2007).
Changed in geda-project: | |
importance: | Undecided → Medium |
Changed in pcb: | |
status: | New → Confirmed |
Changed in pcb: | |
status: | In Progress → Fix Committed |
Changed in pcb: | |
status: | Fix Committed → Fix Released |
Changed in geda-project: | |
status: | New → Fix Released |
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A mistake in the date. I updated on 10. Feb **2008**.
And "ChangeClearSize" as workaround for the whole pcb is not really a good idea, because resistors and some other elements should have a clearance greater than 7mil.