pcb

DRC "minspace between pad and polygon" not triggerd!

Bug #699245 reported by ferch on 2008-02-10
14
This bug affects 2 people
Affects Status Importance Assigned to Milestone
gEDA project
Medium
Unassigned
pcb
Medium
Unassigned

Bug Description

Look at the attached picture. A package SO8 and a line, surrounded by a polygon. You can see, that i have defined a minspace of 6.3 mil.
The space between pad and polygon is less than 5mil. (Defined in the SO8-package)

This should raise a DRC-error, but i get a "No DRC problems found".

Workaround: Select all pads at the pcb and execute:
ChangeClearSize(SelectedPads, 7, mil)

PS:
Look also ID #1843179 (DRC misses odd trace/poly clearance error).

I use the cvs-version updateted today (10. Feb 2007).

ferch (ferch) wrote :
ferch (ferch) wrote :

A mistake in the date. I updated on 10. Feb **2008**.
And "ChangeClearSize" as workaround for the whole pcb is not really a good idea, because resistors and some other elements should have a clearance greater than 7mil.

DJ Delorie (djdelorie) wrote :

It gives a message for me, but I might have a slightly different board than you do. Could you update from cvs again to make sure it's still broken, and attach a *.pcb board to this tracker if it is?

ferch (ferch) wrote :

Yes, the bug is still there. Do I have to take care on cvs update? I use "cvs up", "make", "make install".
The about-dialog:
...
version 1.99w
Compiled on Dec 28 2008 at 22:17:17
...

ferch (ferch) wrote :
Traumflug (mah-jump-ing) on 2015-09-27
Changed in geda-project:
importance: Undecided → Medium

Object report say clearance width in polygons 5.00 mil.

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