DRC "minspace between pad and polygon" not triggerd!

[ferch]

Look at the attached picture. A package SO8 and a line, surrounded by a polygon. You can see, that i have defined a minspace of 6.3 mil.
The space between pad and polygon is less than 5mil. (Defined in the SO8-package)

This should raise a DRC-error, but i get a "No DRC problems found".

Workaround: Select all pads at the pcb and execute:
ChangeClearSize(SelectedPads, 7, mil)

PS:
Look also ID #1843179 (DRC misses odd trace/poly clearance error).

I use the cvs-version updateted today (10. Feb 2007).

[ferch (ferch)]

A mistake in the date. I updated on 10. Feb **2008**.
And "ChangeClearSize" as workaround for the whole pcb is not really a good idea, because resistors and some other elements should have a clearance greater than 7mil.

[DJ Delorie (djdelorie)]

It gives a message for me, but I might have a slightly different board than you do. Could you update from cvs again to make sure it's still broken, and attach a *.pcb board to this tracker if it is?

[ferch (ferch)]

Yes, the bug is still there. Do I have to take care on cvs update? I use "cvs up", "make", "make install".
The about-dialog:
...
version 1.99w
Compiled on Dec 28 2008 at 22:17:17
...

[Nicklas Karlsson (nicklas-karlsson17)]

Object report say clearance width in polygons 5.00 mil.

[Chad Parker (parker-charles)]

The DRC still has this issue in pcb-4.1.3. For some reason, those pads are either not being tested, or the test is returning improperly.

[Chad Parker (parker-charles)]

The issue is in drc_callback. For some reason, after testing the clearance of the pad, it calls IsPadInPolygon. This will only return true if the pad is actually touching the copper of the polygon.

This extra test was introduced by DJ in commit bc48a574, in 2007. The log suggests that it somehow fixes the DRC for slanted pads. However, I don't see any issues with slanted pads.

I've fixed this at the head of branch home/cparker/drc_updates.