DRC misses odd trace/poly clearance error
Bug #699234 reported by
Ben Jackson
This bug affects 2 people
Affects | Status | Importance | Assigned to | Milestone | |
---|---|---|---|---|---|
pcb |
Fix Released
|
High
|
Chad Parker |
Bug Description
The attached PCB is distilled from one I sent to Sierra Proto Express. Their DRC caught the problem. You can see I used 3 fat wires and 3 vias to tie a cap SMT pad to ground. The cap is inside a small poly on the surface. The lines themselves are not clearing the poly, but they don't touch because of the combination of the pad and via clearances overlapping. The actual gap (if you measure it) is only 4mil, though, smaller than the 6/6 rules.
Changed in pcb: | |
importance: | Undecided → High |
status: | New → Confirmed |
Changed in geda-project: | |
importance: | Undecided → High |
status: | New → Confirmed |
tags: | added: drc |
Changed in pcb: | |
status: | Confirmed → In Progress |
milestone: | none → pcb-4.2.0 |
Changed in pcb: | |
milestone: | pcb-4.2.0 → pcb-4.1.3 |
Changed in pcb: | |
milestone: | pcb-4.1.3 → future-bug-fix-release |
Changed in pcb: | |
milestone: | future-bug-fix-release → pcb-4.2.0 |
Changed in pcb: | |
status: | In Progress → Fix Committed |
Changed in pcb: | |
status: | Fix Committed → Fix Released |
Changed in geda-project: | |
status: | Confirmed → Fix Released |
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Interestingly, I was able to pull the via a little more away from the pad so that the polygon copper still does not actually make contact to the track. But the DRC then detected the problem.
---<)kaimartin(>---