pcb

DRC misses odd trace/poly clearance error

Bug #699234 reported by Ben Jackson on 2007-12-03
6
This bug affects 1 person
Affects Status Importance Assigned to Milestone
gEDA project
High
Unassigned
pcb
High
Unassigned

Bug Description

The attached PCB is distilled from one I sent to Sierra Proto Express. Their DRC caught the problem. You can see I used 3 fat wires and 3 vias to tie a cap SMT pad to ground. The cap is inside a small poly on the surface. The lines themselves are not clearing the poly, but they don't touch because of the combination of the pad and via clearances overlapping. The actual gap (if you measure it) is only 4mil, though, smaller than the 6/6 rules.

Ben Jackson (ben.jackson) wrote :
Traumflug (mah-jump-ing) on 2015-09-06
Changed in pcb:
importance: Undecided → High
status: New → Confirmed
Traumflug (mah-jump-ing) on 2015-09-27
Changed in geda-project:
importance: Undecided → High
status: New → Confirmed
KaiMartin (kmk-familieknaak) wrote :

Interestingly, I was able to pull the via a little more away from the pad so that the polygon copper still does not actually make contact to the track. But the DRC then detected the problem.

---<)kaimartin(>---

I opened the attached file and if via is moved lines join polygon. If I press the "J" button "Change Join Object" clearance seems to work correct although I do not know the exact clearance value for the line.

tags: added: drc
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