merely overlapping vias with pads produces DRC error?
Affects | Status | Importance | Assigned to | Milestone | |
---|---|---|---|---|---|
pcb |
Won't Fix
|
Undecided
|
Unassigned |
Bug Description
I have some vias going to power planes. I've got a cap that is so close that it overlaps (the hole is not on the pad, but the annular ring is solidly on the pad).
DRC doesn't complain until I update the ratsnest, which figures out there is a connection. Then the DRC goes nuts:
Rules are minspace 6.01, minoverlap 5.0 minwidth 6.00, minsilk 5.00
min drill 15.00, min annular ring 5.00
WARNING!! Design Rule Error - potential for broken trace!
near location (8688.46,5050.00)
WARNING! Design Rule error - copper areas too close!
WARNING!! Design Rule Error - potential for broken trace!
near location (8621.54,5050.00)
WARNING! Design Rule error - copper areas too close!
WARNING!! Design Rule Error - potential for broken trace!
near location (8690.00,5020.00)
WARNING! Design Rule error - copper areas too close!
near location (8690.00,5020.00)
WARNING!! Design Rule Error - potential for broken trace!
near location (8620.00,5020.00)
WARNING! Design Rule error - copper areas too close!
near location (8620.00,5020.00)
Found 8 design rule errors.
that's for one cap/via setup. If I draw 8mil traces from the vias to the pads (which do not produce any additional copper, and are, in fact, narrower than the neck of the overlap that's there) the DRC is clean again.
Could you try this with minoverlap == 0.01 ?