pcb

Large Pads (150 mils) silently dropped

Bug #699152 reported by whitis on 2007-03-25
6
This bug affects 1 person
Affects Status Importance Assigned to Milestone
gEDA project
Medium
Unassigned
pcb
Medium
Unassigned

Bug Description

Vias over 150 mils pad diameter (inclusive) are silently dropped.

pcb-20070208p1

Pin 14 below is not drawn and not saved. Pin 13 is because I lowered its pad diameter to 149 mils.

Via[49500 67500 7500 2000 0 5100 "1" ""]
Via[44500 77500 7500 2000 0 5100 "2" ""]
Via[39500 67500 7500 2000 0 5100 "3" ""]
Via[34500 77500 7500 2000 0 5100 "4" ""]
Via[29500 67500 7500 2000 0 5100 "5" ""]
Via[24500 77500 7500 2000 0 5100 "6" ""]
Via[19500 67500 7500 2000 0 5100 "7" ""]
Via[14500 77500 7500 2000 0 5100 "8" ""]
Via[56900 23200 7500 2000 0 5100 "9" ""]
Via[46900 29200 7500 2000 0 5100 "10" ""]
Via[17100 23200 7500 2000 0 5100 "11" ""]
Via[7100 29200 7500 2000 0 5100 "12" ""]
Via[9500 42500 14500 2000 0 12500 "" ""]
Via[54500 42500 14500 2000 0 12500 "" ""]
Via[1000 54500 14900 2000 0 8300 "13" ""]
Via[63000 54500 15000 2000 0 8300 "14" ""]

Layer(10 "silk")
(
 Line[0 0 64000 0 1000 2000 "clearline"]
 Line[64000 0 64000 85000 1000 2000 "clearline"]
 Line[64000 85000 0 85000 1000 2000 "clearline"]
 Line[0 85000 0 0 1000 2000 "clearline"]
)

This is from a footprint definition. Everything that isn't part of the footprint (header, fonts, etc) has been edited out.

Ineiev (ineiev) wrote :

Vias can not overlap, as you mention in your next bug report.

More clear example based on your is

Via[11500 12500 14500 2000 0 12500 "13" ""]
Via[14000 24500 15000 2000 0 8300 "17" ""]
Via[9000 27050 15000 2000 0 8300 "19" ""]
Via[23000 12500 10000 2000 0 9000 "11" ""]
Via[24000 12500 10000 2000 0 9000 "23" ""]

First comes 13, it forbids 17 and 23, but admits 19 as well as 11.

If you want the holes to overlap, you can remove from pcb/src/create.c
(CVS version for Apr 01 2007) these lines:

230a231,238
> VIA_LOOP (Data);
> {
> if (SQUARE (via->X - X) + SQUARE (via->Y - Y) <=
> SQUARE (via->Thickness / 2 + Thickness / 2))
> return (NULL); /* don't allow via stacking */
> }
> END_LOOP;
>

Maybe this code should be replaced with something like this:

   VIA_LOOP (Data);
   {
     if (SQUARE (via->X - X) + SQUARE (via->Y - Y) <=
       SQUARE (via->Thickness / 2 - Thickness / 2))
       return (NULL); /* don't allow via stacking */
   }
   END_LOOP;

That is, no via should sink in another.

Regards,

danmc (danmc) wrote :

this has come up somewhere else too. Perhaps the real bug is you can create this by resizing a via but then when the file is loaded the next time (causing the via to be created) it is dropped due to the code you point out here. I'm thinking what should really happen is that you get a DRC violation or at an absolute minimum, a warning. I just added a warning when this happens but thats not what I want for a longer term solution.

I think the proposed code change isn't quite right. You need to look at drill sizes to see if a via will get chopped by another vias drill hole. But as I said, a better fix is to allow anything but give a DRC warning.

Ineiev (ineiev) wrote :

You are right. vias are more complicated objects than
I think.

Maybe overlapping vias do not need even
warning, the same as when PCB does not warn about
merged lines. if someone does not like such
things, they can purify the board manually
using thin-line mode.

Peter Clifton (pcjc2) on 2011-01-14
tags: added: core
Peter Clifton (pcjc2) wrote :

It would be worth verifying if this is still a problem with current PCB versions...

Bert Timmerman (bert-timmerman) wrote :

Hi,
I just copy-pasted some of the vias from above in to an empty pcb file, updated the file format, saved, and reloaded in pcb (current git HEAD).
Vias now overlap and all (7) vias show up, some on top of each other.
This has changed since pcb version 20100929 which is my current installed version (on an updated FC13 distro).
 Hopes this gives some insight and clues how to proceed.
Kind regards, Bert Timmerman.

Bert Timmerman (bert-timmerman) wrote :

Hi,
Silly me ;-) I forgot about the recent pcb file format update.
Not all vias show up when opening the attached test file (only vias "A" and "17").
Kind regards, Bert Timmerman.

Traumflug (mah-jump-ing) on 2015-09-27
Changed in geda-project:
importance: Undecided → Medium
Bert Timmerman (bert-timmerman) wrote :

Hi,

In current pcb HEAD (eb2b00f5419cd69ce90d9d1aeda218627beeafac) it is still possible to load vias with overlapping drill holes.

No warnings in the log window either.

AFAICT, no vias are dropped.

Kind regards,

Bert Timmerman.

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