Large Pads (150 mils) silently dropped
Affects | Status | Importance | Assigned to | Milestone | |
---|---|---|---|---|---|
pcb |
New
|
Medium
|
Unassigned |
Bug Description
Vias over 150 mils pad diameter (inclusive) are silently dropped.
pcb-20070208p1
Pin 14 below is not drawn and not saved. Pin 13 is because I lowered its pad diameter to 149 mils.
Via[49500 67500 7500 2000 0 5100 "1" ""]
Via[44500 77500 7500 2000 0 5100 "2" ""]
Via[39500 67500 7500 2000 0 5100 "3" ""]
Via[34500 77500 7500 2000 0 5100 "4" ""]
Via[29500 67500 7500 2000 0 5100 "5" ""]
Via[24500 77500 7500 2000 0 5100 "6" ""]
Via[19500 67500 7500 2000 0 5100 "7" ""]
Via[14500 77500 7500 2000 0 5100 "8" ""]
Via[56900 23200 7500 2000 0 5100 "9" ""]
Via[46900 29200 7500 2000 0 5100 "10" ""]
Via[17100 23200 7500 2000 0 5100 "11" ""]
Via[7100 29200 7500 2000 0 5100 "12" ""]
Via[9500 42500 14500 2000 0 12500 "" ""]
Via[54500 42500 14500 2000 0 12500 "" ""]
Via[1000 54500 14900 2000 0 8300 "13" ""]
Via[63000 54500 15000 2000 0 8300 "14" ""]
Layer(10 "silk")
(
Line[0 0 64000 0 1000 2000 "clearline"]
Line[64000 0 64000 85000 1000 2000 "clearline"]
Line[64000 85000 0 85000 1000 2000 "clearline"]
Line[0 85000 0 0 1000 2000 "clearline"]
)
This is from a footprint definition. Everything that isn't part of the footprint (header, fonts, etc) has been edited out.
tags: | added: core |
Changed in geda-project: | |
importance: | Undecided → Medium |
Vias can not overlap, as you mention in your next bug report.
More clear example based on your is
Via[11500 12500 14500 2000 0 12500 "13" ""]
Via[14000 24500 15000 2000 0 8300 "17" ""]
Via[9000 27050 15000 2000 0 8300 "19" ""]
Via[23000 12500 10000 2000 0 9000 "11" ""]
Via[24000 12500 10000 2000 0 9000 "23" ""]
First comes 13, it forbids 17 and 23, but admits 19 as well as 11.
If you want the holes to overlap, you can remove from pcb/src/create.c
(CVS version for Apr 01 2007) these lines:
230a231,238
> VIA_LOOP (Data);
> {
> if (SQUARE (via->X - X) + SQUARE (via->Y - Y) <=
> SQUARE (via->Thickness / 2 + Thickness / 2))
> return (NULL); /* don't allow via stacking */
> }
> END_LOOP;
>
Maybe this code should be replaced with something like this:
VIA_LOOP (Data);
{
if (SQUARE (via->X - X) + SQUARE (via->Y - Y) <=
SQUARE (via->Thickness / 2 - Thickness / 2))
return (NULL); /* don't allow via stacking */
}
END_LOOP;
That is, no via should sink in another.
Regards,