| 2019-09-12 20:43:31 |
Joseph Coffland |
bug |
|
|
added bug |
| 2019-09-12 20:43:31 |
Joseph Coffland |
attachment added |
|
drc_pad_clearance_problem.pcb https://bugs.launchpad.net/bugs/1843834/+attachment/5288396/+files/drc_pad_clearance_problem.pcb |
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| 2019-09-12 20:44:55 |
Joseph Coffland |
description |
As of version 4.2.0 my PCB layout has 176 new DRC errors. I have many pads which are connected to polys by setting the pad clearance to zero. The DRC previously ignored theses. I understand that this looks like a legitimate clearance violation but there is no way, as far as I can tell, to tell PCB that the connection from the pad to the poly is intentional. A flag on the pad indicating that it should be connected such as "pininpoly" would be ideal.
The "clearline" flag on lines is related. If there were a "noclear" flag for pads, I could add this to all the pads that were intentionally connected to the poly. Ideally, "noclear" would both prevent the DRC from calling the connection an error *and* cause the poly router to ignore the pad clearance setting.
This is fairly easy to reproduce.
1. Start a new project
2. Add a poly rectangle on the top layer.
3. Add a component that has a pad.
4. Set the clearance of a pad to zero (Shift-K).
5. Run the DRC.
See attached file. |
As of version 4.2.0 my PCB layout has 176 new DRC errors. I have many pads which are connected to polys by setting the pad clearance to zero. The DRC previously ignored theses. I understand that this looks like a legitimate clearance violation but there is no way, as far as I can tell, to tell PCB that the connection from the pad to the poly is intentional. A flag on the pad indicating that it should be connected would be ideal.
The "clearline" flag on lines is related. If there were a "noclear" flag for pads, I could add this to all the pads that were intentionally connected to polys. Ideally, "noclear" would both prevent the DRC from calling the connection an error *and* cause the poly router to ignore the pad clearance setting.
This is fairly easy to reproduce.
1. Start a new project
2. Add a poly rectangle on the top layer.
3. Add a component that has a pad.
4. Set the clearance of a pad to zero (Shift-K).
5. Run the DRC.
See attached file. |
|
| 2019-09-12 20:53:05 |
Joseph Coffland |
description |
As of version 4.2.0 my PCB layout has 176 new DRC errors. I have many pads which are connected to polys by setting the pad clearance to zero. The DRC previously ignored theses. I understand that this looks like a legitimate clearance violation but there is no way, as far as I can tell, to tell PCB that the connection from the pad to the poly is intentional. A flag on the pad indicating that it should be connected would be ideal.
The "clearline" flag on lines is related. If there were a "noclear" flag for pads, I could add this to all the pads that were intentionally connected to polys. Ideally, "noclear" would both prevent the DRC from calling the connection an error *and* cause the poly router to ignore the pad clearance setting.
This is fairly easy to reproduce.
1. Start a new project
2. Add a poly rectangle on the top layer.
3. Add a component that has a pad.
4. Set the clearance of a pad to zero (Shift-K).
5. Run the DRC.
See attached file. |
As of version 4.2.0 my PCB layout has 176 new DRC errors. I have many pads which are connected to polys by setting the pad clearance to zero. The DRC previously ignored theses. I understand that this looks like a legitimate clearance violation but there is no way, as far as I can tell, to tell PCB that the connection from the pad to the poly is intentional.
I believe the DRC should just ignore zero-clearance pads as it did in previous versions. If the resulting connections were errors, they would be detected as such anyway because they would violate the netlist.
An alternative but less ideal solution would be to add a flag, say "noclear", that could be added to the pad to indicate connection to the poly was intentional.
This is fairly easy to reproduce.
1. Start a new project
2. Add a poly rectangle on the top layer.
3. Add a component that has a pad.
4. Set the clearance of a pad to zero (Shift-K).
5. Run the DRC.
See attached file. |
|
| 2020-05-31 15:23:04 |
Bert Timmerman |
pcb: status |
New |
Confirmed |
|
| 2020-09-20 19:59:50 |
Bert Timmerman |
pcb: milestone |
|
future-bug-fix-release |
|
