Photo-mode png export not export for non-standard board outline

[Yu - Sian , Liu]

With master version 4584cc3aaff6f88e25e8d343d99b2d2e7627b4db
the following command generate the blank png file. It may due to non-standard board outline.

./src/pcb -x png --outfile top.png --dpi 1000 --use-alpha --format PNG --photo-mode ./outline.pcb

The outline layout of the board
Layer(7 "outline" "outline")
(
 Line[0.0000 700.00mil 300.00mil 700.00mil 10.00mil 20.00mil "clearline"]
 Line[500.00mil 500.00mil 1600.00mil 500.00mil 10.00mil 20.00mil "clearline"]
 Line[1600.00mil 500.00mil 1800.00mil 700.00mil 10.00mil 20.00mil "clearline"]
 Line[1800.00mil 700.00mil 2100.00mil 700.00mil 10.00mil 20.00mil "clearline"]
 Line[0.0000 100.00mil 300.00mil 100.00mil 10.00mil 20.00mil "clearline,selected"]
 Line[300.00mil 100.00mil 400.00mil 0.0000 10.00mil 20.00mil "clearline"]
 Line[0.0000 100.00mil 0.0000 700.00mil 10.00mil 20.00mil "clearline"]
 Line[400.00mil 0.0000 1700.00mil 0.0000 10.00mil 20.00mil "clearline"]
 Line[1700.00mil 0.0000 1800.00mil 100.00mil 10.00mil 20.00mil "clearline"]
 Line[1800.00mil 100.00mil 2100.00mil 100.00mil 10.00mil 20.00mil "clearline"]
 Line[2100.00mil 100.00mil 2100.00mil 700.00mil 10.00mil 20.00mil "clearline"]
 Line[300.00mil 700.00mil 500.00mil 500.00mil 10.00mil 20.00mil "clearline"]
)

[DJ Delorie (djdelorie)]

The problem is that the flood fill that fills the "outside" messes up when the outline touches the edge of the workspace - it ends up flood filling the inside as well. If you grow the workspace a bit and move the board away from the edge, it should work OK.

[Yu - Sian , Liu (thomasysliu)]

Confirmed. If I grow both right and bottom side of the workspace by 100 mil it work fine.

[Bert Timmerman (bert-timmerman)]

Hi Liu Yu - Sian,

Do you want to keep this bug report and have pcb-developers take action on this, and if so, what action do you propose pcb-developers to take ?

If no further action is needed please close the bug with "won't fix" or reply to this bug report.

Kind regards,

Bert Timmerman.

[Yu - Sian , Liu (thomasysliu)]

Hi Bert,
I would like to keep this bug report.
I think pcb-developers can enlarge the workspace for flood filling and find the correct outline.