pcb

Add per-layer flags.

Bug #1493557 reported by Traumflug on 2015-09-08
6
This bug affects 1 person
Affects Status Importance Assigned to Milestone
gEDA project
Medium
Unassigned
pcb
Medium
Unassigned

Bug Description

After being half done with a fix for https://bugs.launchpad.net/pcb/+bug/1492966, DJ came up with another plan.

My idea was to split the layer stack (PCB->Data->Layer[]) not into two (non-silk layers and two silk layers), but into three sections: copper layers, non-copper layers and silk layers. This way the various sections of code can iterate _unconditionally_ over the appropriate sections of the stack. For example, finding connection would no longer be done on all but the silk layers, but only on the copper layers by simply adjusting the range of the iteration. This plan works without any file format change, older files just need to be sorted at load time. Code is on the LP1492966 branch: http://git.geda-project.org/pcb/log/?h=LP1492966

DJ's idea is to give up relying on any order on this stack at all. Instead, each layer should get a flag which describes his properties. Code messing with tracks, conductivity or whatever would iterate over the entire stack, then, but also check flags wether each layer has appropriate properties. For example, searching connections would take only tracks into account which are on a layer with the property "copper". This requires these properties to be saved inside the layout file. Luckily, this was taken care of a long time ago already, this line in parse_y.y does it:

    : T_LAYER '(' INTEGER STRING opt_string ')' '('

DJ did some work already, in form of a patch: http://www.delorie.com/pcb/pcb-layertypes.patch

Traumflug (mah-jump-ing) wrote :

Fine. DJs code builds now. I've tested the outcome and also refined the code a bit, e.g. to make sure there's only one outline layer.

The results are surprisingly good. When loading existing layouts, all relevant properties are detected properly. Regression tests continue to work fine, so old code and new code can coexist side by side.

The only thing I'm not sure about is wether it's a wise move to add a "side" property to each layer. Some layers, e.g. the outline layer, have no "side". For all others, the side is defined by the group they belong to. I think this part of the patch should be removed before it gets used elsewhere in the code.

Branch LP1493557 updated: http://git.geda-project.org/pcb/log/?h=LP1493557

Traumflug (mah-jump-ing) wrote :

After having another talk to DJ I came to the conclusion that layers shouldn't have a 'side'. At least not as long as groups are considered to be authoritative about which side (or inner layer) a specific layer lies on. So I reverted this part of the patch, along with an extensive explanation in the commit message.

Branch LP1493557 updated again: http://git.geda-project.org/pcb/log/?h=LP1493557

As far as I can see, layer types work fine now (on this branch). Next steps would include to replace the currently used various voodoo heuristics' all over the place for finding the layer type by a simple read of the now existing flag. Probably no longer part of this bug.

Changed in pcb:
importance: Undecided → Medium
status: New → In Progress
Traumflug (mah-jump-ing) wrote :

Code written, forwarded to master :-)

Changed in pcb:
status: In Progress → Fix Committed
Traumflug (mah-jump-ing) on 2015-09-27
Changed in geda-project:
importance: Undecided → Medium
status: New → Fix Released
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