thermals connect too many layers

[RussNelson]

Trying to create a PCB with a ground plane. The automatically-routed thermals get placed on both sides of the board. This is fine until you try to create a power plane, at which point VCC and GND get shorted.

Here's what I did:
run pcb (git version 1.7.0.4 version 1.99z Compiled on Feb 27 2013 at 14:49:16).
File/Import Schematic (appended)
Select/Disperse all elements
Connects/Auto-route all rats
Window/Netlist
Select GND.
Click Select button.
Click Close button.
Select/Rip up selected auto-route tracks
Click on "solder" layer.
Click on THRM tool button.
Deposit a thermal on Pin 1 of U2
Click on RECT tool button.
Draw a rectangle surrounding all the parts.
Save as some junk filename.pcb
grep for "thermal" in that filename.
expect to see the first thermal(1X) and subsequent thermal(0X,1X), which is wrong.

You'll see that the thermal you placed by hand is correctly placed on only layer 1 (solder), however the thermals which were automatically placed are on layer 0 and 1 (component and solder).

[RussNelson (nelson-crynwr)]

Simpler procedure to reproduce:

run pcb (git version 1.7.0.4 version 1.99z Compiled on Feb 27 2013 at 14:49:16).
File/Import Schematic (appended)
Click on "solder" layer (very important - doesn't fail on "component" layer)
Click on RECT tool button.
Draw a rect around both components
Click on THRM tool button.
Deposit a thermal on pin 1 of R1.
Connects/Auto-route all rats
Save as /tmp/test.pcb
egrep "^Element|thermal" /tmp/test.pcb
Expect to see something like this:
Element["" "ACY400" "R2" "unknown" 3448.80mil 58.4701mm 320.00mil 53.00mil 0 100 ""]
 Pin[0.0000 0.0000 55.00mil 30.00mil 61.00mil 30.00mil "1" "1" "square,edge2,thermal(0X,1X)"]
Element["" "ACY400" "R1" "unknown" 83.3599mm 56.5787mm 320.00mil 53.00mil 0 100 ""]
 Pin[0.0000 0.0000 55.00mil 30.00mil 61.00mil 30.00mil "1" "1" "square,edge2,thermal(1X)"]

The thermal that was auto-placed on R2 is incorrectly placed on the "component" layer in addition to the correct "solder" layer.

[Chad Parker (parker-charles)]

This bug still exists in PCB 4.2.0.

Instead of inspecting the file, it's easy enough to see by subsequently drawing a rectangle over the components on the component layer after executing the provided procedure.