Incorrect DRC failure on polygon + via + therm
Bug #1047123 reported by
Ralph Loader
This bug affects 1 person
| Affects | Status | Importance | Assigned to | Milestone | |
|---|---|---|---|---|---|
| pcb |
Fix Released
|
Medium
|
Unassigned | ||
Bug Description
I found the following behaviour (more or less minimal test case attached):
1. Set DRC constraints to min spacing 0.1501mm
2. Draw two polygons (rectangles are not enough, they need to be more complex) with 0.2mm space between them. DRC passes.
3. Add a via entirely inside one polygon & connect with therm.
4. DRC now fails on insufficient clearance on the polygon.
This is with both fedora pcb-0.20110918-
In the example attached:
(1) DRC fails.
(2) Delete the via. DRC passes.
(3) Move the via into one of the rectangles. DRC passes. Despite the two rectangles having the same seperation as the polygons.
Revision history for this message
| Ralph Loader (qemu-i-deactivatedaccount) wrote | #1 |
| Changed in pcb: | |
| importance: | Undecided → Medium |
| status: | New → Confirmed |
| Changed in geda-project: | |
| importance: | Undecided → Medium |
| status: | New → Confirmed |
Revision history for this message
| Chad Parker (parker-charles) wrote | #2 |
| Changed in pcb: | |
| status: | Confirmed → Fix Released |
| Changed in geda-project: | |
| status: | Confirmed → Fix Released |
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I'm not able to reproduce this with pcb-4.1. When I run the DRC on this, I get no errors. Whatever it was it must have been fixed somewhere along the line. If the problem shows up again, please file a new bug report. Thank you.