Incorrect DRC failure on polygon + via + therm

Bug #1047123 reported by Ralph Loader on 2012-09-07
This bug affects 1 person
Affects Status Importance Assigned to Milestone
gEDA project

Bug Description

I found the following behaviour (more or less minimal test case attached):

1. Set DRC constraints to min spacing 0.1501mm
2. Draw two polygons (rectangles are not enough, they need to be more complex) with 0.2mm space between them. DRC passes.
3. Add a via entirely inside one polygon & connect with therm.
4. DRC now fails on insufficient clearance on the polygon.

This is with both fedora pcb-0.20110918-4.fc17.x86_64 and also a recent pcb built from git.

In the example attached:

(1) DRC fails.
(2) Delete the via. DRC passes.
(3) Move the via into one of the rectangles. DRC passes. Despite the two rectangles having the same seperation as the polygons.

Traumflug (mah-jump-ing) on 2015-09-06
Changed in pcb:
importance: Undecided → Medium
status: New → Confirmed
Traumflug (mah-jump-ing) on 2015-09-27
Changed in geda-project:
importance: Undecided → Medium
status: New → Confirmed
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