From f96d7867a9ae95f0c5cfa0d76e441013ffc99ac6 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Wed, 30 Mar 2011 13:17:29 -0600 Subject: [PATCH] SAUCE: OMAP4: clock: wait for module to become accessible on a clk enable On omap4, the clock f/w is missing a check for module accessebility on a call to clk enable. Since this check is already part of the omap device layer, this check at the clock framework is redundant. But since not all drivers are yet using omap device apis, and most still depend on clk framework to enable clocks, this patch seems to be needed at this point to avoid any module accessebility issues Signed-off-by: Rajendra Nayak --- arch/arm/mach-omap2/clock.c | 20 +++- arch/arm/mach-omap2/clock.h | 1 + arch/arm/mach-omap2/clock44xx_data.c | 246 +++++++++++++++++----------------- 3 files changed, 142 insertions(+), 125 deletions(-) diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 2a2f152..8a63fab 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -30,6 +30,7 @@ #include "clock.h" #include "cm2xxx_3xxx.h" +#include "cm44xx.h" #include "cm-regbits-24xx.h" #include "cm-regbits-34xx.h" @@ -41,6 +42,11 @@ u8 cpu_mask; /* Private functions */ +static void _omap4_module_wait_ready(struct clk *clk) +{ + omap4_cm_wait_module_ready(clk->enable_reg); +} + /** * _omap2_module_wait_ready - wait for an OMAP module to leave IDLE * @clk: struct clk * belonging to the module @@ -188,8 +194,12 @@ int omap2_dflt_clk_enable(struct clk *clk) __raw_writel(v, clk->enable_reg); v = __raw_readl(clk->enable_reg); /* OCP barrier */ - if (clk->ops->find_idlest) - _omap2_module_wait_ready(clk); + if (clk->ops->find_idlest) { + if (cpu_is_omap44xx()) + _omap4_module_wait_ready(clk); + else + _omap2_module_wait_ready(clk); + } return 0; } @@ -217,6 +227,12 @@ void omap2_dflt_clk_disable(struct clk *clk) /* No OCP barrier needed here since it is a disable operation */ } +const struct clkops clkops_omap4_dflt_wait = { + .enable = omap2_dflt_clk_enable, + .disable = omap2_dflt_clk_disable, + .find_idlest = omap2_clk_dflt_find_idlest, +}; + const struct clkops clkops_omap2_dflt_wait = { .enable = omap2_dflt_clk_enable, .disable = omap2_dflt_clk_disable, diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 896584e..44e2c46 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -129,6 +129,7 @@ extern u8 cpu_mask; extern const struct clkops clkops_omap2_dflt_wait; extern const struct clkops clkops_dummy; extern const struct clkops clkops_omap2_dflt; +extern const struct clkops clkops_omap4_dflt_wait; extern struct clk_functions omap2_clk_functions; extern struct clk *vclk, *sclk; diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index 95f2c4c..b27bbf5 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -53,7 +53,7 @@ static struct clk extalt_clkin_ck = { static struct clk pad_clks_ck = { .name = "pad_clks_ck", .rate = 12000000, - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_CLKSEL_ABE, .enable_bit = OMAP4430_PAD_CLKS_GATE_SHIFT, }; @@ -73,7 +73,7 @@ static struct clk secure_32k_clk_src_ck = { static struct clk slimbus_clk = { .name = "slimbus_clk", .rate = 12000000, - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_CLKSEL_ABE, .enable_bit = OMAP4430_SLIMBUS_CLK_GATE_SHIFT, }; @@ -618,7 +618,7 @@ static struct clk dpll_core_m3x2_ck = { .clksel = dpll_core_m6x2_div, .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_CORE, .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_DIV_M3_DPLL_CORE, .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, .recalc = &omap2_clksel_recalc, @@ -873,7 +873,7 @@ static struct clk dpll_per_m3x2_ck = { .clksel = dpll_per_m2x2_div, .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_PER, .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_DIV_M3_DPLL_PER, .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, .recalc = &omap2_clksel_recalc, @@ -1350,7 +1350,7 @@ static struct clk syc_clk_div_ck = { static struct clk aes1_fck = { .name = "aes1_fck", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L4SEC_AES1_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l4_secure_clkdm", @@ -1360,7 +1360,7 @@ static struct clk aes1_fck = { static struct clk aes2_fck = { .name = "aes2_fck", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L4SEC_AES2_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l4_secure_clkdm", @@ -1370,7 +1370,7 @@ static struct clk aes2_fck = { static struct clk aess_fck = { .name = "aess_fck", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "abe_clkdm", @@ -1380,7 +1380,7 @@ static struct clk aess_fck = { static struct clk bandgap_fclk = { .name = "bandgap_fclk", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, .clkdm_name = "l4_wkup_clkdm", @@ -1390,7 +1390,7 @@ static struct clk bandgap_fclk = { static struct clk des3des_fck = { .name = "des3des_fck", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l4_secure_clkdm", @@ -1431,7 +1431,7 @@ static struct clk dmic_fck = { .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .recalc = &omap2_clksel_recalc, .enable_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, @@ -1440,7 +1440,7 @@ static struct clk dmic_fck = { static struct clk dsp_fck = { .name = "dsp_fck", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, .clkdm_name = "tesla_clkdm", @@ -1450,7 +1450,7 @@ static struct clk dsp_fck = { static struct clk dss_sys_clk = { .name = "dss_sys_clk", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT, .clkdm_name = "l3_dss_clkdm", @@ -1460,7 +1460,7 @@ static struct clk dss_sys_clk = { static struct clk dss_tv_clk = { .name = "dss_tv_clk", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, .clkdm_name = "l3_dss_clkdm", @@ -1470,7 +1470,7 @@ static struct clk dss_tv_clk = { static struct clk dss_dss_clk = { .name = "dss_dss_clk", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT, .clkdm_name = "l3_dss_clkdm", @@ -1480,7 +1480,7 @@ static struct clk dss_dss_clk = { static struct clk dss_48mhz_clk = { .name = "dss_48mhz_clk", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT, .clkdm_name = "l3_dss_clkdm", @@ -1490,7 +1490,7 @@ static struct clk dss_48mhz_clk = { static struct clk dss_fck = { .name = "dss_fck", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l3_dss_clkdm", @@ -1500,7 +1500,7 @@ static struct clk dss_fck = { static struct clk efuse_ctrl_cust_fck = { .name = "efuse_ctrl_cust_fck", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l4_cefuse_clkdm", @@ -1510,7 +1510,7 @@ static struct clk efuse_ctrl_cust_fck = { static struct clk emif1_fck = { .name = "emif1_fck", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, .flags = ENABLE_ON_INIT, @@ -1521,7 +1521,7 @@ static struct clk emif1_fck = { static struct clk emif2_fck = { .name = "emif2_fck", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, .flags = ENABLE_ON_INIT, @@ -1542,7 +1542,7 @@ static struct clk fdif_fck = { .clksel = fdif_fclk_div, .clksel_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_FCLK_MASK, - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .recalc = &omap2_clksel_recalc, .round_rate = &omap2_clksel_round_rate, .set_rate = &omap2_clksel_set_rate, @@ -1553,7 +1553,7 @@ static struct clk fdif_fck = { static struct clk fpka_fck = { .name = "fpka_fck", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l4_secure_clkdm", @@ -1563,7 +1563,7 @@ static struct clk fpka_fck = { static struct clk gpio1_dbclk = { .name = "gpio1_dbclk", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, .clkdm_name = "l4_wkup_clkdm", @@ -1573,7 +1573,7 @@ static struct clk gpio1_dbclk = { static struct clk gpio1_ick = { .name = "gpio1_ick", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, .clkdm_name = "l4_wkup_clkdm", @@ -1583,7 +1583,7 @@ static struct clk gpio1_ick = { static struct clk gpio2_dbclk = { .name = "gpio2_dbclk", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, .clkdm_name = "l4_per_clkdm", @@ -1593,7 +1593,7 @@ static struct clk gpio2_dbclk = { static struct clk gpio2_ick = { .name = "gpio2_ick", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, .clkdm_name = "l4_per_clkdm", @@ -1603,7 +1603,7 @@ static struct clk gpio2_ick = { static struct clk gpio3_dbclk = { .name = "gpio3_dbclk", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, .clkdm_name = "l4_per_clkdm", @@ -1613,7 +1613,7 @@ static struct clk gpio3_dbclk = { static struct clk gpio3_ick = { .name = "gpio3_ick", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, .clkdm_name = "l4_per_clkdm", @@ -1623,7 +1623,7 @@ static struct clk gpio3_ick = { static struct clk gpio4_dbclk = { .name = "gpio4_dbclk", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, .clkdm_name = "l4_per_clkdm", @@ -1633,7 +1633,7 @@ static struct clk gpio4_dbclk = { static struct clk gpio4_ick = { .name = "gpio4_ick", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, .clkdm_name = "l4_per_clkdm", @@ -1643,7 +1643,7 @@ static struct clk gpio4_ick = { static struct clk gpio5_dbclk = { .name = "gpio5_dbclk", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, .clkdm_name = "l4_per_clkdm", @@ -1653,7 +1653,7 @@ static struct clk gpio5_dbclk = { static struct clk gpio5_ick = { .name = "gpio5_ick", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, .clkdm_name = "l4_per_clkdm", @@ -1663,7 +1663,7 @@ static struct clk gpio5_ick = { static struct clk gpio6_dbclk = { .name = "gpio6_dbclk", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, .clkdm_name = "l4_per_clkdm", @@ -1673,7 +1673,7 @@ static struct clk gpio6_dbclk = { static struct clk gpio6_ick = { .name = "gpio6_ick", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, .clkdm_name = "l4_per_clkdm", @@ -1683,7 +1683,7 @@ static struct clk gpio6_ick = { static struct clk gpmc_ick = { .name = "gpmc_ick", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L3_2_GPMC_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, .clkdm_name = "l3_2_clkdm", @@ -1705,7 +1705,7 @@ static struct clk gpu_fck = { .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_SGX_FCLK_MASK, - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .recalc = &omap2_clksel_recalc, .enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, @@ -1714,7 +1714,7 @@ static struct clk gpu_fck = { static struct clk hdq1w_fck = { .name = "hdq1w_fck", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l4_per_clkdm", @@ -1734,7 +1734,7 @@ static struct clk hsi_fck = { .clksel = hsi_fclk_div, .clksel_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_24_25_MASK, - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .recalc = &omap2_clksel_recalc, .round_rate = &omap2_clksel_round_rate, .set_rate = &omap2_clksel_set_rate, @@ -1745,7 +1745,7 @@ static struct clk hsi_fck = { static struct clk i2c1_fck = { .name = "i2c1_fck", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l4_per_clkdm", @@ -1755,7 +1755,7 @@ static struct clk i2c1_fck = { static struct clk i2c2_fck = { .name = "i2c2_fck", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l4_per_clkdm", @@ -1765,7 +1765,7 @@ static struct clk i2c2_fck = { static struct clk i2c3_fck = { .name = "i2c3_fck", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l4_per_clkdm", @@ -1775,7 +1775,7 @@ static struct clk i2c3_fck = { static struct clk i2c4_fck = { .name = "i2c4_fck", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l4_per_clkdm", @@ -1785,7 +1785,7 @@ static struct clk i2c4_fck = { static struct clk ipu_fck = { .name = "ipu_fck", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, .clkdm_name = "ducati_clkdm", @@ -1795,7 +1795,7 @@ static struct clk ipu_fck = { static struct clk iss_ctrlclk = { .name = "iss_ctrlclk", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT, .clkdm_name = "iss_clkdm", @@ -1805,7 +1805,7 @@ static struct clk iss_ctrlclk = { static struct clk iss_fck = { .name = "iss_fck", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "iss_clkdm", @@ -1815,7 +1815,7 @@ static struct clk iss_fck = { static struct clk iva_fck = { .name = "iva_fck", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, .clkdm_name = "ivahd_clkdm", @@ -1825,7 +1825,7 @@ static struct clk iva_fck = { static struct clk kbd_fck = { .name = "kbd_fck", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l4_wkup_clkdm", @@ -1835,7 +1835,7 @@ static struct clk kbd_fck = { static struct clk l3_instr_ick = { .name = "l3_instr_ick", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, .clkdm_name = "l3_instr_clkdm", @@ -1846,7 +1846,7 @@ static struct clk l3_instr_ick = { static struct clk l3_main_3_ick = { .name = "l3_main_3_ick", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, .clkdm_name = "l3_instr_clkdm", @@ -1881,7 +1881,7 @@ static struct clk mcasp_fck = { .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .recalc = &omap2_clksel_recalc, .enable_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, @@ -1914,7 +1914,7 @@ static struct clk mcbsp1_fck = { .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .recalc = &omap2_clksel_recalc, .enable_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, @@ -1947,7 +1947,7 @@ static struct clk mcbsp2_fck = { .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .recalc = &omap2_clksel_recalc, .enable_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, @@ -1980,7 +1980,7 @@ static struct clk mcbsp3_fck = { .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .recalc = &omap2_clksel_recalc, .enable_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, @@ -2012,7 +2012,7 @@ static struct clk mcbsp4_fck = { .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_SOURCE_24_24_MASK, - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .recalc = &omap2_clksel_recalc, .enable_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, @@ -2021,7 +2021,7 @@ static struct clk mcbsp4_fck = { static struct clk mcpdm_fck = { .name = "mcpdm_fck", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "abe_clkdm", @@ -2031,7 +2031,7 @@ static struct clk mcpdm_fck = { static struct clk mcspi1_fck = { .name = "mcspi1_fck", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l4_per_clkdm", @@ -2041,7 +2041,7 @@ static struct clk mcspi1_fck = { static struct clk mcspi2_fck = { .name = "mcspi2_fck", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l4_per_clkdm", @@ -2051,7 +2051,7 @@ static struct clk mcspi2_fck = { static struct clk mcspi3_fck = { .name = "mcspi3_fck", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l4_per_clkdm", @@ -2061,7 +2061,7 @@ static struct clk mcspi3_fck = { static struct clk mcspi4_fck = { .name = "mcspi4_fck", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l4_per_clkdm", @@ -2077,7 +2077,7 @@ static struct clk mmc1_fck = { .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .recalc = &omap2_clksel_recalc, .enable_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, @@ -2092,7 +2092,7 @@ static struct clk mmc2_fck = { .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .recalc = &omap2_clksel_recalc, .enable_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, @@ -2101,7 +2101,7 @@ static struct clk mmc2_fck = { static struct clk mmc3_fck = { .name = "mmc3_fck", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l4_per_clkdm", @@ -2111,7 +2111,7 @@ static struct clk mmc3_fck = { static struct clk mmc4_fck = { .name = "mmc4_fck", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l4_per_clkdm", @@ -2121,7 +2121,7 @@ static struct clk mmc4_fck = { static struct clk mmc5_fck = { .name = "mmc5_fck", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l4_per_clkdm", @@ -2131,7 +2131,7 @@ static struct clk mmc5_fck = { static struct clk ocp2scp_usb_phy_phy_48m = { .name = "ocp2scp_usb_phy_phy_48m", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, .clkdm_name = "l3_init_clkdm", @@ -2141,7 +2141,7 @@ static struct clk ocp2scp_usb_phy_phy_48m = { static struct clk ocp2scp_usb_phy_ick = { .name = "ocp2scp_usb_phy_ick", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, .clkdm_name = "l3_init_clkdm", @@ -2151,7 +2151,7 @@ static struct clk ocp2scp_usb_phy_ick = { static struct clk ocp_wp_noc_ick = { .name = "ocp_wp_noc_ick", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, .clkdm_name = "l3_instr_clkdm", @@ -2162,7 +2162,7 @@ static struct clk ocp_wp_noc_ick = { static struct clk rng_ick = { .name = "rng_ick", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L4SEC_RNG_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, .clkdm_name = "l4_secure_clkdm", @@ -2172,7 +2172,7 @@ static struct clk rng_ick = { static struct clk sha2md5_fck = { .name = "sha2md5_fck", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l4_secure_clkdm", @@ -2182,7 +2182,7 @@ static struct clk sha2md5_fck = { static struct clk sl2if_ick = { .name = "sl2if_ick", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, .clkdm_name = "ivahd_clkdm", @@ -2192,7 +2192,7 @@ static struct clk sl2if_ick = { static struct clk slimbus1_fclk_1 = { .name = "slimbus1_fclk_1", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_FCLK1_SHIFT, .clkdm_name = "abe_clkdm", @@ -2202,7 +2202,7 @@ static struct clk slimbus1_fclk_1 = { static struct clk slimbus1_fclk_0 = { .name = "slimbus1_fclk_0", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_FCLK0_SHIFT, .clkdm_name = "abe_clkdm", @@ -2212,7 +2212,7 @@ static struct clk slimbus1_fclk_0 = { static struct clk slimbus1_fclk_2 = { .name = "slimbus1_fclk_2", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_FCLK2_SHIFT, .clkdm_name = "abe_clkdm", @@ -2222,7 +2222,7 @@ static struct clk slimbus1_fclk_2 = { static struct clk slimbus1_slimbus_clk = { .name = "slimbus1_slimbus_clk", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, .clkdm_name = "abe_clkdm", @@ -2232,7 +2232,7 @@ static struct clk slimbus1_slimbus_clk = { static struct clk slimbus1_fck = { .name = "slimbus1_fck", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "abe_clkdm", @@ -2242,7 +2242,7 @@ static struct clk slimbus1_fck = { static struct clk slimbus2_fclk_1 = { .name = "slimbus2_fclk_1", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, .clkdm_name = "l4_per_clkdm", @@ -2252,7 +2252,7 @@ static struct clk slimbus2_fclk_1 = { static struct clk slimbus2_fclk_0 = { .name = "slimbus2_fclk_0", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT, .clkdm_name = "l4_per_clkdm", @@ -2262,7 +2262,7 @@ static struct clk slimbus2_fclk_0 = { static struct clk slimbus2_slimbus_clk = { .name = "slimbus2_slimbus_clk", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, .clkdm_name = "l4_per_clkdm", @@ -2272,7 +2272,7 @@ static struct clk slimbus2_slimbus_clk = { static struct clk slimbus2_fck = { .name = "slimbus2_fck", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l4_per_clkdm", @@ -2282,7 +2282,7 @@ static struct clk slimbus2_fck = { static struct clk smartreflex_core_fck = { .name = "smartreflex_core_fck", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l4_ao_clkdm", @@ -2292,7 +2292,7 @@ static struct clk smartreflex_core_fck = { static struct clk smartreflex_iva_fck = { .name = "smartreflex_iva_fck", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l4_ao_clkdm", @@ -2302,7 +2302,7 @@ static struct clk smartreflex_iva_fck = { static struct clk smartreflex_mpu_fck = { .name = "smartreflex_mpu_fck", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l4_ao_clkdm", @@ -2318,7 +2318,7 @@ static struct clk timer1_fck = { .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .recalc = &omap2_clksel_recalc, .enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, @@ -2333,7 +2333,7 @@ static struct clk timer10_fck = { .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .recalc = &omap2_clksel_recalc, .enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, @@ -2348,7 +2348,7 @@ static struct clk timer11_fck = { .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .recalc = &omap2_clksel_recalc, .enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, @@ -2363,7 +2363,7 @@ static struct clk timer2_fck = { .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .recalc = &omap2_clksel_recalc, .enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, @@ -2378,7 +2378,7 @@ static struct clk timer3_fck = { .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .recalc = &omap2_clksel_recalc, .enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, @@ -2393,7 +2393,7 @@ static struct clk timer4_fck = { .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .recalc = &omap2_clksel_recalc, .enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, @@ -2414,7 +2414,7 @@ static struct clk timer5_fck = { .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .recalc = &omap2_clksel_recalc, .enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, @@ -2429,7 +2429,7 @@ static struct clk timer6_fck = { .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .recalc = &omap2_clksel_recalc, .enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, @@ -2444,7 +2444,7 @@ static struct clk timer7_fck = { .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .recalc = &omap2_clksel_recalc, .enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, @@ -2459,7 +2459,7 @@ static struct clk timer8_fck = { .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .recalc = &omap2_clksel_recalc, .enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, @@ -2474,7 +2474,7 @@ static struct clk timer9_fck = { .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .recalc = &omap2_clksel_recalc, .enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, @@ -2483,7 +2483,7 @@ static struct clk timer9_fck = { static struct clk uart1_fck = { .name = "uart1_fck", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l4_per_clkdm", @@ -2493,7 +2493,7 @@ static struct clk uart1_fck = { static struct clk uart2_fck = { .name = "uart2_fck", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l4_per_clkdm", @@ -2503,7 +2503,7 @@ static struct clk uart2_fck = { static struct clk uart3_fck = { .name = "uart3_fck", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l4_per_clkdm", @@ -2513,7 +2513,7 @@ static struct clk uart3_fck = { static struct clk uart4_fck = { .name = "uart4_fck", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l4_per_clkdm", @@ -2523,7 +2523,7 @@ static struct clk uart4_fck = { static struct clk usb_host_fs_fck = { .name = "usb_host_fs_fck", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l3_init_clkdm", @@ -2550,7 +2550,7 @@ static struct clk utmi_p1_gfclk = { static struct clk usb_host_hs_utmi_p1_clk = { .name = "usb_host_hs_utmi_p1_clk", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT, .clkdm_name = "l3_init_clkdm", @@ -2577,7 +2577,7 @@ static struct clk utmi_p2_gfclk = { static struct clk usb_host_hs_utmi_p2_clk = { .name = "usb_host_hs_utmi_p2_clk", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT, .clkdm_name = "l3_init_clkdm", @@ -2587,7 +2587,7 @@ static struct clk usb_host_hs_utmi_p2_clk = { static struct clk usb_host_hs_utmi_p3_clk = { .name = "usb_host_hs_utmi_p3_clk", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT, .clkdm_name = "l3_init_clkdm", @@ -2597,7 +2597,7 @@ static struct clk usb_host_hs_utmi_p3_clk = { static struct clk usb_host_hs_hsic480m_p1_clk = { .name = "usb_host_hs_hsic480m_p1_clk", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT, .clkdm_name = "l3_init_clkdm", @@ -2607,7 +2607,7 @@ static struct clk usb_host_hs_hsic480m_p1_clk = { static struct clk usb_host_hs_hsic60m_p1_clk = { .name = "usb_host_hs_hsic60m_p1_clk", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT, .clkdm_name = "l3_init_clkdm", @@ -2617,7 +2617,7 @@ static struct clk usb_host_hs_hsic60m_p1_clk = { static struct clk usb_host_hs_hsic60m_p2_clk = { .name = "usb_host_hs_hsic60m_p2_clk", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT, .clkdm_name = "l3_init_clkdm", @@ -2627,7 +2627,7 @@ static struct clk usb_host_hs_hsic60m_p2_clk = { static struct clk usb_host_hs_hsic480m_p2_clk = { .name = "usb_host_hs_hsic480m_p2_clk", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT, .clkdm_name = "l3_init_clkdm", @@ -2637,7 +2637,7 @@ static struct clk usb_host_hs_hsic480m_p2_clk = { static struct clk usb_host_hs_func48mclk = { .name = "usb_host_hs_func48mclk", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT, .clkdm_name = "l3_init_clkdm", @@ -2647,7 +2647,7 @@ static struct clk usb_host_hs_func48mclk = { static struct clk usb_host_hs_fck = { .name = "usb_host_hs_fck", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l3_init_clkdm", @@ -2674,7 +2674,7 @@ static struct clk otg_60m_gfclk = { static struct clk usb_otg_hs_xclk = { .name = "usb_otg_hs_xclk", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_XCLK_SHIFT, .clkdm_name = "l3_init_clkdm", @@ -2684,7 +2684,7 @@ static struct clk usb_otg_hs_xclk = { static struct clk usb_otg_hs_ick = { .name = "usb_otg_hs_ick", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, .clkdm_name = "l3_init_clkdm", @@ -2694,7 +2694,7 @@ static struct clk usb_otg_hs_ick = { static struct clk usb_phy_cm_clk32k = { .name = "usb_phy_cm_clk32k", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_ALWON_USBPHY_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_CLK32K_SHIFT, .clkdm_name = "l4_ao_clkdm", @@ -2704,7 +2704,7 @@ static struct clk usb_phy_cm_clk32k = { static struct clk usb_tll_hs_usb_ch2_clk = { .name = "usb_tll_hs_usb_ch2_clk", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT, .clkdm_name = "l3_init_clkdm", @@ -2714,7 +2714,7 @@ static struct clk usb_tll_hs_usb_ch2_clk = { static struct clk usb_tll_hs_usb_ch0_clk = { .name = "usb_tll_hs_usb_ch0_clk", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT, .clkdm_name = "l3_init_clkdm", @@ -2724,7 +2724,7 @@ static struct clk usb_tll_hs_usb_ch0_clk = { static struct clk usb_tll_hs_usb_ch1_clk = { .name = "usb_tll_hs_usb_ch1_clk", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT, .clkdm_name = "l3_init_clkdm", @@ -2734,7 +2734,7 @@ static struct clk usb_tll_hs_usb_ch1_clk = { static struct clk usb_tll_hs_ick = { .name = "usb_tll_hs_ick", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, .clkdm_name = "l3_init_clkdm", @@ -2767,7 +2767,7 @@ static struct clk usim_ck = { static struct clk usim_fclk = { .name = "usim_fclk", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, .enable_bit = OMAP4430_OPTFCLKEN_FCLK_SHIFT, .clkdm_name = "l4_wkup_clkdm", @@ -2777,7 +2777,7 @@ static struct clk usim_fclk = { static struct clk usim_fck = { .name = "usim_fck", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, .clkdm_name = "l4_wkup_clkdm", @@ -2787,7 +2787,7 @@ static struct clk usim_fck = { static struct clk wd_timer2_fck = { .name = "wd_timer2_fck", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l4_wkup_clkdm", @@ -2797,7 +2797,7 @@ static struct clk wd_timer2_fck = { static struct clk wd_timer3_fck = { .name = "wd_timer3_fck", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .enable_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "abe_clkdm", @@ -2853,7 +2853,7 @@ static struct clk auxclk0_ck = { .name = "auxclk0_ck", .parent = &sys_clkin_ck, .init = &omap2_init_clksel_parent, - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .clksel = auxclk_sel, .clksel_reg = OMAP4_SCRM_AUXCLK0, .clksel_mask = OMAP4_SRCSELECT_MASK, @@ -2866,7 +2866,7 @@ static struct clk auxclk1_ck = { .name = "auxclk1_ck", .parent = &sys_clkin_ck, .init = &omap2_init_clksel_parent, - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .clksel = auxclk_sel, .clksel_reg = OMAP4_SCRM_AUXCLK1, .clksel_mask = OMAP4_SRCSELECT_MASK, @@ -2879,7 +2879,7 @@ static struct clk auxclk2_ck = { .name = "auxclk2_ck", .parent = &sys_clkin_ck, .init = &omap2_init_clksel_parent, - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .clksel = auxclk_sel, .clksel_reg = OMAP4_SCRM_AUXCLK2, .clksel_mask = OMAP4_SRCSELECT_MASK, @@ -2891,7 +2891,7 @@ static struct clk auxclk3_ck = { .name = "auxclk3_ck", .parent = &sys_clkin_ck, .init = &omap2_init_clksel_parent, - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .clksel = auxclk_sel, .clksel_reg = OMAP4_SCRM_AUXCLK3, .clksel_mask = OMAP4_SRCSELECT_MASK, @@ -2904,7 +2904,7 @@ static struct clk auxclk4_ck = { .name = "auxclk4_ck", .parent = &sys_clkin_ck, .init = &omap2_init_clksel_parent, - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .clksel = auxclk_sel, .clksel_reg = OMAP4_SCRM_AUXCLK4, .clksel_mask = OMAP4_SRCSELECT_MASK, @@ -2917,7 +2917,7 @@ static struct clk auxclk5_ck = { .name = "auxclk5_ck", .parent = &sys_clkin_ck, .init = &omap2_init_clksel_parent, - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap4_dflt_wait, .clksel = auxclk_sel, .clksel_reg = OMAP4_SCRM_AUXCLK5, .clksel_mask = OMAP4_SRCSELECT_MASK, -- 1.7.1