Improve hidden pin behavior?

[Special LIU]

System : scientific linux 6.0, X86_64
KiCAD version : (1) Pre-build rpm from EPEL, 2011-01-28 BZR 2765 stable
                          (2) 2011-0708 BZR-3044 -stable, build from source code

Both version generate same wrong result.

While system use multi-voltage for digital component, annotate and netlist writer generate
wrong result, the ERC will failure and wrong netlist generated.

How to re-produce:
      (1) open eeschema with a new design.
      (2) make Show Hidden Pin ON to see hidden power pin
      (3) place two 7404 gate from 74xx library,
      (4) 7404 gate 1, vcc connect to Power A (+5V, for example)
      (5) 7404 gate 2, vcc connect to Power B (+3.3V for example)
      (6) make annotate, 7404 gate 1 & 7404 gate 2 gets same U1
      (7) run ERC(with default option) got "Conflict problem bewteen pins (power)"
      (8) Annotate error, because two 7404 gate from different power should generate U1 & U2 , not only U1
      (9) So, the netlist will be wrong, beacause two different power source connected togeger, and only one power net shows on netlist file.
      (10) if on step 6, we manual annotate 7404 gate 1 as U1, 7404 gate 2 as U2, run ERC and netlist also wrong

When use KiCAD to design signle-power system, everything works fine, but when we design a multi-voltage system, the eeschema generate wrong netlist.

Both error (annotate & netlist writer) should be same bug in eeschema, and should be modify with following:

When Annotate:
   (1) if hidden power pin manual connected to other net then go step 2, else original eeschema work
   (2) checked power pin connected net name, same net name will be same device else was different device

When Write Netlist:
   (1) if hidden power pin manual connected to other net name (+5V, for examples), then net name change to the name connected not the original name.

Work Around:
   Currently, we create ourself library for multi-voltage design, for examples : 74XX with power name VCC, 74XX_3V3 with power name 3V3 .

[alias 5000 (alias5000)]

In digital systems multiple voltage levels are not uncommon. The stated work around is not a clean solution. Wouldn't it be better to not make VCC and GND power pins in the 74xx library (and only have those pins on one unit as a consequence)?
Then the user could decide on how to use those connections.

[Chris Pavlina (pavlina-chris)]

The correct decision is to recognize that hidden, automatically-connected power pins are a nasty relic of the mostly-TTL 70s and 80s and have no place in a component library in the 21st century. Put real power pins on them. Use a separate unit for the power pins to allow the power delivery to be done separately, or even on a different page ("power delivery" schematic pages are not uncommon), but don't bloody hide them or make them connect themselves automatically!

[Chris Pavlina (pavlina-chris)]

Maybe this is something we could look at changing during the development of the new eeschema file format? The current hidden pin behavior, whether or not you like hidden pins, sucks. It would be nice if hidden pins could be manually made visible (per part, and persistently), and when connections are made to them, this should cancel the auto-connect behavior. IMHO.

[Daniel Silverstone (dsilvers)]

Another option would be to take a leaf out of Mentor's book and allow parts to contain net-rename blocks.

Essentially one (or more) of the gates of a component carry a special text block which is of a form similar to:

  VCC=3.3v
  GND=AGND

Where the left hand of the equality is the name given to the hidden power pin, and the right hand of the equality is
the net on the sheet which it magically connects to.

This (a) makes the hidden-pins more obvious since each such component carries a rename block visibly on the sheet, (b) makes it possible to (for example) have individual power wells more easily, and (c) means we won't end up with a proliferation of parts each of which carrying a different hidden pin name for the power supply.

Sometimes it's good to have the individual power pins listed (particularly if the component has very odd decoupling requirements) but more often than not, it's just as easy, or better, to have hidden pins and a net-rename block. It's a feature of Mentor I miss a lot in Kicad.

[KiCad Janitor (kicad-janitor)]

KiCad bug tracker has moved to Gitlab. This report is now available here: https://gitlab.com/kicad/code/kicad/-/issues/1961