DRC does not test pad drill minimum size

[David Pearce]

Pre-5.1.5 Jenkins-441 on Windows 64 bit

A trivial test project with 0.3mm drill vias
The DRC is set to a minimum via drill of 0.4mm, but fails to warn about the 0.3mm vias

Application: KiCad
Version: (5.1.4-122-gb67acd5ea)-1, release build
Libraries:
    wxWidgets 3.0.4
    libcurl/7.66.0 OpenSSL/1.1.1d (Schannel) zlib/1.2.11 brotli/1.0.7 libidn2/2.2.0 libpsl/0.21.0 (+libidn2/2.1.1) nghttp2/1.39.2
Platform: Windows 8 (build 9200), 64-bit edition, 64 bit, Little endian, wxMSW
Build Info:
    wxWidgets: 3.0.4 (wchar_t,wx containers,compatible with 2.8)
    Boost: 1.71.0
    OpenCASCADE Community Edition: 6.9.1
    Curl: 7.66.0
    Compiler: GCC 9.2.0 with C++ ABI 1013

Build settings:
    USE_WX_GRAPHICS_CONTEXT=OFF
    USE_WX_OVERLAY=OFF
    KICAD_SCRIPTING=ON
    KICAD_SCRIPTING_MODULES=ON
    KICAD_SCRIPTING_PYTHON3=OFF
    KICAD_SCRIPTING_WXPYTHON=ON
    KICAD_SCRIPTING_WXPYTHON_PHOENIX=OFF
    KICAD_SCRIPTING_ACTION_MENU=ON
    BUILD_GITHUB_PLUGIN=ON
    KICAD_USE_OCE=ON
    KICAD_USE_OCC=OFF
    KICAD_SPICE=ON

[David Pearce (halzia)]

My Minimum via size: 0.4mm
Also there is no tool tip for Minimum via size, while the uVia line does have one.

Forum discussion here
https://forum.kicad.info/t/does-drc-check-the-footprint-pads-for-minimum-drill-size/19561

[David Pearce (halzia)]

Further experimentation has shown two problems:
1) that KiCad is not treating a thermal via in a EP pad as a drilled via, which it is
2) that the DRC dialog need a clarifying tool tip that the Minimum via size is PAD diameter

[jean-pierre charras (jp-charras)]

There is a misunderstanding here:
In Kicad vias and pads are *fully different entities*:
A pad is found inside a footprint.
A via is a "track segment" between 2 layers.

PTH pads and vias are not equivalent in many cases.

Perhaps they are equivalent in some other ECAD, but not in Kicad.

[David Pearce (halzia)]

The end result though is unexpected 0.2mm holes that are not detected by the DRC.
The only way to find this is by opening the .drl file with a text editor

[Wayne Stambaugh (stambaughw)]

I just tested your sample test board and there are no vias with a 0.2mm drill. They are all 0.3mm drills which passes the DRC. If I change the minimum via drill size in the board configuration to 0.31mm, the DRC correctly detects the 0.3mm via drills as DRC violations. Are you sure this isn't cockpit error on your part? There is no minimum via drill setting in the DRC dialog. There is a minimum via size (not drill) setting in the DRC dialog but this also works as expected as well.

[Walt Holm (waltholm)]

Hi Wayne:

I was the person who brought this up originally on the forum; see the link David posted above for context. The reason I didn't file a bug report immediately is that, being a new KiCAD user, I wasn't sure that I was using DRC correctly.

I believe that there was some initial misunderstanding on David's part, so the bugtracker title and the test provided don't represent what I originally noted.

The original forum issue was that KiCAD DRC does not appear to check the sizing of pad drills. The DRC dialogs appear to be literally correct- there is a minimum limit for via drills, but nothing for pad drills. This became an issue in a board I designed because the footprint thermal vias were implemented as through-hole pads, and the drill for these was smaller than what the board-house allowed.

Copied from the forum:

Steps to re-create:

1.) Create a test project. Open the pcb, draw a board outline.
2.) Place a footprint- Package_SO: SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm_ThermalVias
3.) Check that Board Setup / Design Rules / Minimum Via Drill is set to 0.3mm
4.) Note that the thermal vias on the footprint are 0.2mm
5.) Run DRC. No errors are reported.
6.) Place a via on the board with a drill diameter of 0.2mm
7.) Run DRC again. An error for “Via Drill too small” is noted.

Version Info from my system:

Application: KiCad
Version: (5.1.4)-1, release build
Libraries:
    wxWidgets 3.0.4
    libcurl/7.61.1 OpenSSL/1.1.1 (WinSSL) zlib/1.2.11 brotli/1.0.6 libidn2/2.0.5 libpsl/0.20.2 (+libidn2/2.0.5) nghttp2/1.34.0
Platform: Windows 7 (build 7601, Service Pack 1), 64-bit edition, 64 bit, Little endian, wxMSW
Build Info:
    wxWidgets: 3.0.4 (wchar_t,wx containers,compatible with 2.8)
    Boost: 1.68.0
    OpenCASCADE Community Edition: 6.9.1
    Curl: 7.61.1
    Compiler: GCC 8.2.0 with C++ ABI 1013

Build settings:
    USE_WX_GRAPHICS_CONTEXT=OFF
    USE_WX_OVERLAY=OFF
    KICAD_SCRIPTING=ON
    KICAD_SCRIPTING_MODULES=ON
    KICAD_SCRIPTING_PYTHON3=OFF
    KICAD_SCRIPTING_WXPYTHON=ON
    KICAD_SCRIPTING_WXPYTHON_PHOENIX=OFF
    KICAD_SCRIPTING_ACTION_MENU=ON
    BUILD_GITHUB_PLUGIN=ON
    KICAD_USE_OCE=ON
    KICAD_USE_OCC=OFF
    KICAD_SPICE=ON

[Wayne Stambaugh (stambaughw)]

The footprint in question technically does not have vias embedded in it. They are actually through hole pads which are not treated the same as JP explained. I guess the $10K question is should we treat through hole pad drills the same as via drills. My gut tells me no and that this should be a separate limit setting for the DRC to check. Unfortunately that would require a board file change along with the DRC algorithm to test all through pads for minimum pad drill violations. Either that or some global minimum drill size that applies to all drill diameters.

[Walt Holm (waltholm)]

Speaking as an end user, is there some context where a pad drill minimum would need to be different from a via drill minimum in DRC? I'm looking at is from the standpoint of the resulting Excellon drill file, are there other reasons to check minimum drill size?

Also, if this is going to sit in the "wishlist" hopper for a while, I'd suggest that the bug title be changed to something more appropriate, maybe to something like "DRC does not test pad drill minimum size". Could the original poster (David) or some moderator here please do so? Thanks.

-W

[KiCad Janitor (kicad-janitor)]

KiCad bug tracker has moved to Gitlab. This report is now available here: https://gitlab.com/kicad/code/kicad/-/issues/2528